74AC11244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998 D D D D D D EPIC (Enhanced-Performance Implanted CMOS ) 1-µm Process 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic DIPs (NT) DB, DW, NT, OR PW PACKAGE (TOP VIEW) 1Y1 1Y2 1Y3 1Y4 GND GND GND GND 2Y1 2Y2 2Y3 2Y4 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 1OE 1A1 1A2 1A3 1A4 VCC VCC 2A1 2A2 2A3 2A4 2OE description The 74AC11244 is an octal buffer or line driver designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as two 4-bit buffers or one 8-bit buffer, with active-low output-enable (OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The 74AC11244 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each driver) INPUTS OE A OUTPUT Y L H H L L L H X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 74AC11244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998 logic symbol† 1OE 1A1 1A2 1A3 1A4 24 2OE EN 23 1 22 2 21 3 20 4 1Y1 2A1 1Y2 2A2 1Y3 1Y4 2A3 2A4 13 EN 17 9 16 10 15 11 14 12 2Y1 2Y2 2Y3 2Y4 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 24 2OE 23 22 21 20 1 2 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 13 17 9 16 10 15 11 14 12 3 4 2Y1 2Y2 2Y3 2Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 74AC11244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998 recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level input voltage VCC = 3 V VCC = 4.5 V MIN NOM MAX 3 5 5.5 0.9 Low-level input voltage VI VO Input voltage 0 Output voltage 0 IOH High-level output current ∆t/∆v Input transition rise or fall rate V 3.85 VIL Low-level output current V 2.1 3.15 VCC = 5.5 V VCC = 3 V IOL UNIT VCC = 4.5 V VCC = 5.5 V 1.35 V 1.65 VCC VCC VCC = 3 V VCC = 4.5 V V V –4 –24 VCC = 5.5 V VCC = 3 V –24 VCC = 4.5 V VCC = 5.5 V 24 mA 12 mA 24 0 10 ns/V TA Operating free-air temperature –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 µA VOH TA = 25°C MIN TYP MAX MIN 3V 2.9 2.9 4.5 V 4.4 4.4 5.5 V 5.4 5.4 3V 2.58 2.48 4.5 V 3.94 3.8 IOL = –24 24 mA A 5.5 V 4.94 IOH = –75 mA† 5.5 V IOH = –4 mA IOL = 50 µA VOL VCC IOL = 12 mA IOL = 24 mA MAX UNIT V 4.8 3.85 3V 0.1 0.1 4.5 V 0.1 0.1 5.5 V 0.1 0.1 3V 0.36 0.44 4.5 V 0.36 0.44 5.5 V 0.36 0.44 V IOL = 75 mA† 5.5 V II IOZ VI = VCC or GND VO = VCC or GND 5.5 V ±0.1 ±1 µA 5.5 V ±0.5 ±5 µA ICC Ci VI = VCC or GND, VI = VCC or GND 8 80 µA IO = 0 1.65 5.5 V 5V 4 Co VO = VCC or GND 5V 10 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pF pF 3 74AC11244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y MIN TA = 25°C TYP MAX MIN MAX 1.5 7.1 9.3 1.5 10.2 1.5 6.3 8.6 1.5 9.5 1.5 8 10.7 1.5 11.8 1.5 7.9 10.6 1.5 11.9 1.5 5.9 7.9 1.5 8.3 1.5 7.2 9.4 1.5 9.9 UNIT ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y MIN TA = 25°C TYP MAX MIN MAX 1.5 4.9 6.7 1.5 7.3 1.5 4.5 6.4 1.5 6.9 1.5 5.4 7.7 1.5 8.5 1.5 5.4 7.6 1.5 8.5 1.5 5.2 7 1.5 7.3 1.5 5.8 7.8 1.5 8.2 UNIT ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d 4 Power dissipation capacitance per buffer/driver POST OFFICE BOX 655303 TEST CONDITIONS Outputs enabled Outputs disabled • DALLAS, TEXAS 75265 CL = 50 pF, pF f = 1 MHz TYP 27 9 UNIT pF 74AC11244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND LOAD CIRCUIT Output Control (low-level enabling) VCC 50% 50% 0V tPLH tPHL VOH Output S1 Open 2 × VCC GND 50% 50% 500 Ω CL = 50 pF (see Note A) Input TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 50% VCC 50% VCC VOL VCC 0V tPZL Output Waveform 2 S1 at GND (see Note B) [ VCC tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) 50% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS 20% VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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