SN54ACT16244, 74ACT16244
16-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS116B – MARCH 1990 – REVISED APRIL 1996
D
D
D
D
D
D
D
D
SN54ACT16244 . . . WD PACKAGE
74ACT16244 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
Flow-Through Architecture Optimizes
PCB Layout
Distributed VCC and GND Pin
Configurations Minimize High-Speed
Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Packages
Using 25-mil Center-to-Center Pin Spacings
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
description
The SN54ACT16244 and 74ACT16244 are 16-bit
buffers/line drivers designed specifically to
improve both the performance and density of
3-state memory address drivers, clock drivers,
and bus-oriented receivers and transmitters.
They can be used as four 4-bit buffers, two 8-bit
buffers, or one 16-bit buffer. The devices provide
true outputs and symmetrical OE (active-low)
output-enable inputs.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
The 74ACT16244 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The SN54ACT16244 is characterized for operation over the full military temperature range of –55°C to 125°C.
The 74ACT16244 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each driver)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ACT16244, 74ACT16244
16-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS116B – MARCH 1990 – REVISED APRIL 1996
logic symbol†
1OE
2OE
3OE
4OE
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
1
EN1
48
25
24
EN2
EN3
EN4
47
1
1
46
3
44
5
43
6
41
8
1
2
40
9
38
11
37
12
36
1
3
13
35
14
33
16
32
17
30
19
1
4
29
20
27
22
26
23
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
SN54ACT16244, 74ACT16244
16-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS116B – MARCH 1990 – REVISED APRIL 1996
logic diagram (positive logic)
1OE
1A1
1A2
1
3OE
47
2
46
3
44
5
43
6
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DGG package . . . . . . . . . . . . . . . . 0.85 W
DL package . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ACT16244, 74ACT16244
16-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS116B – MARCH 1990 – REVISED APRIL 1996
recommended operating conditions (see Note 3)
SN54ACT16244
MAX
MIN
MAX
4.5
5.5
4.5
5.5
VCC
VIH
Supply voltage (see Note 4)
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
∆t/∆v
Low-level output current
High-level input voltage
74ACT16244
MIN
2
2
0.8
Input transition rise or fall rate
0
UNIT
V
V
0.8
V
VCC
VCC
V
–24
–24
mA
24
24
mA
10
ns/V
VCC
VCC
10
0
0
0
V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTES: 3. Unused inputs should be tied to VCC through a pullup resistor of approximately 5 kW or greater to prevent them from floating.
4. All VCC and GND pins must be connected to the proper voltage supply.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
4.5 V
IOH = –50
50 mA
VOH
IOH = –24
24 mA
IOH = –50 mA{
IOH = –75 mA{
MIN
TA = 25°C
TYP
MAX
SN54ACT16244
MIN
MAX
IOL = 50 mA{
IOL = 75 mA{
MIN
4.4
4.4
5.5 V
5.4
5.4
5.4
4.5 V
3.94
3.7
3.8
5.5 V
4.94
4.7
4.8
UNIT
V
3.85
4.5 V
0.1
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
5.5 V
0.1
V
1.65
5.5 V
1.65
II
IOZ
VI = VCC or GND
VO = VCC or GND
5.5 V
±0.1
±1
±1
5.5 V
±0.5
±10
±5
ICC
VI = VCC or GND, IO = 0
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
8
160
80
mA
mA
mA
5.5 V
0.9
1
1
mA
∆ICC}
Ci
Co
VI = VCC or GND
VO = VCC or GND
5V
4.5
pF
5V
13.5
pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
4
MAX
3.85
5.5 V
IOL = 24 mA
74ACT16244
4.4
5.5 V
IOL = 50 mA
VOL
VCC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ACT16244, 74ACT16244
16-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS116B – MARCH 1990 – REVISED APRIL 1996
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ACT16244
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
OE
Y
tPHZ
tPLZ
OE
Y
TA = 25°C
MIN
TYP
MAX
MIN
MAX
4
6.5
8.5
3
10.3
3.4
6.3
8.7
3.4
10.1
3
5.8
8.1
3
10.5
3.7
6.7
9.3
3.7
11
5.4
8.1
11.5
5.4
13
5
7.5
9.5
5
10.9
UNIT
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
74ACT16244
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
OE
Y
tPHZ
tPLZ
OE
Y
TA = 25°C
MIN
TYP
MAX
MIN
MAX
4
6.5
8.5
4
9.4
3.4
6.3
8.7
3.4
9.5
3
5.8
8.1
3
8.9
3.7
6.7
9.3
3.7
10.3
5.4
8.1
10.3
5.4
11.3
5
7.5
9.5
5
10.3
UNIT
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CL = 50 pF,
pF
f = 1 MHz
TYP
39
11
UNIT
pF
5
SN54ACT16244, 74ACT16244
16-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS116B – MARCH 1990 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC
500 Ω
From Output
Under Test
S1
Open
GND
Output
Control
(low-level
enabling)
LOAD CIRCUIT
3V
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
Output
S1
Open
2 × VCC
GND
1.5 V
1.5 V
500 Ω
CL = 50 pF
(see Note A)
Input
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
50% VCC
50% VCC
VOL
3V
0V
tPZL
Output
Waveform 2
S1 at GND
(see Note B)
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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Copyright 1998, Texas Instruments Incorporated