LP61L256B Series 32K X 8 Bit High SPEED LOW VCC CMOS SRAM Features n Single +3.3 volt power supply n Access times: 12 ns (max.) n Current: Operating: 100mA (max.) Standby: 10mA (max.) n Full static operation, no clock or refreshing required n n n n All inputs and outputs directly TTL compatible Common I/O using three-state output Data retention voltage: 2V (min.) Available in 28-pin SOJ and TSOP packages General Description The LP61L256B is a high-speed, low-power 262,144-bit static random access memory organized as 32,768 words by 8 bits that operates on a single 3.3V power supply. Input and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Minimum standby power is drawn by this device when CE is at a high level, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 2V. Pin Configurations n SOJ n TSOP 28 VCC 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 A3 7 A2 8 A1 9 23 A11 22 OE 21 A10 20 CE A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 GND 14 15 I/O4 (August, 2001, Version 1.0) 14 1 LP61L256BV 1 A12 LP61L256B A14 28 15 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin Name OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 Pin No. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name A2 A1 A0 I/O 1 I/O 2 I/O 3 GND I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 CE A10 1 AMIC Technology, Inc. LP61L256B Series Block Diagram A0 VCC A5 GND ROW 256 X 1024 DECODER MEMORY ARRAY A7 A9 A12 I/O1 COLUMN I/O INPUT DATA CIRCUIT COLUMN DECODER I/O8 A1 A4 A8 A13 A14 CE OE WE CONTROL CIRCUIT Pin Descriptions -SOJ Pin Description - TSOP Pin No. Symbol 1 - 10, 21, 23 - 26 A0 - A14 Address Inputs 11 - 13, 15 - 19 I/O1 - I/O8 Data Inputs/Outputs 14 GND 20 CE Chip Enable 22 OE Output Enable 27 WE Write Enable VCC Power Supply (+3.3V) 28 (August, 2001, Version 1.0) Description Ground 2 Pin No. Symbol Description 1 OE Output Enable 2 - 5, 8 - 17, 28 A0 - A14 Address Inputs 6 WE Write Enable 7 VCC Power Supply 18 - 20, 22 - 26 I/O1 - I/O8 21 GND 27 CE Data Inputs/Outputs Ground Chip Enable AMIC Technology, Inc. LP61L256B Series Recommended DC Operating Conditions (TA = 0°C to + 70°C) Symbol Parameter VCC Supply Voltage GND Ground Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 0 0 V VIH Input High Voltage 2.2 - VCC + 0.3 V VIL Input Low Voltage -0.3 0 0.8 V CL Output Load - - 30 pF TTL Output Load - - 1 - Absolute Maximum Ratings* *Comments VCC to GND . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V IN, IN/OUT Volt to GND . . . . . . . . . . -0.3V to VCC +0.3V Operating Temperature, Topr . . . . . . . . . . . 0°C to +70°C Storage Temperature, Tstg . . . . . . . . . . -55°C to +125°C Power Dissipation, Pt . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (TA = 0°C to 70°C, VCC = 3.3V ± 10%, GND = 0V) LP61L256B-12 Symbol Parameter Unit Min. Max. Conditions ILI Input Leakage Current - 2 µA VIN = GND to VCC ILO Output Leakage Current - 2 µA CE = VIH or OE = VIH VI/O = GND to VCC Dynamic Operating Current - 100 mA CE = VIL, II/O = 0 mA - 20 mA CE = VIH - 10 mA CE ≥ VCC - 0.2V VIN ≥ VCC - 0.2V or VIN ≤ 0.2V ICC1 (1) ISB ISB1 Standby Power Supply Current VOL Output Low Voltage - 0.4 V IOL = 8 mA VOH Output High Voltage 2.4 - V IOH = -4 mA Notes: 1. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns. (August, 2001, Version 1.0) 3 AMIC Technology, Inc. LP61L256B Series Truth Table Mode I/O Operation Supply Current CE OE WE Standby H X X High Z ISB, ISB1 Output Disable L H H High Z ICC1 Read L L H DOUT ICC1 Write L X L DIN ICC1 Capacitance (TA = 25°C, f = 1.0 MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance - 10 pF VIN = 0 V CI/O* Input/Output Capacitance - 10 pF VI/O = 0 V * These parameters are sampled and not 100% tested. AC Characteristics (TA = 0°C to + 70°C, VCC = 3.3V ± 10%) LP61L256B-12 Symbol Parameter Unit Min. Max. 12 - ns Read Cycle tRC Read Cycle Time tAA Address Access Time - 12 ns tACE Chip Enable Access Time - 12 ns tOE Output Enable to Output Valid - 7 ns tCLZ Chip Enable to Output in Low Z 2 - ns tOLZ Output Enable to Output in Low Z 2 - ns tCHZ Chip Disable to Output in High Z 0 7 ns tOHZ Output Disable to Output in High Z 2 6 ns tOH Output Hold from Address Change 2 - ns (August, 2001, Version 1.0) 4 AMIC Technology, Inc. LP61L256B Series AC Characteristics (continued) LP61L256B-12 Symbol Parameter Unit Min. Max. Write Cycle tWC Write Cycle Time 12 - ns tCW Chip Enable to End of Write 10 - ns tAS Address Setup Time of Write 0 - ns tAW Address Valid to End of Write 10 - ns tWP Write Pulse Width 8 - ns tWR Write Recovery Time 0 - ns tWHZ Write to Output in High Z 0 7 ns tDW Data to Write Time Overlap 8 - ns tDH Data Hold from Write Time 0 - ns tOW Output Active from End of Write 5 - ns Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. Timing Waveforms (1, 2, 4) Read Cycle 1 tRC Address tAA tOH tOH DOUT (August, 2001, Version 1.0) 5 AMIC Technology, Inc. LP61L256B Series Timing Waveforms (continued) (1, 3, 4) Read Cycle 2 CE tACE tCLZ 5 tCHZ 5 DOUT (1) Read Cycle 3 tRC Address tAA OE tOH tOE tOLZ 5 CE tOHZ 5 tCHZ 5 tACE tCLZ 5 DOUT Note: 1. 2. 3. 4. 5. WE is high for Read cycle. Device is continuously enabled, CE = VIL. Address valid prior to or coincident with CE transition low. OE = VIL. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested. (August, 2001, Version 1.0) 6 AMIC Technology, Inc. LP61L256B Series Timing Waveforms (continued) (6) Write Cycle (Write Enable Controlled) tWC Address tAW tWR3 tCW5 CE (4) tAS1 tWP2 WE tDW tDH DIN tWHZ 7 tOW7 DOUT Write Cycle 2 (Chip Enable Controlled) tWC Address tAW tAS1 CE tWR3 tCW5 (4) tWP2 WE tDW tDH DIN tWHZ 7 DOUT Notes: 1. 2. 3. 4. tAS is measured from address valid to the beginning of Write. A Write occurs during the overlap (tWP) of a low CE and a low WE . tWR is measured from CE or WE going high to the end of the Write cycle. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from CE going low to the end of Write. 6. OE is continuously low ( OE = VIL). 7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested. (August, 2001, Version 1.0) 7 AMIC Technology, Inc. LP61L256B Series AC Test Conditions Input Pulse Levels 0V - 3V Input Rise and Fall Times 3 ns Input and Current Timing Reference Levels 1.5V Output Load See Figures 1, 2 and 3 +3.3V +3.3V 320Ω 320Ω I/O OUTPUT I/O 5pF* 350Ω VT=1.5V * Including scope and jig. * Including scope and jig. Figure 1. Output Load RL=50Ω ZO=50Ω 30pF* 350Ω Figure 2. Output Load for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW Figure 3. Output Load Data Retention Characteristics (TA = 0°C to 70°C) Symbol Parameter Min. Max. Unit VDR VCC for Data Retention 2.0 3.6 V ICCDR Data Retention Current - 0.5 mA tCDR Chip Disable to Data Retention Time 0 - ns Operation Recovery Time 5 - ms tR (August, 2001, Version 1.0) 8 Conditions CE ≥ VCC - 0.2V VCC = 2V, CE ≥ VCC - 0.2V VIN ≥ VCC - 0.2V or VIN ≤ 0.2V See Retention Waveform AMIC Technology, Inc. LP61L256B Series Low VCC Data Retention Waveform DATA RETENTION MODE VCC 3.3V 3.3V tCDR tR VDR ≥ 2V VIH CE VIH CE ≥ VDR - 0.2V Ordering Information Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mA) LP61L256BS-12 12 100 10 28L SOJ LP61L256BV-12 12 100 10 28L TSOP Part No. (August, 2001, Version 1.0) 9 Package AMIC Technology, Inc. LP61L256B Series Package Information SOJ 28L Outline Dimensions 15 1 14 E 28 HE unit: inches/mm L A A2 C D e A1 b b1 D S Seating Plane e1 y Symbol Dimensions in inches Dimensions in mm A 0.140 Max. 3.56 Max. A1 0.027 Min. 0.69 Min. A2 0.100±0.005 2.54±0.13 b1 0.028 Typ. 0.71 Typ. b 0.018 Typ. 0.46 Typ. C 0.010 Typ. 0.25 Typ. D 0.710 Typ. (0.730 Max.) 18.03 Typ. (18.54 Max.) E 0.300±0.005 7.62±0.13 e 0.050 Typ. 1.27 Typ. e1 0.265±0.010 6.73±0.25 HE 0.337±0.008 8.56±0.20 L 0.087±0.10 2.21±0.25 S 0.045 Max. 1.14 Max. y 0.004 Max. 0.10 Max. Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (August, 2001, Version 1.0) 10 AMIC Technology, Inc. LP61L256B Series Package Information TSOP 28L TYPE I (8 X 13.4mm) Outline Dimensions D unit: inches/mm RD c A A2 12.0° A1 E GAUGE PLANE e 0.25 BSC θ L LE HD Detail "A" D Detail "A" y S b Symbol Dimensions in inches Dimensions in mm A 0.049 Max. 1.25 Max. A1 0.002 Min. 0.05 Min. A2 0.039±0.002 1.00±0.05 b 0.0079±0.0012 0.20±0.03 c 0.006±0.0003 0.15±0.008 D 0.465±0.004 11.80±0.10 E 0.315±0.004 8.00±0.10 e 0.0217 TYP. 0.55 TYP. HD 0.528±0.008 13.40±0.20 L 0.02±0.008 0.50±0.20 LE 0.0266 TYP. 0.675 TYP. S 0.0167 TYP. 0.425 TYP. y 0.004 Max. 0.10 Max. θ 0° ~ 6° 0° ~ 6° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (August, 2001, Version 1.0) 11 AMIC Technology, Inc.