LP62S2048-T Series 256K X 8 BIT LOW VOLTAGE CMOS SRAM Features n Power supply range: 2.7V to 3.3V n Access times: 70/100 ns (max.) n Current: Low power version: Operating: 30mA (max.) Standby: 50µA (max.) Very low power version: Operating: 30mA (max.) Standby: 10µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2V (min.) n Available in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm) and 36-pin CSP packages General Description Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. The LP62S2048-T is a low operating current 2,097,152bit static random access memory organized as 262,144 words by 8 bits and operates on a low power supply range: 2.7V to 3.3V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Pin Configurations n SOP n TSOP/(TSSOP) n CSP (Chip Size Package) 36-pin Top View 1 32 VCC A16 2 31 A15 A14 3 30 CE2 A12 4 29 WE A7 5 28 A13 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O1 LP62S2048M-T A6 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE1 21 I/O8 13 20 I/O7 I/O2 14 19 I/O6 I/O3 15 18 I/O5 GND 16 17 I/O4 (August, 2001, Version 1.0) 16 1 LP62S2048V-T (LP62S2048X-T) A17 32 17 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name A3 A2 A1 A0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 I/O8 CE1 A10 OE 1 1 2 3 4 5 6 A A0 A1 CE2 A3 A6 A8 A2 WE A4 A7 I/O1 NC A5 B I/O5 C I/O6 D GND E VCC F I/O7 G I/O8 H A9 I/O2 VCC GND NC A17 I/O3 OE CE1 A16 A15 I/O4 A10 A11 A12 A13 A14 AMIC Technology, Inc. LP62S2048-T Series Block Diagram A0 VCC GND A15 ROW 1024 X 2048 DECODER MEMORY ARRAY INPUT DATA CIRCUIT COLUMN I/O A16 A17 I/O1 I/O8 CE2 CE1 CONTROL CIRCUIT OE WE Pin Description - SOP Pin Descriptions - TSOP/TSSOP Pin No. Symbol Description 1 - 12, 23, 25 - 28, 31 A0 - A17 Address Inputs 13 - 15, 17 - 21 I/O1 - I/O8 Data Input/Outputs 16 GND Pin No. Symbol Description 1 - 4, 7, 9 - 20, 31 A0 - A17 5 WE Write Enable 6 CE2 Chip Enable 8 VCC Power Supply 9 NC No Connection 21 - 23, 25 - 29 I/O1 - I/O8 24 GND Ground Address Inputs Ground 22 CE1 Chip Enable 24 OE Output Enable 29 WE Write Enable 30 CE2 Chip Enable 30 CE1 Chip Enable 32 VCC Power Supply 32 OE Output Enable (August, 2001, Version 1.0) 2 Data Input/Outputs AMIC Technology, Inc. LP62S2048-T Series Pin Description - CSP Symbol A0 - A17 Description Address Inputs Symbol Description NC No Connection WE Write Enable I/O1 - I/O8 Data Input/Output OE Output Enable VCC Power Supply CE1 Chip Enable GND Ground CE2 Chip Enable -- -- Recommended DC Operating Conditions (TA = -25°C to + 85°C) Symbol Parameter VCC Supply Voltage GND Ground Min. Typ. Max. Unit 2.7 3.0 3.3 V 0 0 0 V VIH Input High Voltage 2.0 - VCC + 0.3 V VIL Input Low Voltage -0.3 - +0.6 V CL Output Load - - 30 pF TTL Output Load - - 1 - (August, 2001, Version 1.0) 3 AMIC Technology, Inc. LP62S2048-T Series Absolute Maximum Ratings* *Comments VCC to GND . . . . . . . . . . . . . . . . . . . . -0.5V to + 4.6V IN, IN/OUT Volt to GND . . . . . . . . . -0.5V to VCC + 0.5V Operating Temperature, Topr . . . . . . . . -25°C to + 85°C Storage Temperature, Tstg . . . . .. . . . . -55°C to + 125°C Temperature Under Bias, Tbias . . . . . . -10°C to + 85°C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . 0.7W Soldering Temp. & Time . . . . . . . . . . . . . 260°C, 10 sec Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Symbol Parameter (TA = -25°C to + 85°C, VCC = 2.7V to 3.3V, GND = 0V) LP62S2048-70LT/10LT LP62S2048-70LLT/10LLT Min. Max. Min. Max. Unit Conditions ILI Input Leakage Current - 1 - 1 µA VIN = GND to VCC ILO Output Leakage Current - 1 - 1 µA CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GND to VCC ICC Active Power Supply Current - 3 - 3 mA CE1 = VIL, CE2 = VIH II/O = 0mA ICC1 Dynamic Operating Current ICC2 (August, 2001, Version 1.0) - 30 - 30 mA Min. Cycle, Duty = 100% CE1 = VIL, CE2 = VIH II/O = 0mA - 5 - 5 mA CE1 = VIL, CE2 = VIH VIH = VCC, VIL = 0V f = 1 MHZ, II/O = 0mA 4 AMIC Technology, Inc. LP62S2048-T Series DC Electrical Characteristics (continued) Symbol LP62S2048-70LT/10LT Parameter ISB ISB1 Standby Power Supply Current ISB2 LP62S2048-70LLT/10LLT Unit Conditions Min. Max. Min. Max. - 0.5 - 0.5 mA CE1 = VIH or CE2 =VIL - 50 - 10 µA CE1 ≥ VCC - 0.2V VIN ≥ 0V - 50 - 10 µA CE2 ≤ 0.2V VIN ≥ 0V VOL Output Low Voltage - 0.4 - 0.4 V IOL = 2.1mA VOH Output High Voltage 2.2 - 2.2 - V IOH = -1.0mA Truth Table Mode CE1 CE2 OE WE I/O Operation H X X X High Z ISB, ISB1 X L X X High Z ISB, ISB2 Output Disable L H H H High Z ICC, ICC1, ICC2 Read L H L H DOUT ICC, ICC1, ICC2 Write L H X L DIN ICC, ICC1, ICC2 Min. Max. Unit Standby Supply Current Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Conditions CIN* Input Capacitance 6 pF VIN = 0V CI/O* Input/Output Capacitance 8 pF VI/O = 0V * These parameters are sampled and not 100% tested. (August, 2001, Version 1.0) 5 AMIC Technology, Inc. LP62S2048-T Series AC Characteristics (TA = -25°C to + 85°C, VCC = 2.7V to 3.3V) Symbol LP62S2048-70LT/LLT Parameter LP62S2048-10LT/LLT Unit Min. Max. Min. Max. 70 - 100 - ns - 70 - 100 ns CE1 - 70 - 100 ns CE2 - 70 - 100 ns - 35 - 50 ns CE1 10 - 10 - ns CE2 10 - 10 - ns 5 - 5 - ns CE1 0 25 0 35 ns CE2 0 25 0 35 ns Read Cycle tRC Read Cycle Time tAA Address Access Time tACE1 Chip Enable Access Time tACE2 tOE tCLZ1 Output Enable to Output Valid Chip Enable to Output in Low Z tCLZ2 tOLZ Output Enable to Output in Low Z tCHZ1 Chip Disable to Output in High Z tCHZ2 tOHZ Output Disable to Output in High Z 0 25 0 35 ns tOH Output Hold from Address Change 10 - 10 - ns tWC Write Cycle Time 70 - 100 - ns tCW Chip Enable to End of Write 60 - 80 - ns tAS Address Setup Time 0 - 0 - ns tAW Address Valid to End of Write 60 - 80 - ns tWP Write Pulse Width 50 - 60 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z 0 25 0 35 ns tDW Data to Write Time Overlap 30 - 40 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 5 - 5 - ns Write Cycle Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. (August, 2001, Version 1.0) 6 AMIC Technology, Inc. LP62S2048-T Series Timing Waveforms Read Cycle 1 (1, 2, 4) tRC Address tAA tOH tOH DOUT Read Cycle 2 (1, 3, 4, 6) CE1 tACE1 tCLZ15 tCHZ15 DOUT Read Cycle 3 (1, 4, 7, 8) CE2 tACE2 tCHZ25 tCLZ25 DOUT (August, 2001, Version 1.0) 7 AMIC Technology, Inc. LP62S2048-T Series Timing Waveforms (continued) Read Cycle 4 (1) tRC Address tAA OE tOE tOH tOLZ5 CE1 tACE1 tCHZ15 tCLZ15 CE2 tACE2 tOHZ 5 tCHZ25 tCLZ25 DOUT Notes: 1. 2. 3. 4. 5. 6. 7. 8. WE is high for Read Cycle. Device is continuously enabled CE1 = VIL and CE2 = VIH. Address valid prior to or coincident with CE1 transition low. OE = VIL. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. CE2 is high. CE1 is low. Address valid prior to or coincident with CE2 transition high. (August, 2001, Version 1.0) 8 AMIC Technology, Inc. LP62S2048-T Series Timing Waveforms (continued) (6) Write Cycle 1 (Write Enable Controlled) tWC Address tAW tWR3 tCW CE1 (4) CE2 (4) 5 tAS1 tWP2 WE tDW tDH DIN tWHZ tOW DOUT (August, 2001, Version 1.0) 9 AMIC Technology, Inc. LP62S2048-T Series Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address tWR3 tAW tCW5 CE1 CE2 tAS1 (4) (4) tCW5 tWP2 WE tDW tDH DIN tWHZ7 DOUT Notes: 1. 2. 3. 4. tAS is measured from the address valid to the beginning of Write. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE . tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. (August, 2001, Version 1.0) 10 AMIC Technology, Inc. LP62S2048-T Series AC Test Conditions Input Pulse Levels 0.4V to 2.4V Input Rise and Fall Time 5 ns Input and Output Timing Reference Levels 1.5V Output Load See Figures 1 and 2 TTL TTL CL CL 30pF 5pF * Including scope and jig. * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tCLZ1, tCLZ2, tOHZ, tOLZ, tCHZ1, tCHZ2, tWHZ, and tOW Data Retention Characteristics (TA = -25°C to 85°C) Symbol Parameter Min. Max. Unit 2.0 3.3 V CE1 ≥ VCC - 0.2V 2.0 3.3 V CE2 ≤ 0.2V, L-Version - 20* µA LL-Version - 5** VCC = 2.0V, CE1 ≥ VCC - 0.2V, VIN ≥ 0V L-Version - 20* LL-Version - 5** 0 - ns tRC - ns 5 - ms VDR1 VDR2 VCC for Data Retention ICCDR1 Data Retention Current ICCDR2 tCDR Chip Disable to Data Retention Time tR Operation Recovery Time tVR VCC Rising Time from Data Retention Voltage to Operating Voltage ** LP62S2048-70LLT/10LLT * LP62S2048-70LT/10LT (August, 2001, Version 1.0) ICCDR: max. ICCDR: max. µA Conditions VCC = 2.0V, CE2 ≤ 0.2V, VIN ≥ 0V See Retention Waveform 1µA at TA = 0°C to + 40°C 5µA at TA = 0°C to + 40°C 11 AMIC Technology, Inc. LP62S2048-T Series Low VCC Data Retention Waveform (1) ( CE1 Controlled) DATA RETENTION MODE VCC 2.7V tCDR 2.7V tR VDR ≥ 2V tVR CE1 VIH VIH CE1 ≥ VDR - 0.2V Low VCC Data Retention Waveform (2) (CE2 Controlled) DATA RETENTION MODE VCC 2.7V tCDR 2.7V tR VDR ≥ 2V tVR CE2 VIL VIL CE2 ≤ 0.2V (August, 2001, Version 1.0) 12 AMIC Technology, Inc. LP62S2048-T Series Ordering Information Part No. Operating Current Max. (mA) Standby Current Max. (µ µA) LP62S2048M-70LT 30 50 32L SOP LP62S2048M-70LLT 30 10 32L SOP LP62S2048V-70LT 30 50 32L TSOP 30 10 32L TSOP LP62S2048X-70LT 30 50 32L TSSOP LP62S2048X-70LLT 30 10 32L TSSOP LP62S2048U-70LT 30 50 36L CSP LP62S2048U-70LLT 30 10 36L CSP LP62S2048M-10LT 30 50 32L SOP LP62S2048M-10LLT 30 10 32L SOP LP62S2048V-10LT 30 50 32L TSOP 30 10 32L TSOP LP62S2048X-10LT 30 50 32L TSSOP LP62S2048X-10LLT 30 10 32L TSSOP LP62S2048U-10LT 30 50 36L CSP LP62S2048U-10LLT 30 10 36L CSP (August, 2001, Version 1.0) 13 LP62S2048V-70LLT LP62S2048V-10LLT Access Time (ns) 70 100 Package AMIC Technology, Inc. LP62S2048-T Series Package Information SOP (W.B.) 32L Outline Dimensions 32 unit: inches/mm 17 e1 E HE ~ L 1 b 16 Detail F e1 e Seating Plane D s A LE A1 A2 c D y See Detail F Symbol Dimensions in inches Dimensions in mm 3.00 Max. A 0.118 Max. A1 0.004 Min. 0.10 Min. A2 0.106±0.005 2.69±0.13 b 0.016 +0.004 0.41 +0.10 -0.002 -0.05 0.008 +0.004 0.20 +0.10 c -0.002 -0.05 D 0.805 Typ. (0.820 Max.) 20.45 Typ. (20.83 Max.) E 0.445±0.010 11.30±0.25 e 0.050 ±0.006 1.27±0.15 e1 0.525 NOM. 13.34 NOM. HE 0.556±0.010 14.12±0.25 L 0.031±0.008 0.79±0.20 LE 0.055±0.008 1.40±0.20 S 0.044 Max. 1.12 Max. y 0.004 Max. 0.10 Max. θ 0° ~ 10° 0° ~ 10° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (August, 2001, Version 1.0) 14 AMIC Technology, Inc. LP62S2048-T Series Package Information TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm e D A c E A2 12.0° A1 GAUGE PLANE 0.25 BSC θ L LE HD Detail "A" D Detail "A" y S Symbol Dimensions in inches Dimensions in mm A 0.047 Max. 1.20 Max. A1 0.004±0.002 0.10±0.05 A2 0.039±0.002 1.00±0.05 b 0.008±0.001 0.20±0.03 c 0.006±0.001 0.15±0.02 D 0.724±0.004 18.40±0.10 E 0.315±0.004 8.00±0.10 e 0.020 TYP. 0.50 TYP. HD 0.787±0.007 20.00±0.20 L 0.020±0.004 0.50±0.10 LE 0.031 TYP. 0.80 TYP. S 0.0167 TYP. 0.425 TYP. Y 0.004 Max. 0.10 Max. θ 0° ~ 6° 0° ~ 6° b 0.10(0.004) M Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (August, 2001, Version 1.0) 15 AMIC Technology, Inc. LP62S2048-T Series Package Information TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions e unit: inches/mm A c E A2 12.0° A1 GAUGE PLANE 0.25 BSC θ L LE D1 D Detail "A" D Detail "A" 0.10MM S b SEATING PLANE Symbol Dimensions in inches Dimensions in mm A 0.049 Max. 1.25 Max. A1 0.002 Min. 0.05 Min. A2 0.039±0.002 1.00±0.05 b 0.008±0.001 0.20±0.03 c 0.006±0.0003 0.15±0.008 E 0.315±0.004 8.00±0.10 e 0.020 TYP. 0.50 TYP. D 0.528±0.008 13.40±0.20 D1 0.465±0.004 11.80±0.10 L 0.02±0.008 0.50±0.20 LE 0.0266 Min. 0.675 Min. S 0.0109 TYP. 0.278 TYP. y 0.004 Max. 0.10 Max. θ 0° ~ 6° 0° ~ 6° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (August, 2001, Version 1.0) 16 AMIC Technology, Inc. LP62S2048-T Series Package Information 36LD CSP (6 x 8 mm) Outline Dimensions unit: mm BOTTOM VIEW TOP VIEW Ball#A1 CORNER 0.10 S C 0.25 S C A B Ball*A1 CORNER b (36X) 6 5 4 3 2 1 1 2 3 4 5 6 A B C D E F G H C D E F G H E1 E e A B B A 0.10 C SIDE VIEW D 0.20(4X) A2 SEATING PLANE A1 (0.36) C Symbol A A1 A2 D E D1 E1 e b A // 0.25 C e D1 Dimensions in mm MIN. NOM. MAX. 1.00 0.16 0.48 5.80 7.80 ------0.25 1.10 0.21 0.53 6.00 8.00 3.75 5.25 0.75 0.30 1.20 0.26 0.58 6.20 8.20 ------0.35 Note: 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 4. BALL PAD OPENING OF SUBSTRATE IS Φ 0.25mm (SMD) SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.25mm (NSMD) (August, 2001, Version 1.0) 17 AMIC Technology, Inc.