® DAC4815 Quad 12-Bit Digital-to-Analog Converter (8-Bit Port Interface) FEATURES ● COMPLETE QUAD DAC — INCLUDES INTERNAL REFERENCES AND OUTPUT AMPLIFIERS ● GUARANTEED SPECIFICATIONS OVER TEMPERATURE ● GUARANTEED MONOTONIC OVER TEMPERATURE ● HIGH-SPEED 8 + 4-BIT PARALLEL INTERFACE DAC4815 +VL 11 +VS 8 –VS 7 AGND 9 10kΩ 5 +VREF Out 3 –VREF Out 4 VREF In 6 BPO 2 VOUT A 1 VOUT B 10kΩ 10V Ref A5 DGND 10 ● LOW POWER, 600mW (150mW/DAC) 20kΩ ● LOW GAIN DRIFT, 5ppm/°C ● LOW NONLINEARITY: ±1/2 LSB max 20kΩ ● BIPOLAR OUTPUT ● CLEAR/RESET TO BIPOLAR ZERO DAC A A1 DESCRIPTION 20kΩ The DAC4815 is one in a family of dual and quad 12-bit digital-to-analog converters (DACs). Serial, 8-bit, 12-bit interfaces are available. The DAC4815 is complete. It contains CMOS logic, switches, a high-performance buried-zener reference, and low-noise bipolar output amplifiers. No external components are required for bipolar ±10V output range. 20kΩ DAC B A2 8-Bit Port and Control In The DAC4815 has a 2-byte (8 + 4) double-buffered interface. Data is first loaded (level transferred) into the input registers in two steps for each DAC. Then both DACs are updated simultaneously. The DAC has an asynchronous clear control for reset to bipolar zero. This feature is useful for power-on reset or system calibration. The DAC4815 is packaged in a 28-pin plastic DIP rated for the –40°C to +85°C extended industrial temperature range. High-stability laser-trimmed thin film resistors assure high reliability and true 12-bit integral and differential linearity over the full specified temperature range. 20kΩ Logic 20kΩ DAC C A3 13 VOUT C 20kΩ 20kΩ DAC D A4 12 VOUT D International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1991 Burr-Brown Corporation PDS-1112B Printed in U.S.A. October, 1993 SPECIFICATIONS, Guaranteed over TA = –40°C to +85°C unless otherwise specified. ELECTRICAL Specifications as shown for VS = ±12V or ±15V, VL = +5V, and RL = 2kΩ unless otherwise noted. DAC4815AP PARAMETER CONDITIONS DIGITAL INPUTS Resolution VIH (Input High Voltage) VIL (Input Low Voltage) IIN ( Input Current) MIN 12 2 0 Bipolar Zero Error Gain Error Power Supply Sensitivity (3) TA = 25°C TA = –40°C to +85°C ±1.5/–1 ±20 With Internal or External 10.0V Ref VS = ±11.4V to ±18V VL = +4.5V to +5.5V +9.980 TA = 25°C TA = –40°C to +85°C Max Load Capacitance (For Stability) Short Circuit Current Load Regulation (∆ VOUT vs ∆ ILOAD) Supply Regulation (∆ VOUT vs ∆ VS) –REFERENCE OUTPUT, Inverter –10V Reference –10V Reference Drift DC Output Impedance Output Current Max Load Capacitance (For Stability) Short Circuit Current DYNAMIC PERFORMANCE(4) Settling Time Slew Rate Small-Signal Bandwidth ±30 ±15 +10 ±2 +10.020 ±30 +9.985 * * ±20 ±8 ppm/°C ppmFSR/°C * * +10.015 ±20 –10 * ±5 * ppm/V –9.985 ±20 V ppm/°C Ω mA pF mA –9.980 ±30 –10.015 * * * * * 2.5 10 5 * * * +VS – 1.4 * * * * * ±11.4 4.5 Digital Inputs = 0V or +VL Digital Inputs = VIL or VIH * µs V/µs MHz * * * * * ±4 * mA 3 * nV-s 30 * nV-s ±15 5 +20 –20 0.4 600 2 V Ω mA pF mA * 10 kΩ kΩ kΩ V * * 500 ±30 3.5 10 3 LSB LSB LSB 40 * * ±5 Full Scale Transition CL= 100pF Bits V V µA µA pF V ppm/°C mA mA pF mA ppm/mA 0.1 CL = 100pF To 1/2 LSB of Full Scale * * * * * * –VS + 1.4 VOUT UNITS % ppmFSR/V ±10 ® DAC4815 ±5 ±5 200 30 1.75 7 3.5 MAX ±1/2 * ±1 mV ±0.15 * ±10 ±0.2 30 0.1 DIGITAL-TO-ANALOG GLITCH IMPULSE POWER SUPPLY +VS and –VS +VL +IS –IS +IL +IL Total Power, All DACs ±1 ±1 ±7 ANALOG GROUND CURRENT (Code Dependent) DIGITAL CROSSTALK * * * 500 ±20 –10.020 TYP * +10/–5 +5/–5 REFERENCE INPUT Reference Input Resistance Inverter Input Resistance BPO Input Resistance Reference Input Range ANALOG SIGNAL OUTPUTS Voltage Range DC Output Impedance Output Current Max Load Capacitance (For Stability) Short Circuit Current MIN 0.8 TEMPERATURE DRIFT Gain Drift Bipolar Zero Drift REFERENCE OUTPUT Output Voltage Reference Drift Output Current DAC4815BP MAX 5 0.8 ±1 ±10 TA = 25°C TA = –40°C to +85°C CIN (Input Capacitance) ACCURACY Integral, Relative Linearity (1) Differential Nonlinearity (2) TYP ±18 5.5 +24 –25.5 2 10 753 * * * * * * * * * * * * * * * V V mA mA mA mA mW SPECIFICATIONS (CONT), Guaranteed over TA = –40°C to +85°C unless otherwise specified. ELECTRICAL Specifications as shown for VS = ±12V or ±15V, VL = +5V, and RL = 2kΩ unless otherwise noted. DAC4815AP PARAMETER CONDITIONS MIN TEMPERATURE RANGE Specified Operating Thermal Resistance, θJA TYP DAC4815BP MAX MIN +85 +85 * * –40 –40 TYP 75 MAX UNITS * * °C °C °C/W * NOTES: (1) End point linearity. (2) Guaranteed monotonic. (3) Change in bipolar full scale output. Includes effect of voltage output DAC, voltage references. (4) Guaranteed but not tested. PIN DESIGNATIONS PIN DESCRIPTOR FUNCTION PIN DESCRIPTOR FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VOUT B VOUT A –VREF Out VREF In +VREF Out BPO –VS +VS AGND DGND +VL VOUT D VOUT C CLR Analog output voltage, DAC B Analog output voltage, DAC A Negative reference voltage output (–10V output) ± Reference voltage input Positive reference voltage output (+10V output) Bipolar offset input, DAC A, B, C, and D Negative analog power supply, –15V input Positive analog power supply, +15V input Analog common Digital common Positive logic power supply, +5V input Analog output voltage, DAC D Analog output voltage, DAC C Asynchronous input reset to zero 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 LE CS WR Address line 2 input Address line 1 input Address line 0 input Data bit 7 input Data bit 6 input Data bit 5 input Data bit 4 input Data bit 3 input Data bit 2 input Data bit 1 input Data bit 0 input Latch data enable, DAC A, B, C, and D Chip select enable, DAC A, B, C, and D Write input, DAC A, B, C, and D PIN CONFIGURATIONS ABSOLUTE MAXIMUM RATINGS Top View VOUT B 1 28 A2 VOUT A 2 27 A1 –VREF Out 3 26 A0 VREF In 4 25 D7 +VREF Out 5 24 D6 BPO 6 +VL to AGND ................................................................................. 0V, +7V +VL to DGND ................................................................................ 0V, +7V +VS to AGND .............................................................................. 0V, +18V –VS to AGND ............................................................................... 0V,–18V AGND to DGND ................................................................................ ±0.3V Any digital input to GND ................................................. –0.3V, +VL +0.3V Ref In to AGND .................................................................................. ±25V Ref In to DGND .................................................................................. ±25V Storage Temperature Range .......................................... –55°C to +125°C Operating Temperature Range ......................................... –40°C to +85°C Lead Temperature (soldering, 10s) ................................................ +300°C Junction Temperature .................................................................... +155°C Output Short Circuit ................................... Continuous to common or ±VS Reference Short Circuit .............................. Continuous to common or +VS 23 D5 DAC4815 –VS 7 +VS 8 21 D3 AGND 9 20 D2 DGND 10 19 D1 22 D4 +VL 11 18 D0 VOUT D 12 17 LE VOUT C 13 16 CS CLR 14 15 WR ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ORDERING INFORMATION ORDERING INFORMATION MODEL MODEL DAC4815AP DAC4815AP DAC4815BP DAC4815BP 1–24 $35.85 43.05 USA OEM PRICES LINEARITY ERROR 25–99 (LSB) $28.45 ±1 34.15 ±1/2 PACKAGE INFORMATION MODEL 100+ $24.95 29.95 DAC4815AP DAC4815BP PACKAGE PACKAGE DRAWING NUMBER(1) 28-Pin Plastic DIP 28-PIn Plastic DIP 215 215 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ® 3 DAC4815 TYPICAL PERFORMANCE CURVES TA = +25°C, VS = ±12V or ±15V, VL = +5V unless otherwise noted. PSRR vs FREQUENCY (Bipolar Mode) NOISE vs BANDWIDTH (Bipolar Mode) 80 250 Voltage Noise (µVrms) 70 PSRR (dB) 60 50 40 VOUT = 0V 30 200 150 VOUT = +10V FFFHEX 100 20 50 VOUT = +10V 10 VOUT = 0V 800HEX 0 0 10k 100k 1M 100 1k Frequency (Hz) 1.0E–02 Gain Error 5.0E–03 0.0E+00 0.0E+00 Bipolar Offset –5.0E–01 ∆ Gain Error (%) 1.0E+00 21.8 –5.0E–03 –1.0E–02 –1.0E+00 –40 –20 0 20 40 1M 60 +80 7 +IL (All Logic Inputs = 2V) 21.5 6 21.2 5 20.9 4 IS 20.6 3 20.3 2 20 1 +IL (All Logic Inputs = 0V or VL) 0 19.4 –1.5E–02 –1.5E+00 ±IS (mA) Analog Supply 1.5E–02 Bipolar Zero 100k POWER SUPPLY CURRENT vs TEMPERATURE 1.5E+00 –40 100 –20 0 20 40 60 80 Temperature (°C) Temperature (°C) OUTPUT VOLTAGE SWING vs RESISTOR LOAD CROSSTALK (Bipolar Mode) 25 20 VS = ±15V 10V REF VL = 5V 0V VOUT B 15 VOUT VOUT (Vp-p) ∆ Bipolar Offset and Zero Error (mV) CHANGE OF GAIN, BIPOLAR OFFSET AND ZERO ERROR vs TEMPERATURE 5.0E+00 10k Frequency (Hz) VOUT A 10 LE +5V 5 0V 0 10 100 1k Time (500ns/div) 10k NOTE: Crosstalk is dominated by digital crosstalk/ feedthrough of LE signal. Load Resistance (Ω ) ® DAC4815 4 +IL (mA) Logic Supply 1k TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VS = ±12V or ±15V, VL = +5V unless otherwise noted. SETTLING TIME BIPOLAR (–10V to +10V) ∆V Around +10V (2mV/div) VOUT (5V/div) FULL-SCALE OUTPUT SWING BIPOLAR (20V Step) 0V VOUT LE +5V VOUT +5V LE 0V Time (2µs/div) Time (1µs/div) SETTLING TIME BIPOLAR (+10V to –10V Step) MAJOR CARRY GLITCH –10V VOUT (20mV/div) ∆V Around –10V (2mV/div) 0V +10V VOUT +5V LE 0V 0V 0V VOUT LE +5V 0V Time (2µs/div) Time (1µs/div) NOTE: Data transition 800HEX to 7FFHEX. VOUT (5mV/div) DIGITAL FEEDTHROUGH VOUT 0V Time (500ns/div) DAC output noise due to activity on digital inputs with latch disabled. ® 5 DAC4815 FUNCTIONAL BLOCK DIAGRAM, DAC4815 — Quad 12-bit DAC, 8-bit Port Data In VREF In 25 4 18 20kΩ 4-Bit Input Register 8-Bit Input Register CLR 14 6 BPO 2 VOUT A 1 VOUT B Bits 8 -11 12-Bit Latch Register 20kΩ Bits 0-11 DAC A A1 Bits 0 - 7 20kΩ 4-Bit Input Register WR 15 CS 16 8-Bit Input Register LE 17 Bits 8 -11 12-Bit Latch Register 20kΩ DAC B Bits 0-11 A2 Bits 0 - 7 Control Logic 20kΩ 4-Bit Input Register A0 26 8-Bit Input Register A1 27 Bits 8 -11 12-Bit Latch Register 20kΩ DAC C Bits 0-11 A3 13 VOUT C Bits 0 - 7 20kΩ A2 28 4-Bit Input Register 8-Bit Input Register Bits 8 -11 12-Bit Latch Register 20kΩ DAC D Bits 0-11 A4 12 VOUT D Bits 0 - 7 10kΩ 10kΩ +10V Voltage Reference A5 11 8 7 9 10 5 +VL +VS –VS AGND DGND +VREF Out ® DAC4815 6 3 –VREF Out TIMING CHARACTERISTICS +VL = +5V, TA = –40°C to +85°C. t1 PARAMETER MINIMUM A0-A2 20ns 10ns 30ns 10ns 0ns DATA t1—Address Valid to Write Setup Time t2—Address Valid to Write Hold Time t3—Data Setup Time t4—Data Hold Time t5—Chip Select to LE or Write Setup Time t6—Chip Select to LE or Write Hold Time t7—Write Pulse Width t8—Clear Pulse Width t2 t3 t5 CS 5V 0V t4 5V 0V t6 5V 0V t7 LE, WR t8 0ns CLR 40ns 40ns 5V 0V 5V 0V NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t R = t F = 5ns. (2) Timing measurement reference level is VIH + VIL . 2 INTERFACE LOGIC TRUTH TABLE CLR LE CS WR A2 A1 A0 FUNCTION 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 X 1 X 0 0 0 0 0 0 0 0 0 0 1 X X 0 0 0 0 0 0 0 0 1 0 X 1 X 0 0 0 0 1 1 1 1 X X X X X 0 0 1 1 0 0 1 1 X X X X X 0 1 0 1 0 1 0 1 X X X X X DAC A LS input register loaded with D7-D0(LSB) DAC A MS input register loaded with D3(MSB)-D0 DAC B LS input register loaded with D7-D0(LSB) DAC B MS input register loaded with D3(MSB)-D0 DAC C LS input register loaded with D7-D0(LSB) DAC C MS input register loaded with D3(MSB)-D0 DAC D LS input register loaded with D7-D0(LSB) DAC D MS input register loaded with D3(MSB)-D0 All DAC registers updated simultaneously from input registers All DAC registers are transparent No data transfer No data transfer Input registers cleared = 000HEX, DAC registers = 800HEX NOTE: X = Don’t care. DISCUSSION OF SPECIFICATIONS DIFFERENTIAL NONLINEARITY Differential nonlinearity is the deviation from an ideal 1 LSB change in the output voltage when the input code changes by 1 LSB. A differential nonlinearity specification of ±1 LSB maximum guarantees monotonicity. INPUT CODES All digital inputs of the DAC4815 are TTL and 5V CMOS compatible. Input codes for the DAC4815 are BOB (Bipolar Offset Binary). See Figure 3 for ±10V bipolar connection. BIPOLAR ZERO ERROR The output voltage for code 800HEX. BIPOLAR OUTPUTS FOR SELECTED INPUT DIGITAL INPUT FFFHEX 800HEX 7FFHEX 000HEX BIPOLAR (BOB) GAIN ERROR The deviation of the output voltage span (VMAX – VMIN) from the ideal span of 20V – 1 LSB (bipolar mode). The gain error is specified with and without the internal +10V reference error included. +Full Scale Zero Zero – 1 LSB –Full Scale INTEGRAL OR RELATIVE LINEARITY This term, also know as end point linearity, describes the transfer function of analog output to digital input code. Integral linearity error is the deviation of the analog output versus code transfer function from a straight line drawn through the end points. OUTPUT SETTLING TIME The time required for the output voltage to settle within a percentage-of-full-scale error band for a full scale transition. Settling to ±0.012% (1/2 LSB) is specified for the DAC4815. ® 7 DAC4815 DIGITAL-TO-ANALOG GLITCH Ideally, the DAC output would make a clean step change in response to an input code change. In reality, glitches occur during the transition. See Typical Performance Curves. R R R VREF 2R 2R 2R 2R 2R R R FB IOUT DIGITAL CROSSTALK Digital crosstalk is the glitch impulse measured at the output of one DAC due to a full scale transition on the other DAC—see Typical Performance Curves. It is dominated by digital coupling. Also, the integrated area of the glitch pulse is specified in nV–s. See table of electrical specifications. D11 (MSB) D9 D0 (LSB) AGND FIGURE 1. Simplified Circuit Diagram of DAC Cell. POWER SUPPLY CONNECTIONS The DAC4815 is specified for operation with power supplies of VL = +5V and VS = either ±12V or ±15V. Even with the VS supplies at ±11.4V the DACs can swing a full ±10V. Power supply decoupling capacitors (1µF tantalum) should be located close to the DAC power supply connections. DIGITAL FEEDTHROUGH Digital feedthrough is the noise at a DAC output due to activity on the digital inputs—see Typical Performance Curves. OPERATION Depending on the address selected, the 4 MSBs or the 8 LSBs are written into the appropriate input register for each DAC when the WR signal is brought low. The data are latched in the input register when the WR goes high. Data are then transferred from the input registers to the DAC latch registers by bringing LE low. The data are latched in the DAC latch registers when LE goes high. All DACs are updated simultaneously. When CLR is brought low, the input registers are cleared to 000HEX while the DAC registers = 800HEX. If LE is brought low after CLR the DACs are updated with 000HEX resulting in –10V (bipolar) or OV (unipolar) on the output. Separate digital and analog ground pins are provided to permit separate current returns. They should be connected together at one point. Proper layout of the two current returns will prevent digital logic switching currents from degrading the analog output signal. The analog ground current is code dependent so the impedance to the system reference ground must be kept to a minimum. Connect DACs as shown in Figure 2 or use a ground plane to keep ground impedance less than 0.1Ω for less than 0.1LSB error. ±10V OUTPUT RANGE CONNECTION For a ±10V bipolar output connect the DAC4815 as shown in Figure 3. CIRCUIT DESCRIPTION Each of the four DACs in the DAC4815 consists of a CMOS logic section, a CMOS DAC cell, and an output amplifier. One buried-zener +10.0V reference and a –10V reference are shared by all DACs. CONNECTION TO DIGITAL BUS DAC4815s can easily be connected to a µprocessor bus. Decode your address lines to derive the control signals shown in Figure 4. Only one LATCH signal is required for a system where all DAC4815s are updated simultaneously. If your want to update DAC4815s independently, use separate LATCH signals. The LATCH and WRITE signals can be brought low simultaneously to update the DAC registers with the same processor instruction that writes the final 8-bit data word the DAC input registers. Figure 1 is a simplified circuit for a DAC cell. An R, 2R ladder network is driven by a voltage reference at VREF. Current from the ladder is switched either to IOUT or AGND by 12 single-pole double-throw CMOS switches. This maintains constant current in each leg of the ladder regardless of digital input code. This makes the resistance at VREF constant (it can be driven by either a voltage or current reference). The reference can be either positive or negative polarity with a range of up to ±10V. CMOS switches included in series with the ladder terminating resistor and the feedback resistor, RFB, compensate for the temperature drift of the ladder switch ON resistance. The output op amps are connected as transimpedance amplifiers to convert the DAC-cell output current into an output voltage. They have been specially designed and compensated for precision and fast settling in this application. ® DAC4815 D10 8 DAC4815 DAC4815 DAC A DAC A VOUT A VOUT A DAC B DAC B VOUT B VOUT B DAC C DAC C VOUT C VOUT C DAC D DAC D VOUT D VOUT D AGND AGND R GND R GND NOTE: Ideally RGND = 0Ω FIGURE 2. Recommended Ground Connections for Multiple DAC Packages. ® 9 DAC4815 DAC4815 Data 5 +5V 11 10kΩ 10V Ref + 1µF 10kΩ 1µF LATCH A0 A5 +15V WRITE 1 A1 3 A2 20kΩ + 17 26 27 28 18-25 6 WRITE 2 20kΩ A1 15 17 DAC A 1µF 15 DAC4815 Data In CS 16 WR LE A0 A1 A2 4 8 –15V 18-25 2 VOUT A 26 7 27 28 + 20kΩ 20kΩ DAC B A2 1 VOUT B 13 VOUT C 12 VOUT D DAC4815 Data In CS 16 WR LE A0 A1 A2 FIGURE 4. Logic Connections for Multiple DAC4815 Packages. 20kΩ 8-Bit Port and Control In 20kΩ DAC C A3 20kΩ 20kΩ DAC D A4 9 10 AGND DGND FIGURE 3. Analog Connections for ±10V DAC Output. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DAC4815 10