SLES007– JULY 2001 FEATURES D Standard Digital Audio Interface Receiver D D D D D D D D D DESCRIPTION (EIAJ1201) Sampling Rate: 32 / 44.1 / 48 / 88.2 / 96 kHz Recover 128 / 256 / 384 / 512 fs System Clock Very Low Jitter System Clock Output (75 ps Typically) On-Chip Master Clock Oscillator, Only an External Crystal Is Required: 24.576 / 22.5792 / 18.432 / 16.9344 / 16.384 / 12.288 / 11.2896 / 8.192 / 6.144 / 5.6448 / 4.096 MHz Crystals Are Available Selectable Output PCM Audio Data Format Selectable Crystal Clock and PPL Clock Operation Mode Output User Bit Data, Flag Signals, and Channel Status Data With Block Start Signal Single 3.3-V Power Supply Package: 28 SSOP APPLICATIONS D AV Receiver D MD Player D DAC Unit The DIR1703 is a digital audio interface receiver (DIR) which receives and decodes audio data up to 96 kHz according to the AES/EBU, IEC958, S/PDIF, and EIAJCP340/1201 consumer and professional format interface standards. The DIR1703 demultiplexes the channel status bit and user bit directly to serial output pins, and has dedicated output pins for the most important channel status bits. It also includes extensive errors reporting. The significant advantages of the DIR1703 are 96-kHz sampling rate capability and Low-jitter clock recovery by the Sampling Period Adaptive Controlled Tracking (SpAct) system. The input signal is reclocked with the patented Sampling period Adaptive controlled tracking system for maximum quality. These features are required for recent consumer and professional audio instruments, in which the DIR has an interface to any kind of delta-sigma type ADC/DAC with a 96-kHz sampling rate. This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SpAct and Burr-Brown are trademarks of Texas Instruments. Copyright 2001, Texas Instruments Incorporated !"# $ % $ ! ! & ' $$ ()% $ ! * $ #) #$ * ## ! % www.ti.com 1 SLES007– JULY 2001 DIR1703 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ADFLG BRATE0 BRATE1 SCKO VDD DGND XTO XTI CKTRNS LRCKO BCKO DOUT SCF0 SCF1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CKSEL UNLOCK FMT1 FMT0 VCC AGND FILT RST DIN BRSEL BFRAME EMFLG URBIT CSBIT PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER DIR1703E SSOP 28 SSOP–28 324† OPERATION TEMPERATURE RANGE PACKAGE MARKING –25°C 25°C to +85°C 85°C DIR1703E BRSEL SCF CKSEL ORDERING NUMBER} TRANSPORT MEDIA DIR1703E Rails DIR1703E/2K Tape and Reel † TI equivalent no. 4040065. ‡ Models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of DIR1703E/2K will get a single 2000-piece tape and reel. block diagram VDD VCC FMT XTI OSC SCKO XTO BCKO OSC Selector PLL1 LRCKO Audio Clock And Data Generator 100 MHZ DIN ADFLG rdclk BRATE UNLOCK CKTRNS 2 URBIT EMFLG wrclk S/PDIF Decoder 2 BFRAME CSBIT PLL2 SpAct DOUT FIFO FILT www.ti.com RST DGND AGND SLES007– JULY 2001 Terminal Functions TERMINAL NAME PIN I/O DESCRIPTIONS ADFLG 1 O Audio data or digital data flag BRATE0 2 O BRATE1 3 O fs rate flag 0 (32 k, 44.1 k, 48 k, and 88 k / 96 k) fs rate flag 1 (32 k, 44.1 k, 48 k, and 88 k / 96 k) SCKO 4 O System clock output VDD DGND 5 – Digital power supply, +3.3 V 6 – Digital ground XTO 7 O Crystal oscillator output XTI 8 I Crystal oscillator input, external clock input CKTRNS 9 O Clock transition status output LRCKO 10 O Audio latch enable (LRCK, fs) output BCKO 11 O Audio bit clock output DOUT 12 O Audio serial data output SCF0 13 I System clock frequency select (128/256/384/512 fs) (see Note 1) SCF1 14 I System clock frequency select (128/256/384/512 fs) (see Note 1) CSBIT 15 O Channel status bit output (see Note 2) URBIT 16 O User bit output (see Note 2) EMFLG 17 O Emphasis flag BFRAME 18 O Block start clock (B-frame) BRSEL 19 I Default bit rate select (32 / 44.1 / 48 / 88.2 / 96 kHz) (see Note 1) DIN 20 I S/PDIF data digital input (see Note 4) RST 21 I Reset input, active LOW (see Note 3) FILT 22 – External filter AGND 23 – Analog ground VCC FMT0 24 – Analog power supply, 3.3V 25 I Audio data format select (see Note 1) FMT1 26 I Audio data format select (see Note 1) UNLOCK 27 O PLL unlock or parity error flag CKSEL 28 I System clock operation mode selected. Low: PLL, High: Crystal (see Note 1) NOTES: 1. 2. 3. 4. Schmitt trigger input with internal pulldown (TYP 51 kΩ), 5 V tolerant. Serial outputs are utilized for both consumer and professional application. Schmitt trigger input with internal pullup (TYP 51 kΩ), 5 V tolerant. CMOS level input with internal pulldown (TYP 51 kΩ), 5 V tolerant. www.ti.com 3 SLES007– JULY 2001 absolute maximum ratings† Supply voltage, VCC, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V Supply voltage differences, VCC, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V Ground voltage differences, AGND, DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V Digital input voltage: Digital input pins except XTI . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (6.5 V + 0.3 V) XTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VDD + 0.3 V) Input current (Any pins except supplies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead temperature (soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5 sec Package temperature (IR reflow, peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235°C, 10 sec † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 4 www.ti.com SLES007– JULY 2001 electrical characteristics, all specifications at TA = 25°C, VCC = VDD = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS DIGITAL INPUT/OUTPUT VIH (5) VIL (5) VIH2 (6) VIL2 (6) VIH3 (7) VIL3 (7) VOH (8) VOL (8) VOH (9) 2 MAX UNIT 5.5 70%VDD Input logic level 30%VDD 5.5 70%VDD VDC 30%VDD Output logic level Input leakage current IIH(6) IIL(6) fs(12) TYP 0.8 VOL (9) IIH(10) IIL(10) IIH(11) IIL(11) MIN IO = 1 mA IO = –2 mA VDD–0.4 IO = 2 mA IO = –4 mA VDD–0.4 0.5 VDC 0.5 VIN = VDD VIN = 0 V 65 –10 VIN = VDD VIN = 0 V –100 10 –10 VIN = VDD VIN = 0 V Input sampling frequency 10 –65 –10 10 –10 10 32 SCKO System clock frequency tj SCKO clock jitter 128/256/ 384/512 fs 75 SCKO duty cycle 50% 4.096 XTI clock accuracy 100 –500 See Table 3 µA 96 kHz 49.152 MHz ps RMS 500 ppm S/PDIF INPUT Duty cycle Jitter VIN = 1.5 V, VIN = 1.5 V fs = 96 kHz 15% 85% ±10 ns p-p 3.3 3.6 VDC 3.4 4.7 26 36 POWER SUPPLY REQUIREMENTS VDD, VCC ICC (VCC) IDD (VDD) PD Voltage range 3 Supply current (see Note 13) Power dissipation 100 mA mW TEMPERATURE RANGE Operation temperature θJA NOTES: 5. 6. 7. 8. 9. 10. 11. 12. 13. Thermal resistance –25 28-pin SSOP 85 100 °C °C/W TTL compatible, except pins 8, 20: XTI, DIN. Pin 8: XTI (CMOS logic level). Pin 20: DIN (CMOS logic level). Pins 1–3, 9, 17–18, 27: ADFLG, BRATE0, BRATE1, CKTRNS, EMFLG, BFRAME, UNLOCK. Pins 4, 10–12, 15–16: SCKO, LRCKO, BCKO, DOUT, CSBIT, URBIT. Pins 13–14, 19–20, 25–26, 28: SCF0, SCF1, BRSEL, DIN, FMT0, FMT1, CKSEL. Pin 21: RST fs is defined as the incoming audio sampling frequency per channel. No load connected to SCKO, LRCKO, BCKO, DOUT, CSBIT, URBIT. Power supply current varies according to the system clock frequency. www.ti.com 5 SLES007– JULY 2001 basic operation theory The DIR1703 is operated as either a PLL clock operation mode or a crystal clock operation mode. These basic operation modes are user selectable. Sampling period adaptive controlled tracking system (SpAct) is a newly developed clock recover architecture, giving very low jitter clock from S/PDIF data input. The DIR1703 has two PLLs, PLL1 and PLL2. SpAct is supplied with a 100 MHz executing clock from PLL1. The DIR1703 requires system clock input for operation of SpAct at both the PLL clock operation mode and the crystal clock operation mode. This system clock can be obtained by connecting a crystal resonator at the XTI/XTO pins or applying an external clock input at the XTI pin as shown in Figure 1. PLL2 generates the system clock SCKO by using the output signal of the SpAct. The source of SCKO, either OSC (crystal) or PLL2, is selected by the CKSEL pin (called PLL clock operation mode and crystal clock operation mode). In the PLL clock operation mode, when the S/PDIF signal goes to noninput, SCKO may hold the latest tracked frequency. Also, the DIR1703 indicates the unlocked state by a high level output at the UNLOCK pin. When the S/PDIF signal restarts, the analog PLL will lock to the incoming S/PDIF signal with very low jitter. The PLL lock-in time is around 1 ms using the SpAct. Then, the DIR1703 indicates the locked status by a low output at the UNLOCK pin. In this status, the BRATE pins simultaneously indicate the bit rate of the incoming S/PDIF signal. After RST (pin 21) is removed, SCKO is set to the default frequency, which can be selected by the BRSEL and SCF pins. The sampling rate (fS), 32 k, 44.1 k, 48 k, 88.2 k, or 96 k is selected by the BRSEL pin. The system clock frequency, 128, 256, 384, or 512 fS is also selected by the SCF pins. In the crystal clock operation mode, the crystal oscillator generates three audio clocks SCKO, BCKO, and LRCKO. In this mode, DOUT is always set to mute (zero). BRATE and UNLOCK can be indicated according to the incoming S/PDIF signal. If CKSEL (pin 28) is connected to UNLOCK (pin 27), which indicates the S/PDIF decoding status and the PLL2 lock-state, the system clock source can be selected automatically when the S/PDIF signal is active and the bit rate is detected. C1 External Clock Crystal XTI R1 XTAL OSC CIR XTI Open XTO XTO C2 R1 = 1 MΩ, C1, C2 = 10 TO 33 pF DIR1703 Crystal Resonator Connection Figure 1. System Clock Connections 6 XTAL OSC CIR www.ti.com DIR1703 External Clock Input SLES007– JULY 2001 system clock output The primary function of the DIR1703 is to recover audio data and a low jitter clock from a digital audio transmission line. The system clock (SCKO) can be selected in two clocks that are generated by the crystal oscillator clock (crystal mode) or the PLL clock (PLL mode) by the SpAct. The two operation modes are selected by the CKSEL pin. In the PLL clock operation mode, the clock that can be generated is SCKO (128 / 256 / 384 / 512 fS, shown in Table 1), BCKO (64 fS), and LRCKO (1 fS). SCKO is the output of the voltage controlled oscillator (VCO) in an analog PLL. The PLL function consists of a VCO, phase and frequency detector, and a external second-order loop filter. The closed-loop transfer function, which specifies the PLL jitter attenuation characteristics, is shown in Figure 2. In the crystal clock operation mode, SCKO can be generated from several crystal oscillators shown in Table 2. The crystal frequency should be defined for internal PLL by connecting the BRSEL pin to one of the output pins BFRAME, EMFLG, URBIT, or CSBIT as shown in Table 3. A 12.288 MHz crystal resonator can be used for 96-kHz – 128 fS (CSBIT), 48-kHz – 256 fS (OPEN) and 32-kHz – 384 fS (BFRAME). If BRSEL is not connected to any pins, the 48-kHz sampling rate is selected. The system clock frequency of both modes can be selected by control data at SCF0 and SCF1 pins shown in Table 4. Table 5 shows the state of the system and the condition of audio clocks and flags in both the PLL and crystal operation modes. In the crystal clock operation mode, SpAct also detects the bit rate of the incoming S/PDIF signal and indicates the state at the UNLOCK pin. Therefore, by connecting CKSEL pin 28) to UNLOCK (pin 27), the system clock source can be selected automatically when the S/PDIF signal arrives and the bit rate is detected. The required accuracy for clock frequency of the crystal resonator or external clock input is ±500 ppm. Table 1. Generated System Clock (SCKO) PLL Clock Operation Mode SAMPLING RATE 128 fS 256 fS 384 fS 512 fS 32 kHz yes yes yes yes 44.1 kHz yes yes yes yes 48 kHz yes yes yes yes 88.2 kHz yes yes yes yes 96 kHz yes yes yes yes 1k 1M 10 k 100 k f – Frequency – kHz Closed Loop Gain – dB 0 –20 –40 –60 –80 –100 100 10 M 100 M Figure 2. Jitter Attenuator Characteristics With Specified Loop Filter www.ti.com 7 SLES007– JULY 2001 system clock output (continued) Table 2. Generated System Clock (SCKO) Crystal Clock Operation Mode SAMPLING RATE 128 fS 256 fS 384 fS 512 fS 32 kHz yes yes yes yes 44.1 kHz yes yes yes yes 48 kHz yes yes yes yes 88.2 kHz yes yes yes yes 96 kHz yes yes See Note 14 See Note 14 NOTE 14: External clock only Table 3. Selectable Crystal Oscillator SAMPLING RATE 128 fS 256 fS 384 fS 512 fS 32 kHz 4.096 MHz 8.192 MHz 12.288 MHz 16.384 MHz BFRAME 44.1 kHz 5.6448 MHz 11.2896 MHz 16.9344 MHz 22.5792 MHz EMFLG 48 kHz 6.144 MHz 12.288 MHz 18.432 MHz 24.576 MHz open 45.1584 MHz (see Note 14) URBIT 49.152 MHz (see Note 14) CSBIT 88.2kHz 11.2896 MHz 22.5792 MHz 33.8688 MHz (see Note 14) 96 kHz 12.288 MHz 24.576 MHz 36.864 MHz (see Note 14) Table 4. System Clock Selection 8 BRSEL CONNECTED TO SCF1 SCF0 SYSTEM CLOCK LOW LOW 128 fS LOW HIGH 256 fS HIGH LOW 384 fS HIGH HIGH 512 fS www.ti.com SLES007– JULY 2001 system clock output (continued) Table 5. System Clock Operation Mode CONDITIONS MODE CKSEL CLOCK AND DATA OUTPUTS S/PDIF DATA SCKO BCKO LRCKO DOUT BRATE UNLOCK CS. UR BIT AD. EMFLG Default PLL† Default Default PLL† PLL† (128, 256, 384, 512 MUTE LOW HIGH LOW LOW (64 fS) (1 fS) fS) PLL PLL PLL (128, 256, 384, 512 YES DATA DETECT LOW DATA DATA PLL LOW (64 fS) (1 fS) fS) HOLD‡ HOLD‡ HOLD‡ Unknown HOLD‡ (128, 256, 384, 512 NO MUTE HIGH HOLD‡ (64 fS) (1 fS) fS) Crystal Crystal Crystal After (128, 256, 384, 512 MUTE LOW HIGH LOW LOW RESET (64 fS) (1 fS) fS) Crystal Crystal Crystal Unknown (128, 256, 384, 512 YES MUTE DETECT LOW LOW CRYSTAL HIGH (64 fS) (1 fS) fS) Crystal Crystal Crystal Unknown LOW (128, 256, 384, 512 NO MUTE Unknown HIGH (64 fS) (1 fS) fS) † In the PLL mode, the DIR1703 will be the same frequencies as the crystal mode after RESET; however, the frequency error is below 1%. ‡ Holds the latest tracked frequency. After RESET SCKO timing tSCKH H 2V SCKO 0.8 V L tSCKL SCKO Clock Pulse Width High SCKO Clock Pulse Width Low tSCKH tSCKL System Clock Pulse Cycle Time† 7 ns (min) 7 ns (min) † 1/128 fS, 1/256 fS, 1/384 fS or 1/512 fS. www.ti.com 9 SLES007– JULY 2001 bit rate detection By using the SpAct frequency estimator (not the S/PDIF channel status bit), the DIR1703 automatically detects the sample rate of an incoming S/PDIF signal and indicates the frequency at the BRATE pins. Table 6 lists the frequency ranges reported. Except for 88.2 and 96 kHz, these sample rates are the same as the channel status bit defined in the S/PDIF specifications. When the bit-rate is 88.2 or 96 kHz the indicator shows the same HL value. This state is not defined in the S/PDIF specifications. Table 6. Incoming Sample Frequency Bits SAMPLING RATE BRATE1 BRATE0 32 kHz HIGH HIGH 44.1 kHz LOW LOW 48 kHz LOW HIGH 88.2 kHz HIGH LOW 96 kHz HIGH LOW timing specification for PLL operation lock-up time PLL Condition Unlock Lock DIN Start PLL Status Indicator Pin Site UNLOCK H L tINT< 1 ms Figure 3. PLL Lock Up Timing relation between audio-data-output timing and PLL condition indicator timing In the PLL clock operation mode, when the S/PDIF signal is not detected after reset removal, audio clocks (SCKO, BCKO, LRCKO) which are not related to S/PDIF signal are generated by SpAct. The bit rate can be selected by setting pin BRSEL. If BRSEL is OPEN or connected to DGND, the default bit rate frequency is set to 48 kHz. If BRSEL is connected to one of the output pins BFRAME, EMFLG, URBIT, or CSBIT, the frequency is set to 32, 44.1, 88.2, or 96 kHz, respectively. Therefore, the initial frequency is the same as the crystal resonator, however, its error frequency is below 1% after reset. When the analog PLL is still unlocked after at least ten rising-edges of the S/PDIF, a S/PDIF decoder can detect the incoming S/PDIF signal. Thus, DOUT becomes low (MUTE) until the analog PLL locks. This MUTE period is less than 1 ms (analog PLL’s lock-up time is less than 0.5 ms). When the decoder does not detect an incoming S/PDIF signal, UNLOCK will output high level status at the LRCKO clock transition. SCKO keeps its frequency at the latest tracked bit rate. 10 www.ti.com SLES007– JULY 2001 relation between audio-data-output timing and PLL condition indicator timing (continued) Unlock Lock PLL Condition H UNLOCK L LRCKO BCKO DOUT Mute 1 31 2 32 Mute Figure 4. Relation Between Audio Data Output Timing and UNLOCK Flag Timing unlock flag minimum pulse width time CASE-A when PLL is unlocked In the PLL clock operation mode, when PLL goes to unlock by a disconnected S/PDIF signal, the UNLOCK flag pin indicates high and the audio data output DOUT becomes low (MUTE). The MUTE period, t(UNL), is a minimum of 200 ms. In this period, SCKO, BCKO, and LRCKO frequencies hold the latest tracked frequency. If the S/PDIF signal is connected again in this unlock period, the bit rate is changed to the incoming signal frequency, after at least 1 ms (before the UNLOCK flag becomes low). CKTRNS indicates the validity of SCKO. When CKTRNS is high, the frequency of SCKO, BCKO, and LRCKO is in transition. www.ti.com 11 SLES007– JULY 2001 t(UNL)>200 ms UNLOCK H L LRCKO CKTRANS S/PDIF Signal Bit Rate S/PDIF Signal Starts Again New Bit Rate BCKO t(TRNS) < 1 ms 1 DOUT 2 Mute Figure 5. UNLOCK Flag Minimum Pulse Width Time for PLL Unlocked CASE-B when parity error occurs When a parity error occurs in one subframe interval, UNLOCK becomes high during this subframe, then returns low at the next arriving subframe. During this subframe with parity error, the data output will hold the previous data of each channel. CASE-B When Parity Error Occurs H UNLOCK L LRCKO BCKO DOUT 24 1 24 Same as The Previous Data Figure 6. UNLOCK Timing for Parity Error 12 www.ti.com 1 2 SLES007– JULY 2001 PCM audio interface The DIR1703 can produce 16-bit or 24-bit output data in standard format and 24-bit output data in IIS format. The PCM audio interface format of the DIR1703 is selected using the format pins FMT1, FMT0. Table 7 shows the FMT pin configuration. Table 7. Audio Output Data Format Select FMT1 FMT0 AUDIO DATA FORMAT LOW LOW 16 bit MSB first, Right justified LOW HIGH 24 bit MSB first, Right justified HIGH LOW 24 bit MSB first, Left justified HIGH HIGH 24 bit IIS Standard Data Format; L–Channel = HIGH, R–Channel = LOW 1/fS LRCKO R–Channel L–Channel BCKO Right Justified Audio Data Word = 16–Bit 1 2 DOUT 14 15 16 MSB Right Justified Audio Data Word = 24–Bit DOUT 22 23 24 DOUT 1 2 23 24 LSB MSB 1 2 LSB MSB 23 2 4 1 2 LSB MSB 15 16 LSB MSB 23 24 1 2 Left Justified Audio Data Word = 24–Bit 1 2 15 16 LSB 23 24 LSB MSB IIS Data Format; L–Channel = LOW, R–Channel = HIGH 1/fS LRCKO L–Channel R–Channel BCKO Audio Data Word = 24–Bit DOUT 1 2 MSB 23 24 LSB 1 2 MSB 23 24 1 LSB Figure 7. Audio Data Output Format www.ti.com 13 SLES007– JULY 2001 PCM audio interface (continued) 50% of VDD SCKO t(SL) t(LS) 50% of VDD LRCKO t(BCH) t(BCL) t(LB) 50% of VDD BCKO t(BCY) t(BL) 50% of VDD DOUT t(DS) t(DH) PARAMETERS MIN MAX UNITS t(SL) t(LS) SCKO rising edge to LRCKO edge 11 ns LRCKO edge to SCKO rising edge 5 ns t(BCY) t(BCL) BCKO pulse cycle time BCKO pulse width low 78 ns t(BCH) t(BL) BCKO pulse width high 78 ns BCKO rising edge to LRCKO edge 78 ns t(LB) t(DS) LRCKO edge to BCKO rising edge 78 ns DOUT setup time 78 ns t(DH) DOUT hold time 78 ns 64 fS Figure 8. Audio Data Output Timing dedicated output pins for both professional and consumer applications The DIR1703 has parallel output pins for both professional and consumer applications. In the professional mode de-emphasis flag EMFLG indicates a 50/15-µs time constant pre-emphasis. Professional mode is set when Bit 0 of CSBIT Byte 0 is high. When Bits 2 to 4 of CSBIT Byte 0 is 110, the EMFLG becomes high. In other cases, EMFLG is low. Audio/non-audio flag ADFLG indicates S/PDIF data mode, i.e., Bit 1 of CSBIT Byte 0. When ADFLG is low, S/PDIF data includes PCM audio signal. In other cases, ADFLG is high. In the consumer mode EMFLG indicates 2-channel audio with a 50/15-µs time constant pre-emphasis. Consumer mode is set when Bit 0 of CSBIT Byte 0 is low. When Bits 3 to 5 of CSBIT Byte 0 is 100, EMFLG becomes high. In other cases, EMFLG is low. The ADFLG signal indicates whether S/PDIF includes digital data, such as AC-3 or not. When Bit 1 of CSBIT Byte 0 is high, the incoming S/PDIF includes a non-audio signal. In other cases, ADFLG is low. These dedicated output pins are checked for only L-ch CS information. The DIR1703 does not support CRC check function in the professional mode. As for other flags, CS bit and user-bit for professional and consumer applications, are directly supplied by serial mode at CSBIT (pin 15) and URBIT (pin 16). These pins indicate L-ch and R-ch information sequentially. 14 www.ti.com SLES007– JULY 2001 dedicated output pins for both professional and consumer applications (continued) Audio data and clock timing are described below. The serial output data starts after 16±8 BCKO clocks from when the corresponding subframe arrives. When B subframe arrives, the BFRAME pin becomes high during 1/fs x 32 (s), then BFRAME returns to low after 32 frames. S/PDIF 1/fS (S) Frame 0 B W M Frame 1 W M Frame 191 W Frame 0 B 16 ± 8 BCKO Delay 64 BCKO URBIT/CSBIT/UNLOCK etc. L0 R0 L1 R1 L191 R191 LRCKO BFRAME 1/fS x 32 (S) 1/fS x 192 (S) LRCKO BCKO DOUT 64 1 2 3 Figure 9. Timing Chart for Audio Data and Channel Status www.ti.com 15 SLES007– JULY 2001 reset sequence The DIR1703 requires external reset operation after power on. Figure 10 shows the reset sequence after power on. The DIR1703 is ready for receiving S/PDIF signal when the internal reset sequence has finished and CKTRNS goes to LOW. BFRAME, EMFLG, URBIT and CSBIT pins are used for configuration during the period from the rising edge of RST to the falling edge of CKTRNS. S/PDIF signal is accepted after CKTRNS goes to LOW. The minimum pulse width of RST, tRST is 100 ns. The RST delay after the power supply reaches 3 V should be at least 10 ms. All of the output pins except CKTRNS and UNLOCK are LOW during RST LOW. 3V VDD, VCC XTI Stable Unstable XTO DIR1703 Ready Internal PLL ON tSTT > 10 ms RST BFRAME, EMFLG, VRBIT, CSBIT LOW HIGH tRST > 100 ns 12.5XTI Clock Chip Status Information LOW LOW Unknown Valid 1160XTI Clock CKTRNS HIGH < 5 fs S/PDIF Acceptable DIN < 1 ms UNLOCK HIGH NOTE: SCF0 and SCF1 should be settled during RST assertion. The change of SCF0 and SCF1 is not permitted during normal operation. When the change is needed, the reset sequence must be started by asserting RST again. Figure 10. After Power ON 16 www.ti.com SLES007– JULY 2001 typical circuit connection 1 2 Bit Rate Indicator 3 4 5 3.3 V VDD + C1 C3 6 7 R1 C5 8 9 C6 10 11 12 13 System Clock Frequency Select (128,256,348, 512 fs) 14 ADFLG CKSEL BRATE0 UNLOCK BRATE1 FMT1 SCKO FMT0 VDD DGND VCC AGND XTO FILT XTI RST CKTRNS DIN LRCKO BRSEL BCKO BFRAME DOUT EMFLG SCF0 URBIT SCF1 CSBIT For Automatic System Clock Selection 27 26 Data Format Select 25 24 23 22 21 20 C7 R2 C4 + 3.3 V VCC C2 C8 Reset (Active LOW) Receiver Circuit 19 18 17 16 15 BRSEL Connection Depends Upon Crystal Resonator Frequency. Audio Data Processor C1 , C2: C3 , C4: C5 , C6: C7: C8: R1: R2: 28 Bypass Capacitor, 1 µF to 10 µF Bypass Capacitor, 0.01 µF to 0.1 µF OSC Capacitor, 10 to 33 pF Loop Filter Capacitor, 0.068 µF Loop Filter Capacitor, 0.0082 µF OSC Resistor, 1 MΩ Loop Filter Resistor, 1.2 kΩ www.ti.com 17 SLES007– JULY 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,15 NOM 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 0°–ā8° A 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065/D 09/00 NOTES: A. B. C. D. 18 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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