® PGA102 High Speed PROGRAMMABLE GAIN AMPLIFIER FEATURES DESCRIPTION ● DIGITALLY PROGRAMMABLE GAIN: G = 1, 10, 100 The PGA102 is a high speed, digitally programmablegain amplifier. CMOS/TTL-compatible inputs select gains of 1, 10 or 100V/V. Each gain has an independent input terminal, providing an input multiplexer function. ● LOW GAIN ERROR: 0.025% max ● FAST SETTLING: 2.8µs to 0.01% ● 16-PIN PLASTIC AND CERAMIC DIP On-chip metal film gain-set resistors are laser-trimmed to provide excellent gain accuracy. High speed input circuitry allows multiplexing of high speed signals. APPLICATIONS The PGA102 is available in 16-pin plastic and ceramic DIP packages. Commercial, industrial and military temperature range models are available. ● DATA ACQUISITION AMPLIFIER ● FIXED-GAIN AMPLIFIER ● AUTOMATIC GAIN SCALING 1.33kΩ Common Force 4 Common Sense 5 1.2kΩ 10.8kΩ 1.2kΩ 10.8kΩ 6 VIN1 Gain Adj. PGA102 10.8kΩ 10 VIN2 Gain Adj. VIN3 15 7 VOUT 9 8 Gain/Channel Select 13 –VCC 16 +VCC 3 1 Logic X10 Ground Select 2 X100 Select 11 12 Offset Adjust International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1985 Burr-Brown Corporation PDS-579C 1 PGA102 Printed in U.S.A. September, 1993 SPECIFICATIONS ELECTRICAL At +25°C, ±VCC = 15VDC unless otherwise specified. PGA102AG PARAMETER CONDITIONS GAIN Inaccuracy(1) MIN RL = 2kΩ, G = 1 G = 10 G = 100 G=1 G = 10 G = 100 RL = 2kΩ, G = 1 G = 10 G = 100 vs Temperature Nonlinearity RATED OUTPUT Voltage Current Short Circuit Current Output Resistance Load Capacitance RL = 2kΩ VOUT = 10V For Stable Operation INPUT OFFSET VOLTAGE Initial(2) vs Temperature vs Supply Voltage INPUT BIAS CURRENT Initial Over Temperature ANALOG INPUT CHARACTERISTICS Voltage Range Resistance Capacitance INPUT NOISE Voltage Noise Voltage Noise Density Current Noise Current Noise Density DYNAMIC RESPONSE ±3dB Bandwidth Full Power Bandwidth Slew Rate ±10 ±5 ±10 PGA102BG, SG TYP MAX ±0.007 ±0.015 ±0.02 ±0.4 ±2 ±7 0.001 0.002 0.003 ±0.02 ±0.03 ±0.05 ±5 ±7 ±20 0.003 0.005 0.01 ±12.5 ±10 ±25 0.01 2000 * * * PGA102KP TYP MAX ±0.003 ±0.01 ±0.015 * * * * * * ±0.01 ±0.02 ±0.025 * * * * * * * * * * * MIN * * * TYP MAX UNITS * * * * * ±9 * * * * ±0.05 ±0.06 * * * * * * % % % ppm/°C ppm/°C ppm/°C % of FS % of FS % of FS * * * * * V mA mA Ω pF G=1 G = 10 G = 100 G=1 G = 10 G = 100 ±5 < V CC < ±18V G=1 G = 10 G = 100 ±200 ±70 ±70 ±5 ±1 ±0.5 ±500 ±200 ±200 ±20 ±7 ±3 ±100 ±50 ±50 * * * ±250 ±100 ±100 * * * * * * ±7 ±3 ±2 ±1500 ±600 ±600 ±50 ±10 ±7 µV µV µV µV/°C µV/°C µV/°C ±30 ±8 ±8 ±70 ±30 ±30 * * * * * * * * * * * * µV/V µV/V µV/V TA = +25°C TA MIN to TA MAX ±20 ±25 ±50 ±60 * * * * * * * * nA nA Linear Operation ±10 fB = 0.1Hz to 10Hz G=1 G = 10 G = 100 fO = 1Hz, G = 1 G = 10 G = 100 fO = 10Hz, G = 1 G = 10 G = 100 fO = 100Hz, G = 1 G = 100 G = 100 fO = 1kHz, G = 1 G = 10 G = 100 fB = 0.1Hz to 10Hz fO = 1Hz fO = 10Hz fO = 100Hz fO = 1kHz Small Signal, G = 1 G = 10 G = 100 VOUT = ±10V, RL = 2kΩ VOUT = ±10V Step, RL = 2kΩ 6 ±12 7 X 108 4 * * * * * * * * V Ω pF 4.5 1.5 0.6 490 178 83 155 56 20 93 31 18 79 31 18 76 8.8 2.8 0.99 0.43 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * µVp-p µVp-p µVp-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz pAp-p pA/√Hz pA/√Hz pA/√Hz pA/√Hz 1500 750 250 160 * * * * * * * * kHz kHz kHz kHz * V/µs 9 * ® PGA102 MIN 2 * * SPECIFICATIONS (CONT) ELECTRICAL At +25°C, ±VCC = 15VDC unless otherwise specified. PGA102AG PARAMETER CONDITIONS MIN DYNAMIC RESPONSE (CONT) Settling Time (0.1%) VOUT = 10V Step, G = 1 G = 10 G = 100 Settling Time (0.01%) VOUT = 10V Step, G = 1 G = 10 G = 100 Overload Recovery 50% Overdrive, G = 1 Time, 0.1% (see Performance Curve) CROSSTALK DC 60Hz DIGITAL INPUT CHARACTERISTICS Input “Low” Threshold Input “Low” Current Input “High” Threshold Input “High” Current Logic Threshold Control Switching Time(4) POWER SUPPLY Rated Voltage Voltage Range Quiescent Current TEMPERATURE RANGE Specification, KP Grade AG and BG Grades SG Grade Operating Storage Thermal Resistance ±10V to Both Off Channels ±10V to Both Off Channels TYP TYP MAX UNITS –155 –144 * * * * dB dB VLTC+0.8 1 1 1 VCC – 4 * * * 1 ±15 ±2.4 * * * * * * * * * * ±18 ±3.3 * * ±5.3 –25 +85 * * * –55 –65 +125 +150 100 * +125 * * * V µA V µA V µs * * VDC VDC mA * mA 0 +70 –25 –55 +85 +125 °C °C °C °C °C °C/W * * * * –55 * * * * * * * * TA MIN to TA MAX θJA MIN µs µs µs µs µs µs µs –VCC VOUT = 0V No External Load, VOUT = ±10V PGA102KP MAX * * * * * * * VLTC+2 ±5 TYP * * * * * * * 0.1 VLTC on Pin 3 Between Channels MIN 1.6 2.2 5.2 2.8 2.8 8.2 2.5 VIL(3) on Pin 1 or 2 VIH(3) on Pin 1 or 2 PGA102BG MAX * * Specification same as AG grade. NOTES: (1) Gain inaccuracy is the percent error between the actual and ideal gain selected. It may be externally adjusted to zero for gains of 10 and 100. (2) Offset voltage can be adjusted for any one channel. Adjustment affects temperature drift by approximately ±0.3µV/°C for each 100µV of offset adjusted. (3) Voltage on the logic threshold control pin, VLTC, adjusts the threshold for “Low” and “High” logic levels. (4) Total time to settle equals switching time plus settling time of the newly selected gain. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 PGA102 PIN CONFIGURATION Top View DIP X10 Select 1 16 +VCC X100 Select 2 15 VOUT Logic Threshold Control 3 14 NC(1) Common Force 4 13 –VCC Common Sense 5 12 Offset Adjust VIN1 (X1) 6 11 Offset Adjust VIN2 (X10) 7 10 Gain Adjust (X10) VIN3 (X100) 8 9 Gain Adjust (X100) NOTE: (1) No Internal Connection. PACKAGE INFORMATION ABSOLUTE MAXIMUM RATINGS Power Supply .................................................................................... ±18V Input Voltage Range: Analog ............................................................ ±VCC Digital ................................. (VPIN 3 – 5.6V) to +VCC Storage Temperature Range: G Package .................... –65°C to +150°C P Package ..................... –55°C to +125°C Lead Temperature (soldering, 10s) ............................................... +300°C Output Short Circuit Duration .............................. Continuous to Common Junction Temperature: G Package ............................................... +175°C P Package ................................................ +110°C MODEL PGA102AG PGA102BG PGA102SG PGA102KP PGA102AG PGA102BG PGA102SG PGA102KP PACKAGE TEMPERATURE RANGE 16-Pin Hermetic DIP 16-Pin Hermetic DIP 16-Pin Hermetic DIP 16-Pin Plastic DIP –25°C to +85°C –25°C to +85°C –55°C to +125°C 0°C to +70°C ® PGA102 PACKAGE DRAWING NUMBER(1) 16-Pin Hermetic DIP 16-Pin Hermetic DIP 16-Pin Hermetic DIP 16-Pin Plastic DIP 109 109 109 180 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION MODEL PACKAGE 4 TYPICAL PERFORMANCE CURVES TA = +25°C, ±VCC = 15VDC unless otherwise noted. GAIN ERROR vs TEMPERATURE NONLINEARITY vs TEMPERATURE 0.1 .006 G = 100 .005 Nonlinearity (% FS) Gain Error (%) .075 .05 G = 10 .025 G=1 0 .004 G = 100 .003 G = 10 .002 –.025 G=1 .001 –.05 –60 –40 –20 0 20 40 60 80 100 0 –60 –40 –20 120 140 0 20 Temperature (°C) SETTLING TIME vs TEMPERATURE 60 80 100 120 140 SMALL SIGNAL FREQUENCY RESPONSE 10 50 9 G = 100 G = 100 40 8 7 30 6 Gain (dB) Settling Time (µs) 40 Temperature (°C) 5 4 G = 1, 10 3 G =10 20 10 Large Signal G=1 2 0 1 0 –60 –40 –20 Large Signal –10 0 20 40 60 80 100 120 140 10 100 1k Temperature (°C) 10k 100k 1M 10M 10 12 Frequency (Hz) SMALL SIGNAL STEP RESPONSE SLEW RATE vs TEMPERATURE 13 G=1 100 12 11 Output (mV) Slew Rate (V/µs) Positive 10 9 G = 10 0 G =100 Negative –100 8 7 –60 –40 –20 0 20 40 60 80 100 0 120 140 2 4 6 8 Time (µs) Temperature (°C) ® 5 PGA102 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, ±VCC = 15VDC unless otherwise noted. LARGE SIGNAL STEP RESPONSE OVERLOAD RECOVERY vs INPUT OVERLOAD 10 Overload Recovery Time (µs) 9 10 Output (V) G=1 G = 10 0 G = 100 –10 8 G = 100 7 6 5 4 G = 10 3 2 G=1 1 0 0 2 4 6 8 10 0 12 5 Time (µs) 10 15 Input Overload Voltage (V) INPUT VOLTAGE AND CURRENT NOISE vs FREQUENCY INPUT CROSSTALK vs FREQUENCY 1k 1k –40 100 G = 10 G = 100 10 10 Current Noise (G = 1 to 100) 1 0.1 10 1 100 1k 10k 1 –60 Input Crosstalk (dB) G=1 100 Current Noise Density (pA/√Hz) Voltage Noise Density (nV/√Hz) Voltage Noise –80 –100 –120 –140 –160 0.1 100k 1 10 100 1k 10k 100k 1M Frequency (Hz) Frequency (Hz) POWER SUPPLY REJECTION vs FREQUENCY QUIESCENT CURRENT vs TEMPERATURE 120 3 G = 100 Quiescent Current (mA) Power Supply Rejection (dB) VCC = ±15V 100 G = 10 80 G=1 60 40 2 VCC = ±5V 1 20 0 1 10 100 1k 10k 100k 0 –60 1M Frequency (Hz) –20 0 20 40 60 Temperature (°C) ® PGA102 –40 6 80 100 120 140 APPLICATION INFORMATION OFFSET ADJUSTMENT The offset voltage of each of the three input stages is lasertrimmed. Many applications require no further adjustment. The optional trim circuit shown in Figure 1 can be used to adjust the offset voltage. This adjustment affects the offset of all three gain channels. Since each gain setting may require a different adjustment of the potentiometer, this requires a compromise. Often, offset voltage of the G = 100 channel is the most important, so adjustment can be optimized for this channel only. Alternatively, Figure 2 shows a CMOS switch used to select independent offset adjustment potentiometers for each of the three channels. Use these offset adjustment techniques only to null the offset voltage of the PGA102. Do not null offset produced by the signal source or other system offsets or this will increase the temperature drift of the PGA102. Figure 1 shows the basic connections required for operation of the PGA102. Power supplies should be bypassed with 0.1µF capacitors located close to the device pins. The inputs for each gain are independent and can be connected to three separate signal sources. Or, for many applications, the three inputs are connected in parallel to form a single input—see Figure 1. Only the input corresponding to the selected gain is active, operating as a non-inverting amplifier. The two inactive inputs behave as open circuits. The input bias current of the inactive inputs is negligible compared to that of the selected input. –VCC +VCC –VCC Optional Offset Trim –15V +15V 0.1µF 100kΩ 11 VIN1 13 0.1µF 12 6 6 VIN = 0V 16 VIN2 VIN3 7 15 7 3 8 VO 4 2 1 45 12 Output Ground 3 Adjust for VOUT = 0V for all channels. 15 PGA102 5 8 Input Ground 16 13 1 2 11 +15V R1 100kΩ Analog Ground 14 11 12 7 Digital Ground INPUT GAIN G=1 VIN1 VIN2 G = 10 VIN3 G = 100 — Invalid — X10 0 1 0 1 X100 0 0 1 1 R2 100kΩ Logic “0”: 0V ≤ V ≤ 0.8V Logic “1”: 2V ≤ V ≤ +VCC Logic voltages are referred to pin 3. R3 100kΩ Offset Adjusts FIGURE 1. Basic Circuit Connections. DIGITAL INPUTS Gain is selected by the digital input pins, "X10" and “X100”. The threshold of these logic inputs is approximately 1.3V above the voltage on pin 3. For CMOS or TTL logic signals, connect pin 3 to logic ground. The logic inputs are not latched. Any change logic inputs immediately selects a new gain. Switching time is approximately 1µs. This does not include the time required for the analog output to settle to a new output value (see settling time specifications). 1 CH1 2 4016 CMOS SWITCH 4 CH2 3 –VCC 9 8 CH3 CH1CH2CH3 6 A 5 B 0 0 1 13 C 0 1 0 1 CH1 0 CH2 0 CH3 FIGURE 2. Independent Offset Adjustment of Channels 1, 2, and 3. GAIN ADJUSTMENT Gain of the PGA102 is accurately laser trimmed and usually requires no further adjustment. The optional circuit in Figure 3 allows independent gain adjustment of the G = 10 and G = 100 inputs. Note that the two logic inputs allow four possible logic states—see Figure 1 for the logic table. A logic “1” on both inputs is an invalid code. This will not damage the device, but the analog output voltage will not be predictable while this code is applied. ® 7 PGA102 The gain of the G = 10 and G = 100 inputs can be changed by adding external resistors to the internal feedback network as shown in Figures 4 and 5. The internal gain-set resistors are trimmed for precise ratios, not to exact values. The internal resistor values are within approximately ±30% of 6 VIN1 (X1) 7 VIN2 (X10) 8 6 VIN1 (X1) CH1 7 VIN2 (X10) 10 CH2 10 VIN3 (X100) the nominal values shown on the front page diagram. This makes the external resistor values in Figures 4 and 5 subject to variation—especially for gains differing greatly from the initial value. 15 PGA102 15 PGA102 8 VIN3 (X100) VOUT 5 4 9 5 4 CH3 VOUT 9 RX10 DN R5 100kΩ RX10 DN ≈ – R4 R6 1MΩ 18MΩ R2 620kΩ X100 Fine Adjust R1 R3 1MΩ 12MΩ RX100 DN ≈ 100 6 15 PGA102 9 VOUT 5 7 V1 4 3.32kΩ RX10 UP ≈ RX100 UP 4 – VIN + 5 Force OPA602 VO Sense VO = G (V2 – V1) 3.32kΩ 10.8kΩ GX10 UP – 10 3.32kΩ PGA102 8 RX10 UP ) G = 1, 10, 100 8 VIN3 (X100) 108kΩ – 1.09kΩ 100 – GX100 DN FIGURE 5. Connections for Lower Gains. 7 10 ( ) RX10 DN ≈ 8.64kΩ and RX100 DN ≈ 107kΩ gives gains of 1, 5, 50 6 VIN2 (X10) 97.2kΩ + 10.8kΩ GX10 DN – 10 Example: X10 Fine Adjust FIGURE 3. Optional Fine Gain Adjustment. VIN1 (X1) ( RX100 DN 3.32kΩ OPA602 V2 108kΩ RX100 UP ≈ GX100 UP – 100 Example: RX10 UP ≈ 1.08kΩ and RX100 UP ≈ 1.08kΩ gives gains of 1, 20, 200 FIGURE 4. Connections for Higher Gains. FIGURE 6. High-Speed Instrumentation Amplifier. ® PGA102 8