CHERRY CS3843AGD14

Off-Line Current Mode PWM Control
Circuit with Undervoltage Lockout
Description
Features
the output stage is enabled. Ion
implant resistors provide tighter control of undervoltage lockout.
The CS284XA, CS384XA provides all
the necessary features to implement
off-line fixed frequency current-mode
control with a minimum number of
external components.
Other features include low start-up
current, pulse-by-pulse current limiting, and a high-current totem pole output for driving capacitive loads, such
as the gate of power MOSFET. The output is LOW in the off state, consistent
with N-channel devices.
The CS384XA family incorporates a
new precision temperature-controlled
oscillator with an internally trimmed
discharge current to minimize variations in frequency. A precision dutycycle clamp eliminates the need for an
external oscillator when a 50% dutycycle is used. Duty-cycles greater than
50% are also possible. On board logic
ensures that VREF is stabilized before
The CS384XA series of current-mode
control ICs are available in 8 and14
lead packages for surface mount (SO)
applications as well as 8 lead PDIP
packages.
Absolute Maximum Ratings
Supply Voltage (ICC<30mA).........................................................................Self Limiting
Supply Voltage (Low Impedance Source) .................................................................30V
Output Current..............................................................................................................±1A
Output Energy (Capacitive Load) ................................................................................5µJ
Analog Inputs (VFB, Sense) ...........................................................................-0.3V to 5.5V
Error Amp Output Sink Current .............................................................................10mA
Lead Temperature Soldering
Wave Solder (through hole styles only) ..........10 sec. max, 260°C peak
Reflow (SMD styles only) ...........60 sec. max above 183°C, 230°C peak
V CC
V CC Pwr
Undervoltage
Lock-out Circuit
Set/
5V
Reset Reference
Gnd
V REF
16V/10V
(8.4V/7.6V)
Internal
Bias
2.50V
OSC
COMP
–
Error
Amplifier
1
8
VREF
VFB
2
7
VCC
Sense
3
6
VOUT
OSC
4
5
Gnd
COMP 1
14
VREF
NC 2
13
NC
VFB 3
12
VCC
NC
4
11
VCC Pwr
5
10
VOUT
NC 6
9
Pwr Gnd
OSC 7
8
Gnd
NOR
V OUT
V FB
COMP
14 Lead SO Narrow
Output
Enable
Oscillator
S
2 R
+
Package Options
8 Lead PDIP & SO Narrow
Block Diagram
34V
■ Optimized for Off-line
Control
■ Internally Trimmed
Temperature
Compensated Oscillator
■ Maximum Duty-cycle
Clamp
■ VREF stabilized before
Output Stage is Enabled
■ Low Start-up Current
■ Pulse-by-pulse Current
Limiting
■ Improved Undervoltage
Lockout
■ Double Pulse Suppression
■ 1% Trimmed Bandgap
Reference
■ High Current Totem Pole
Output
R
VC
R
1 V
PWM
Latch
Pwr Gnd
Current
Sensing
Comparator
Sense
( ) Indicates CS-2843A/3843A
Sense
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
Rev. 10/23/98
1
A
®
Company
CS2842A/3843A SERIES
CS2842A/CS3842A
CS2843A/CS3843A
CS2842A/3843A SERIES
Electrical Characteristics: -25° ≤ TA ≤ 85˚C for CS2842A/2843A, 0° ≤ TA ≤ 70˚C for CS3842A/3843A. VCC = 15V (Note 1);
RT = 680Ω, CT = .022µF for triangular mode, RT = 10kΩ, CT = 3.3nF for sawtooth mode (see Figure 3), unless otherwise stated.
PARAMETER
TEST CONDITIONS
CS2842A/CS2843A
MIN TYP MAX
CS3842A/CS3843A
MIN TYP MAX UNITS
4.95
4.90
■ Reference Section
Output Voltage
TJ = 25˚C, IOUT = 1mA
5.00
5.05
Line Regulation
5.00
5.10 V
12 ≤ VIN ≤ 25V
6
20
6
20
mV
Load Regulation
1 ≤ IOUT ≤ 20mA
Temperature Stability
(Note 2)
6
25
6
25
mV
0.2
0.4
0.2
0.4
mV/˚C
Total Output Variation
Line, Load, Temp. (Note 2)
4.90
5.10
Output Noise Voltage
10Hz ≤ f ≤ 10kHz, TJ = 25˚C (Note 2)
50
Long Term Stability
TA = 125˚C, 1kHrs. (Note 2)
5
25
Output Short Circuit
TA = 25˚C
-100
-180
-30
4.82
5.18 V
50
µV
5
25
mV
-30
-100
-180 mA
47
44
52
52
57
60
kHz
kHz
0.2
1.0
%
■ Oscillator Section
Initial Accuracy
Sawtooth Mode (see Fig. 3), TJ = 25˚C 47
Triangular Mode (see Fig. 3), TJ = 25˚C 47
52
52
57
57
Voltage Stability
12 ≤ VCC ≤ 25V
0.2
1.0
Temp. Stability
Sawtooth Mode TMIN ≤ TA ≤ TMAX
(Note 2)
Triangular Mode TMIN ≤ TA ≤ TMAX
(Note 2)
Amplitude
OSC peak to peak
Discharge Current
TJ = 25˚C
TMIN ≤ TA ≤ TMAX
7.5
7.2
Input Voltage
VCOMP = 2.5V
2.45
Input Bias Current
VFB = 0
AVOL
2 ≤ VOUT ≤ 4V
5
5
%
8
8
%
1.7
1.7
V
8.3
9.3
9.5
7.5
7.2
2.50
2.55
2.42
-0.3
-1.0
8.3
9.3
9.5
mA
mA
■ Error Amp Section
65
90
65
2.50
2.58 V
-0.3
-2.0
90
µA
dB
Unity Gain Bandwidth
(Note 2)
0.7
1.0
0.7
1.0
MHz
PSRR
12 ≤ VCC ≤ 25V
60
70
60
70
dB
Output Sink Current
VFB = 2.7V, VCOMP = 1.1V
2
6
2
6
mA
Output Source Current
VFB = 2.3V, VCOMP = 5V
-0.5
-0.8
-0.5
-0.8
mA
VOUT High
VFB = 2.3V, RL = 15kΩ to ground
5
6
5
6
V
VOUT Low
VFB = 2.7V, RL = 15kΩ to VREF
0.7
1.1
0.7
1.1
V
■ Current Sense Section
Gain
(Notes 3 & 4)
2.85
3.00
3.15
2.85
3.00
3.15 V/V
Maximum Input Signal
VCOMP = 5V (Note 3)
0.9
1.0
1.1
0.9
1.0
1.1
70
V
PSRR
12 ≤ VCC ≤ 25V (Note 3)
70
Input Bias Current
VSense = 0
-2
-10
-2
-10
dB
µA
Delay to Output
TJ = 25˚C (Note 2)
150
300
150
300
ns
Output Low Level
ISINK = 20mA
ISINK = 200mA
0.1
1.5
0.4
2.2
0.1
1.5
0.4
2.2
V
V
Output High Level
ISOURCE = 20mA
ISOURCE = 200mA
■ Output Section
13.0
12.0
2
13.5
13.5
13.0
12.0
13.5
13.5
V
V
PARAMETER
CS2842A/CS2843A
MIN TYP MAX
TEST CONDITIONS
CS3842A/CS3843A
MIN TYP MAX UNITS
■ Output Section: continued
Rise Time
TJ = 25˚C, CL = 1nF (Note 2)
50
150
50
150
ns
Fall Time
TJ = 25˚C, CL = 1nF (Note 2)
50
150
50
150
ns
Output Leakage
UVLO Active, VOUT = 0
-0.01
-10.00
-0.01 -10.00 µA
0.5
1.0
Operating Supply Current
VFB = VSense = 0V, RT = 10kΩ, CT = 3.3nF 11
17
VCC Zener Voltage
ICC = 25mA
34
■ Total Standby Current
Start-Up Current
PARAMETER
TEST CONDITIONS
MIN
CS2842A
TYP MAX
MIN
11
0.5
1.0
17
mA
34
CS3842A
TYP MAX
mA
V
CS2843A/CS3843A
MIN TYP MAX UNITS
■ Under-Voltage Lockout Section
Start Threshold
Min. Operating
Voltage
Notes:
After Turn On
15
16
17
14.5
16.0 17.5
7.8
8.4
9.0
V
9
10
11
8.5
10.0 11.5
7.0
7.6
8.2
V
1. Adjust VCC above the start threshold before setting at 15V.
3. Parameter measured at trip point of latch with VFB=0.
2.These parameters, although guaranteed, are not 100% tested in production.
4. Gain defined as:
A=
∆VCOMP
∆VSense
; 0 ≤ VSense ≤ 0.8V.
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
8L PDIP/SO
14L SO Narrow
1
1
COMP
2
3
VFB
3
5
Sense
Noninverting input to Current Sense Comparator
4
7
OSC
Oscillator timing network with Capacitor to Ground, resistor
to VREF
5
8
Gnd
Ground
9
Pwr Gnd
10
VOUT
11
VCCPwr
7
12
VCC
Positive power supply
8
14
VREF
Output of 5V internal reference
2,4,6,13
NC
No Connection
6
Error amp output, used to compensate error amplifier
Error amp inverting input
Output driver Ground
Output drive pin
Output driver positive supply
3
CS2842A/3843A SERIES
Electrical Characteristics: continued
Oscillator Duty Cycle vs RT
Oscillator Frequency vs CT
100
900
90
800
RT =680Ω
80
DUTY CYCLE (%)
700
FREQ. (kHz)
CS2842A/3843A SERIES
Typical Performance Characteristics
600
500
RT =1.5kΩ
400
70
60
50
40
300
30
200
20
RT =10kΩ
100
.0005
10
.001
.002
.003
.005
.01
.02
.03 .04 .05
100
200
300 400 500 700
CT (µF)
1k
2k
3k 4k 5k
7k
10k
RT (Ω)
Test Circuit
V REF
RT
2N2222
V CC
A
100kΩ
COMP
4.7kΩ
1kΩ
ERROR AMP
ADJUST
4.7kΩ
V REF
V FB
0.1µF
V CC
0.1µF
5kΩ
V OUT
V OUT
Sense
Sense
ADJUST
1kΩ
1W
OSC
Gnd
Gnd
CT
Circuit Description
Undervoltage Lockout
V CC
During Undervoltage Lockout (Figure 1), the output driver is biased to a high impedance state. The output should
be shunted to ground with a resistor to prevent output
leakage current from activating the power switch.
ON/OFF Command
to reset of IC
CSX842A CSX843A
V ON
V OFF
16V
10V
8.4V
7.6V
PWM Waveform
To generate the PWM waveform, the control voltage from
the error amplifier is compared to a current sense signal
which represents the peak output inductor current (Figure
2). An increase in VCC causes the inductor current slope to
increase, thus reducing the duty cycle. This is an inherent
feed-forward characteristic of current mode control, since
the control voltage does not have to change during
changes of input supply voltage.
When the power supply sees a sudden large output current increase, the control voltage will increase allowing the
duty cycle to momentarily increase. Since the duty cycle
tends to exceed the maximum allowed to prevent trans-
I CC
<15mA
<1mA
V CC
V ON
V OFF
Figure 1: Typical Undervoltage Characteristics
4
former saturation in some power supplies, the internal
oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of oscillator components.
VOSC
OSC
RESET
Setting the Oscillator
Oscillator timing capacitor, CT, is charged by VREF through
RT and discharged by an internal current source. During
the discharge time, the internal clock signal blanks out the
output to the Low state, thus providing a user selected
maximum duty cycle clamp. Charge and discharge times
are determined by the formula:
EA Output
Switch
Current
VCC
IOUT
t c = RTCT ln
VOUT
t d = RTCT ln
Figure 2: Timing Diagram for key CS2841B parameters
(
(
VREF - Vlower
VREF - Vupper
)
VREF - IdRT - Vlower
VREF - IdRT - Vupper
)
Substituting in typical values for the parameters in the
above formulas:
VREF = 5.0V, Vupper = 2.7V, Vlower = 1.0V, Id = 8.3mA
tc ≈ 0.5534RTCT
V REF
RT
OSC
CT
td = RTCT ln
Gnd
(
2.3 - 0.0083 RT
4.0 - 0.0083 RT
)
The frequency and maximum duty cycle can be determined using the Typical Performance Characteristic
graphs.
Timing parameters
Vupper
Grounding
Vlower
tc
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass
capacitors should be connected close to Gnd pin in a single point ground.
The transistor and 5kΩ potentiometer, shown in the test
circuit, are used to sample the oscillator waveform and
apply an adjustable ramp to Sense.
td
Sawtooth Mode
LARGE RT (≈10kΩ)
VOSC
Internal Clock
Triangular Mode
SMALL RT (≈700kΩ)
VREF
Internal Clock
Figure 3: Oscillator Timing Network and parameters
5
CS2842A/3843A SERIES
Circuit Description: continued
CS2842A/3843A SERIES
Package Specification
PACKAGE THERMAL DATA
PACKAGE DIMENSIONS IN mm (INCHES)
Thermal Data
D
Lead Count
Metric
Max
Min
10.16
9.02
5.00
4.80
8.75
8.55
8 Lead PDIP
8 Lead SO Narrow
14 Lead SO Narrow
English
Max Min
.400 .355
.197 .189
.344 .337
RΘJC
RΘJA
Plastic DIP (N); 300 mil wide
typ
typ
8L
PDIP
52
100
Surface Mount Narrow Body (D); 150 mil wide
7.11 (.280)
6.10 (.240)
1.77 (.070)
1.14 (.045)
8.26 (.325)
7.62 (.300)
8L
14 L
SO Narrow SO Narrow
45
30
˚C/W
165
125
˚C/W
4.00 (.157)
3.80 (.150)
6.20 (.244)
5.80 (.228)
0.51 (.020)
0.33 (.013)
1.27 (.050) BSC
2.54 (.100) BSC
3.68 (.145)
2.92 (.115)
1.75 (.069) MAX
0.39 (.015)
MIN.
.356 (.014)
.203 (.008)
.558 (.022)
.356 (.014)
REF: JEDEC MS-001
D
1.57 (.062)
1.37 (.054)
Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
All specs are the same.
1.27 (.050)
0.40 (.016)
0.25 (.010)
0.19 (.008)
D
0.25 (0.10)
0.10 (.004)
REF: JEDEC MS-012
Ordering Information
Part Number
0˚C to
70˚C
CS2842ALN8
CS2843ALN8
CS3842AGN8
CS3842AGD8
CS3842AGDR8
•
•
•
CS3842AGD14
CS3842AGDR14
•
•
CS2843ALD14
CS2843ALDR14
CS3843AGN8
CS3843AGD8
CS3843AGDR8
•
•
•
CS3843AGD14
CS3843AGDR14
•
•
Rev. 10/23/98
-25˚C to
Description
85˚C
•
8L PDIP
•
8L PDIP
8L PDIP
8L SO Narrow
8L SO Narrow
(tape & reel)
14L SO Narrow
14L SO Narrow
(tape & reel)
•
14L SO Narrow
•
14L SO Narrow
(tape & reel)
8L PDIP
8L SO Narrow
8L SO Narrow
(tape & reel)
14L SO Narrow
14L SO Narrow
(tape & reel)
Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.
6
© 1999 Cherry Semiconductor Corporation