CHERRY CS5127GDW16

CS5127
CS5127
Dual Output Nonsynchronous Buck Controller
with Sync Function and Second Channel Enable
Features
Description
circuits. The first lockout releases
when VIN reaches 8.4V, while the
second lockout ensures that VREF is
higher than 3.6V. The outputs are
held in a low state until both lockouts have released. The controller is
configured to utilize the V2ª control method to achieve the fastest
possible transient response and
best overall regulation. This dual
controller is a cost-effective solution for providing VCORE and VIO
power solutions in computing
applications using a single controller. The CS5127 will operate
over an input voltage range of 9.4V
to 20V and is available in a 16 lead
wide body surface mount package.
The CS5127 is a fixed frequency
dual output nonsynchronous buck
controller. It contains circuitry for
regulating two separate outputs.
Each output channel contains a
high gain error amplifier, a comparator and latch, and a totem-pole
output driver capable of providing
DC current of 100mA and peak current in excess of 0.5A. A common
oscillator controls switching for
both channels, and a sync lead is
provided to allow parallel supply
operation or shifting of the switching noise spectrum. An on-chip 5V
reference is capable of providing as
much as 10mA of current for external circuitry. The CS5127 also
contains two undervoltage lockout
Applications Diagram
■ Nonsynchronous Buck
Design
■ V2ª Control Topology
■ 100ns Transient Loop
Response
■ Programmable Oscillator
Frequency
■ 30ns Typical Gate Rise
and 10ns Fall Times
(No Load)
■ Frequency
Synchronization Input
■ ENABLE Input Controls
Channel 2 Gate Driver
■ 5V/10mA Reference
Output
Package Option
12V, 5V to 2.8V @ 7A and 3.3V @ 7A for 233MHz Pentium¨ Processor with MMXª Technology
+
C3 +
1mF
C1, C2
2 x 680mF
16 Lead SOIC Wide
+5V
12V
5V
C4, C5
2 x 680mF
SYNC
+
Q1
FMMT2222ACT
CT
C6
0.1mF
C7
330pF
VFB1
R2
27k
COMP1
Q2
IRL3103S
L1
+
R4
1540
CS5127
RT
2.8V
5mH
C10, C11
2 x 680mF
D1
1N5821
+ C8
1mF
VFB2
GATE1
GATE2
20k
VFB2
COMP1
Q3
IRL3103S
L2
3.3V
5mH
C12, C13
2 x 680mF
PGnd
D2
1N5821
R6
1k
C14
330pF
ENABLE
VFB1
COMP2
VFFB2
LGnd
C9
0.1mF
ENABLE
VFFB1
VREF
RT
VIN
VREF
R5
1270
R10
VIN
CT
SYNC
R1
20k
1
+
R9
2k
R7
2400
R3
18k
R8
1500
COMP2
VFFB1
VFFB2
GATE1
GATE2
LGND
PGND
R11
C15
100mF
C16
100mF
C17
330pF
20k
V2 is a trademark of Switch Power, Inc.
Pentium is a registered trademark and MMX is a trademark of Intel Corporation
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
Rev. 11/3/98
1
A
¨
Company
CS5127
Absolute Maximum Ratings
Operating Junction Temperature, TJ ..................................................................................................................................... 150¡C
Storage Temperature Range, TS ...................................................................................................................................-65 to 150¡C
ESD (Human Body Model).........................................................................................................................................................2kV
Lead Temperature Soldering: Reflow (SMD styles only).............................................60 sec. max above 183¡C, 230¡C peak
Lead Symbol
VMAX
Lead Name
VMIN
ISOURCE
ISINK
SYNC
Oscillator Synchronization Input
5.5V
-0.3V
5 mA
5 mA
CT
Oscillator Integrating Capacitor
5.5V
-0.3V
1mA
1mA
RT
Oscillator Charge Current Resistor
5.5V
-0.3V
1mA
1mA
VFB1, VFB2
Voltage Feedback Inputs
5.5V
-0.3V
N/A
N/A
COMP1, COMP2
Error Amplifier Outputs
7.5V
-0.3V
2mA
50mA
VFFB1, VFFB2
PWM Ramp Inputs
5.5V
-0.3V
1mA
1mA
GATE1, GATE2
FET Gate Drive Outputs
20V
-0.3V DC,
-2.0V for
t < 50ns
200mA DC,
1A peak
(t < 100µs)
200mA DC,
1A peak
(t < 100µs)
LGnd
Reference Ground and IC Substrate
0V
0V
25 mA
N/A
PGnd
Power Ground
0V
0V
1A Peak,
200mA DC
N/A
ENABLE
Channel 2 Enable
5.5V
-0.3V
1mA
N/A
VREF
Reference Voltage Output
5.5V
-0.3V
150mA
(short circuit)
5mA
VIN
Power Supply Input
20V
-0.3V
N/A
200mA DC,
1A peak
(t < 100µs)
Electrical Characteristics: 0¡C < TA < 70¡C; 0¡C < TJ < 125¡C; 9.4V < VIN < 20V; CT = 330 pF; RT = 27k½;
unless otherwise stated.
PARAMETER
■ Reference Section
VREF Output Voltage
Line Regulation
Load Regulation
VREF Variation over Line, Load
and Temperature
Output Short Circuit Current
■ Oscillator Section
Oscillator Frequency Variation
over Line and Temperature
Maximum Duty Cycle
Sync Threshold
Sync Bias Current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Room Temperature,
IVREF = 1mA, VIN = 12V
4.9
5.0
5.1
V
1
15
20
26
5.15
mV
mV
V
30
100
150
mA
175
210
245
kHz
80
0.8
90
1.6
170
430
230
98
2.4
250
750
%
V
µA
1 mA < IVREF < 10 mA
4.85
VSYNC = 2.4V
VSYNC = 5.0V
Sync Propagation Delay
2
ns
CS5127
Electrical Characteristics: 0¡C < TA < 70¡C; 0¡C < TJ < 125¡C; 9.4V < VIN < 20V; CT = 330 pF; RT = 27k½;
unless otherwise stated.
PARAMETER
■ Error Amplifiers
VFB Reference Voltage
Input Bias Current
Open Loop Gain
Unity Gain Bandwidth
PSRR
COMP Source Current
COMP Sink Current
COMP Output Low Voltage
■ PWM Comparators
VFFB Bias Current
Propagation Delay
Common Mode
Maximum Input Voltage
■ ENABLE Lead
ENABLE High Threshold
ENABLE Bias Current
■ Gate Driver Outputs
Output Low Saturation Voltage
Output High Saturation Voltage
Output Voltage under Lockout
Output Rise Time
Output Fall Time
TEST CONDITIONS
VCOMP = VVFB
VFB = 1.275V
f = 120Hz
VCOMP = 3V, VVFB = 1.1V
VCOMP = 1.2V, VVFB = 1.45V
VVFB = 1.45V, ICOMP = 0.3 mA
TYP
MAX
UNIT
1.245
1.300
1.0
0.9
10
0.50
1.275
0.1
85
1.0
80
1.3
16
0.85
V
µA
dB
MHz
dB
mA
mA
V
20
250
2.9
2.0
100
3.3
VFFB = 0
VFFB rising to VGATE falling
channel 2 enabled
VENABLE = 0
3
µA
ns
V
1.5
2.5
3.5
V
250
400
µA
0.1
0.25
1.5
1.6
0.1
30
10
0.4
2.50
2.0
3.0
0.2
V
V
V
V
V
ns
ns
8.4
7.8
9.4
8.8
V
V
0.4
17.5
0.8
25
mA
mA
7.4
6.8
VIN = 6V
VCT = 0V, no load
2.0
24
1.00
100
IGATE = 20 mA
IGATE = 100 mA
IGATE = 20 mA
IGATE = 100 mA
VIN = 6V, IGATE = 1 mA
no load
no load
■ Undervoltage Lockout
Turn On Threshold
Turn Off Threshold
■ Supply Current
Start Up Current
Operating Current
MIN
CS5127
Package Lead Description
PACKAGE LEAD #
LEAD SYMBOL
FUNCTION
16 Lead SO Wide
1
SYNC
A pulse train on this lead will synchronize the oscillator. Sync threshold level
is 2.4V. Synchronization frequency should be at least 10% higher than the regular operating frequency. The sync feature is level sensitive.
2
CT
The oscillator integrating capacitor is connected to this lead.
3
RT
The oscillator charge current setting resistor is connected to this lead.
4
VFB1
5
COMP1
6
VFFB1
This lead connects to the non-inverting input of the channel 1 PWM comparator.
7
GATE1
This lead is the gate driver for the channel 1 FET. It is capable of providing
nearly 1A of peak current.
8
LGND
This lead provides a ÒquietÓ ground for low power circuitry in the IC. This
lead should be shorted to the PGND lead as close as possible to the IC for best
operating results.
9
PGND
This lead is the power ground. It provides the return path for the FET gate discharge. It should be shorted to the LGND lead as close as possible to the IC for
best operating results.
10
GATE2
This lead is the gate driver for the channel 2 FET. See GATE1 lead description
for more details.
11
VFFB2
This lead connects to the non-inverting input of the channel 2 PWM comparator.
12
COMP2
13
VFB2
14
ENABLE
The regulator controlled by channel 2 may be turned on and off selectively by
the user. Pulling the ENABLE lead above 3.5V will turn channel 2 on. Setting
the ENABLE lead voltage below 1.5V guarantees that channel 2 is off.
15
VREF
This lead is the output of a ± 3% reference. This reference drives most of the
on-chip circuitry, but will provide a minimum of 10 mA to external circuitry if
needed. The reference is inherently stable and does not require a compensation capacitor, but use of a decoupling capacitor will reduce noise in the IC.
16
VIN
This lead is the power supply input to the IC. The maximum input voltage
that can be withstood without damage to the IC is 20V.
The inverting input of the channel 1 error amplifier is brought out to this lead.
The lead is connected to a resistor divider which provides a measure of the
output voltage. The input is compared to a 1.275V reference, and channel 1
error amp output is used as the V2ª PWM control voltage.
Channel 1 error amp output and PWM comparator input.
Channel 2 error amp output and PWM comparator input.
Inverting input for the channel 2 error amp. See VFBI for more details.
4
CS5127
Block Diagram
COMP1
VFFB1
+
PWM
Comparator
-
VFB1
Error
Amplifier
-
Channel 2
Gate Driver
+
1.275V
GATE1
VREF
VIN
Undervoltage
Lockout
VIN
Bandgap
Voltage
Reference
Reference
Undervoltage
Lockout
LGND
PGND
SYNC
RT
Oscillator
CT
1.275V
VFB2
Channel 2
Gate Driver
+
Error
Amplifier
-
GATE2
PWM
Comparator
-
+
COMP2
VFFB2
ENABLE
Theory of Operation
The CS5127 is a dual power supply controller that utilizes
the V2ª control method. Two nonsynchronous V2ª buck
regulators can be built using a single controller IC. This IC
is a perfect choice for efficiently and economically providing core power and I/O power for the latest
high-performance CPUs. Both switching regulators
employ a fixed frequency architecture driven from a
common oscillator circuit.
The V2ª control method is illustrated in Figure 1. Both
the ramp signal and the error signal are generated by the
output voltage. Since the ramp voltage is defined as the
output voltage, the ramp signal is affected by any change
in the output, regardless of the origin of that change. The
ramp signal also contains the DC portion of the output
voltage, allowing the control circuit to drive the output
switch from 0% to about 90% duty cycle.
Changes in line voltage will change the current ramp in
the inductor, affecting the ramp signal and causing the
V2ª control loop to adjust the duty cycle. Since a change
in inductor current changes the ramp signal, the V2ª
method has the characteristics and advantages of current
mode control for line transient response.
Changes in load current will affect the output voltage and
thus will also change the ramp signal. A load step will
immediately change the state of the comparator output
that controls the output switch. In this case, load transient
response time is limited by the comparator response time
and the transition speed of the switch. Notice that the reaction time of the V2ª loop to a load transient is not
dependent on the crossover frequency of the error signal
loop. Traditional voltage mode and current mode methods
are dependent on the compensation of the error signal
loop.
The V2ª error signal loop can have a low crossover frequency, since transient response is handled by the ramp
signal loop. The ÒslowÓ error signal loop provides DC
accuracy. Low frequency roll-off of the error amplifier
bandwidth will significantly improve noise immunity.
This also improves remote sensing of the output voltage,
since switching noise picked up in long feedback traces
can be effectively filtered.
V2ª line and load regulation are dramatically improved
because there are two separate control loops. A voltage
V2ª Control Method
The V2ª method of control uses a ramp signal generated
by the ESR of the output capacitors. This ramp is proportional to the AC current in the inductor and is offset by the
DC output voltage. V2ª inherently compensates for variation in both line and load conditions since the ramp signal
is generated from the output voltage. This differs from traditional methods such as voltage mode control, where an
artificial ramp signal must be generated, and current mode
control, where a ramp is generated from inductor current.
+
PWM
Comparator
GATE
Ramp Signal
-
COMP
Error
Amplifier
+
Error Signal
VFFB
VFB
Reference
Voltage
Figure 1: V2ª control diagram.
5
CS5127
Theory of Operation: continued
mode controller relies on a change in the error signal to
indicate a change in the line and/or load conditions. The
error signal change causes the error loop to respond with a
correction that is dependent on the gain of the error amplifier. A current mode controller has a constant error signal
during line transients, since the slope of the ramp signal
will change in this case. However, regulation of load transients still requires a change in the error signal. V2ª
control maintains a fixed error signal for both line and
load variation, since the ramp signal is affected by both.
CT Lead Waveform
If the sync pulse is longer
than the CT lead discharge
time, a short Òdead spotÓ
will exist during which the
output driver is off.
Sync Lead Waveform
Figure 2a: Sync pulse duration vs. CT lead discharge time.
Voltage Mode Control
The CS5127 can be operated in voltage mode if necessary.
For example, if very small values of output ripple voltage
are required, V2ª control may not operate correctly.
Details on how to choose the components for voltage
mode operation are provided in the section on VFFB component selection.
The best way to determine if the pulse width is sufficiently
short is to examine the CT lead waveform with an oscilloscope. If Òdead spotsÓ are observed in the CT lead waveform,
decreasing the SYNC pulse width should be considered.
Alternatively, the SYNC signal may be AC coupled through
a small capacitor. In this case, care must be taken to ensure
that current pulled out of the IC during the high-to-low transition of the SYNC signal is limited to less than 5mA.
Constant Frequency
As output line and load conditions change, the V2ª control loop modifies the switch duty cycle to regulate the
output voltage. The CS5127 uses a fixed frequency architecture. Both output channels are controlled from a
common oscillator. The CS5127 can typically provide a
maximum duty cycle of about 90%.
SYNC
20k
Oscillator
2200p
Sync Function
It is sometimes desirable to shift the switching noise spectrum to different frequencies. A pulse train applied to the
SYNC lead will terminate charging of the CT lead capacitor
and pull the CT lead voltage to ground for the duration of
the positive pulse level. This reduces the period of oscillation and increases the switching frequency.
Synchronization must always be done at a frequency
higher than the typical oscillator frequency. Using a lower
frequency will lead to erratic operation and poor regulation. The SYNC pulse train frequency should be at least 10
% higher than the unsynchronized oscillator frequency.
Synchronizing the oscillator will also decrease the maximum duty cycle. If the nominal oscillator frequency is
200kHz, increasing the oscillator frequency by 10% (to
220kHz) will decrease the maximum duty cycle from a
typical of 90% to about 89%. Increasing the frequency by
25% (to 250kHz) will change the maximum duty cycle to
about 87%. A 50% increase (to 300kHz) gives a maximum
duty cycle of about 85%. The width of the SYNC pulse
should be slightly shorter than the duration of the falling
edge of the CT lead waveform (see Figure 2a) so the SYNC
pulse doesnÕt interfere with the oscillator function.
Figure 2b: Capacitive coupling of the SYNC signal. The external diode
is used to clamp the IC substrate diode if ISYNC is greater than 5mA
during the negative portion of the input waveform.
Overcurrent Protection
The CS5127 has no on-board current limit circuitry. An
example current limit circuit is provided in the Additional
Application Circuits section of this data sheet.
6
CS5127
Applications Information
variables the designer must consider. Inductance values
between 1µH and 50µH are suitable for use with the CS5127.
Low values within this range minimize the component size
and improve transient response, but larger values reduce
ripple current. Choosing the inductor value requires the
designer to make some choices early in the design. Output
current, output voltage and the input voltage range should
be known in order to make a good choice.
The input voltage range is bracketed by the maximum and
minimum expected values of VIN. Most computer applications use a fairly well-regulated supply with a typical
output voltage tolerance on the order of ±5%. The values
of VIN(MAX) and VIN(MIN) are used to calculate peak current
and minimum inductance value, respectively. However, if
the supply is well-regulated, these calculations may both
be made using the typical input voltage value with very
little error.
Current in the inductor while operating in the continuous
current mode (CCM) is defined as the load current plus
the inductor ripple current:
Selection of Feedback Lead Divider Resistor Values
The feedback (VFB) leads are connected to external resistor
dividers to set the output voltage. The on-chip error amplifier is referenced to 1.275V, and the resistor divider values
are determined by selecting the desired output voltage
and the value of the divider resistor connected between
the VFB lead and ground.
Resistor R1 is chosen first based on a design trade-off of
system efficiency vs. output voltage accuracy. Low values
of divider resistance consume more current which decreases system efficiency. However, the VFB lead has a 1µA
maximum bias current which can introduce errors in the
output voltage if large resistance values are used. The
approximate value of current sinking through the resistor
divider is given by
1.275V
IV(FB) =
R1
The output voltage error that can be expected due to the
bias current is given by
(1E - 6) ´ R1
Error Percentage =
´ 100%
1.275
IL = IOUT + IRIPPLE
The ripple current waveform is triangular, and the current
is a function of the voltage across the inductor, the switch
on-time and the inductor value. Switch on-time is the duty
cycle divided by the operating frequency, and duty cycle
can be defined as the ratio of VOUT to VIN, such that
where R1 is given in ohms. For example, setting R1 = 5K
yields an output voltage error of 0.39% while setting the
feedback divider current at 255µA. Larger currents will
result in reduced error.
IRIPPLE =
Output
Driver
The peak current can be described as the load current plus
half of the ripple current. Peak current must be less than
the maximum rated switch current. This limits the maximum load current that can be provided. It is also
important that the inductor can deliver the peak current
without saturating.
VOUT
+
1.275V
-
R2
VFB
IOUT(MAX) = ISWITCH(MAX) -
R1
GATE
COMP
R2 can be sized according to the following formula once
the desired output voltage and the value of R1 have been
determined:
(
(VIN(MAX) - VOUT)VOUT
2f ´ L ´ VIN(MAX)
Since the peak inductor current must be less than or equal
to the peak switch current, the minimum value of inductance can be calculated:
Figure 3: Feedback resistor divider.
R2 = R1
(VIN - VOUT)VOUT
f ´ L ´ VIN
VOUT
-1
1.275
LMIN =
)
(VIN(MIN) - VOUT)VOUT
f ´ VIN(MIN) ´ ISWITCH(MAX)
Load Current Transient Response
The theoretical limit on load current transient response is a
function of the inductor value, the load transient and the
voltage across the inductor. In conventionally-controlled
regulators, the actual limit is the time required by the control loop. Conventional current-mode and voltage-mode
control loops adjust the switch duty cycle over many oscillator periods, often requiring tens or even hundreds of
Selecting the Inductor
There are many factors to consider when choosing the
inductor. Maximum load current, core losses, winding
losses, output voltage ripple, short circuit current, saturation, component height, EMI/EMC and cost are all
7
CS5127
Applications Information: continued
microseconds to return to a steady-state. V2ª control uses
the ripple voltage from the output capacitor and a ÒfastÓ
control loop to respond to load transients, with the result
that the transient response of the CS5127 is very close to
the theoretical limit. Response times are defined below.
tRESPONSE(INCREASING) =
Selecting the Output Capacitor
Output capacitors are chosen primarily on the value of
equivalent series resistance, because this is what determines how much output ripple voltage will be present.
Most polarized capacitors appear resistive at the typical
oscillator frequencies of the CS5127. As a rule of thumb,
physically larger capacitors have lower ESR. The capacitorÕs value in µF is not of great importance, and values
from a few tens of µF to several hundreds of µF will work
well. Tantalum capacitors serve very well as output capacitors, despite their bad reputation for spectacular failure
due to excessive inrush current. This is not usually an issue
for output capacitors, because the failure is not associated
with discharge surges. Ripple current in the output capacitor is usually small enough that the ripple current rating is
not an issue. The ripple current waveform is triangular,
and the formula to calculate the ripple current value is:
L(ÆIOUT)
(VIN - VOUT) ´ 0.85
tRESPONSE(DECREASING) =
L(ÆIOUT)
VOUT
Note that the response time to a load decrease is limited
only by the inductor value.
Other Inductor Selection Concerns
IRIPPLE =
Inductor current rating is an important consideration. If
the regulated output is subject to short circuit or overcurrent conditions, the inductor must be sized to handle the
fault without damage. Sizing the inductor to handle fault
conditions within the maximum DC current rating helps to
ensure the coil doesnÕt overheat. Not only does this prevent damage to the inductor, but it reduces unwanted heat
generated by the system and makes thermal management
easier.
Selecting an open core inductor will minimize cost, but
EMI/EMC performance may be degraded. This is a tough
choice, since there are no guidelines to ensure these components will not prove troublesome.
Core materials influence the saturation current and saturation characteristics of the inductor. For example, a slightly
undersized inductor with a powdered iron core may provide satisfactory operation because powdered iron cores
have a ÒsoftÓ saturation curve compared to other core
materials.
Small physical size, low core losses and high temperature
operation will also increase cost. Finally, consider whether
an alternate supplier is an important consideration. All of
these factors can increase the cost of the inductor.
and output ripple voltage due to inductor ripple current is
given by:
VRIPPLE(ESR) =
(VIN - VOUT) ´ VOUT ´ ESR
f ´ L ´ VIN
A load step will produce an instantaneous change in
output voltage defined by the magnitude of the load step,
capacitor ESR and ESL.
DI
DVO = (DIO ´ ESD) + DT ESL
A good practice is to first choose the output capacitor to
accommodate voltage transient requirements and then to
choose the inductor value to provide an adequate ripple
voltage.
Increasing a capacitorÕs value typically reduces its ESR, but
there is a limit to how much improvement can be had. In
most applications, placing several smaller capacitors in
parallel will result in acceptable ESR while maintaining a
small PC board footprint. A warning is necessary at this
point. The V2ª topology relies on the presence of some
amount of output ripple voltage being present to provide
the input signal for the ÒfastÓ control loop, and it is important that some ripple voltage be present at the lightest load
condition in normal operation to avoid subharmonic oscillation. Externally generated slope compensation can be
added to ensure proper operation.
Operating in Discontinuous Current Mode
For light load designs, the CS5127 will operate in discontinuous current mode (DCM). In this regime, external
components can be smaller, since high power dissipation is
not an issue. In discontinuous mode, maximum output
current is defined as:
IOUT(MAX) =
(VIN - VOUT)VOUT
f ´ L ´ VIN
(IPK)2 f ´ L(VIN)
2VOUT ´ (VIN(MAX) - VOUT)
Selecting the VFFB Lead Components
where IPK is the maximum current allowed in the switch
FET.
The VFFB lead is tied to the PWM comparatorÕs non-inverting input, and provides the connection for the
externally-generated artificial ramp signal that is required
whenever duty cycle is greater than 50%.
8
CS5127
Applications Information: continued
The DC voltage for the VFFB pin is usually provided from
the output voltage through an RC filter if VOUT is less than
3V. If VOUT is greater than 2.9V, a resistor divider from
VOUT is recommended for proper circuit bias due to the
common mode input range limitations of the PWM comparator. In most cases, the FB pin resistor divider can be
used for this purpose with very little error, but a separate
divider is recommended if high accuracy is required. The
filter network is typically composed of a 1K resistor (RFFB)
and a 330 pF capacitor (CFFB). This filter gives a 330 ns
time constant which is sufficient to remove switching
noise from the DC voltage. Note that in cases where a
resistor divider provides the ramp signal, the resistor
between VOUT and the VFFB pin serves as RFFB. An artificial
ramp signal is generated using an NPN transistor (Q1), a
small coupling capacitor (CC) and a second resistor (RR).
The NPN transistor collector is connected either to the
external 5V supply or to the ICÕs 5V on-chip reference. The
transistorÕs base is connected to the CT pin, and the ramp
on the CT pin is used to provide the artificial ramp. The
transistorÕs emitter is connected to the coupling capacitor.
The capacitor value should provide a low impedance at
the switching frequency. A 0.1 µF capacitor represents 6.4
ohms at 250 kHz. A resistor is placed in series between this
capacitor and the VFFB pin to set the amplitude of the ramp
signal.
if DC voltage is provided from the output, or
(RESR) (VOUT)(R1)
VRAMP = 2000 (L
OUT) (R1 + R2)
if DC voltage is provided from a resistor divider as in
figure 5.
where RESR is the equivalent series resistance in ohms of
the total output capacitance, VOUT is the output voltage in
volts and LOUT is the inductor value in Henries. The result
is VRAMP given in millivolts per oscillator period. This
value is the optimum amplitude for the artificial ramp.
Note that COMP pin voltage changes and output ripple
voltage must be added to the ramp amplitude for proper
operation.
Once the total ramp signal has been determined, the value
of the ramp resistor (RR) can be determined. The ramp
resistor and filter resistor RFFB create a resistor divider
between the output voltage and the artificial ramp voltage.
We can assume the output does not change, and that the
maximum input voltage to the divider is equal to the DC
output voltage plus the CT pin voltage swing of 2.1V. The
ramp amplitude on the filter capacitor is then the divider
output voltage:
GATE
VOUT
R2
VRAMP =
+
(2.1V) (RFFB)
(RR + RFFB)
VFB
CT
5V
Q1
CT
Rearranging, we have
VFFB
RR
CC
RE
RR = RFFB
RFFB
CFFB
R1
(
)
2.1V
-1
VRAMP
Selecting the Catch Diode
Figure 4: Artificial ramp components CC, CFFB, RR and RFFB must be
provided for each channel if duty cycle for that channel exceeds 50%. Q1
and RE are common to both channels. DC voltage is shown supplied to
VFFB through the VFB resistor divider.
The schottky ÒcatchÓ diode must be capable of handling
the peak inductor current and must withstand a reverse
voltage at least equal to the value of VIN. Since the catch
diode only conducts during switch off-time, the average
current through the catch diode is defined as:
The amount of artificial ramp is dependent on oscillator
frequency, output voltage, output capacitor equivalent
series resistance (ESR), and inductor value. It also assumes
very small voltage fluctuations on the COMP pin. If the
added ramp is too small, it will not be sufficient to prevent
subharmonic oscillation. If the ramp is too large, V2ª control will be defeated, and loop regulation will enter voltage
mode control. DC regulation will be adequate, but transient response will be degraded. However, this may be
desirable in cases where very low values of output ripple
voltage are desired.
The artificial ramp amplitude can be calculated as follows:
ICATCH = IOUT
(
VIN - VOUT
VIN
)
Minimizing the diode on-voltage will improve efficiency.
Selecting Oscillator Components RT and CT
The on-chip oscillator frequency is set by two external
components. RT sets the oscillator charge current. It is connected to a voltage reference approximately equal to 2.5V.
The current generated in this fashion charges the CT capacitor between threshold levels of 1.5V and 3.6V. CT
capacitor discharge is done by a saturating NPN, and the
(RESR) (VOUT)
VRAMP = 2000 (L
OUT)
9
CS5127
Applications Information: continued
should conduct all the ripple current. RMS ripple current
can be as large as half the load current, and can be calculated as:
discharge time is typically less than 10% of the charge
time. External components CT and RT allow the switching
frequency to be set by the user in the range between 10kHz
and 500kHz. CT can be chosen first based on size and cost
constraints. For proper operation over temperature, the
value of RT should be chosen within the range from 20k½
to 40k½. Any type of one-eighth watt resistor will be adequate. Larger values of RT will decrease the maximum
duty cycle slightly. This occurs because the sink current on
the CT lead has an exponential relationship to the charge
current. Higher charge currents will discharge the CT lead
capacitor more quickly than lower currents, and a shorter
discharge time will result in a higher maximum duty
cycle.
Once the oscillator frequency and a value of CT have been
selected, the necessary value of RT can be calculated as follows:
IRIPPLE(RMS) = IOUT
ÆV = IRIPPLE(RMS) ´ ESR
(fOSC)(CT)
The type of capacitor is also an important consideration.
Aluminum electrolytic capacitors are inexpensive, but they
typically have low ripple current ratings. Choosing larger
values of capacitance will increase the ripple current
rating, but physical size will increase as well. Size constraints may eliminate aluminum electrolytics fro
consideration. Aluminum electrolytics typically have
shorter operating life because the electrolyte evaporates
during operation. Tantalum electrolytic capacitors have
been associated with failure from inrush current, and manufacturers of these components recommended derating the
capacitor voltage by a ratio 2:1 in surge applications. Some
manufacturers have product lines specifically tested to
withstand high inrush current. AVX TPS capacitors are
one such product. Ceramic capacitors perform well, but
they are also large and fairly expensive.
where fOSC is the oscillator frequency in hertz, CT is given
in farads, and the value of RT is given in ohms. ESR effects
are negligible since the charge and discharge currents are
fairly small, and any type of capacitor is adequate for CT.
Selecting the Compensation Capacitor
As previously noted, the error amplifier does not contribute greatly to transient response, but it does influence
noise immunity. The fast feedback loop input is compared
against the COMP pin voltage. The DC bias to the VFFB pin
may be provided directly from the output voltage, or
through a resistor divider if output voltage is greater than
2.9V. The desired percentage value of DC accuracy translates directly to the VFFB pin, and the minimum COMP pin
capacitor value can be calculated:
CCOMP =
VIN2
Peak current requirement, load transients, ambient operating temperature and product reliability requirements all
play a role in choosing this component. Capacitor ESR and
the maximum load current step will determine the maximum transient variation of the supply voltage during
normal operation. The drop in the supply voltage due to
load transient response is given as:
1.88
RT =
VOUT(VIN - VOUT)
Startup
(16mA)(TOSC)
(VFFBDC Bias Voltage)(tolerance)
At startup, output switching does not occur until two
undervoltage lockouts release. The first lockout monitors
the VIN lead voltage. No internal IC activity occurs until
VIN lead voltage exceeds the VIN turn-on threshold. This
threshold is typically 8.4V. Once this condition is met, the
on-chip reference turns on. As the reference voltage begins
to rise, a second undervoltage lockout disables switching
until VREF lead voltage is about 3.5V. The GATE leads are
held in a low state until both lockouts are released.
As switching begins, the VFB lead voltage is lower than the
output voltage. This causes the error amplifier to source
current to the COMP lead capacitor. The COMP lead voltage will begin to rise. As the COMP lead voltage begins to
rise, it sets the threshold level at which the rising VFFB lead
voltage will trip the PWM comparator and terminate
switch conduction. This process results in a soft start interval. The DC bias voltage on VFFB will determine the final
COMP voltage after startup, and the soft start time can be
approximately calculated as:
If fOSC = 200kHz, VFFB DC bias voltage is 2.8V and tolerance is 0.1%, CCOMP = 28.6µF. This is the minimum value
of COMP pin capacitance that should be used. It is a good
practice to guard band the tolerance used in the calculation. Larger values of capacitance will improve noise
immunity, and a 100µF capacitor will work well in most
applications.
The type of capacitor is not critical, since the amplifier
output sink current of 16mA into a fairly large value or
wide range of ESR will typically result in a very small DC
output voltage error. The COMP pin capacitor also determines the length of the soft start interval.
Selecting the Input Bypass Capacitor
The input bypass capacitors minimize the ripple current in
the input supply, help to minimize EMI, and provide a
charge reservoir to improve transient response. The capacitor ripple current rating places the biggest constraint on
component selection. The input bypass capacitor network
TSOFT START =
10
VFFB ´ CCOMP
ICOMP(SOURCE)
CS5127
Applications Information: continued
where TSOFT START is given in seconds if CCOMP is given in
farads, ICOMP(SOURCE) in amperes, and VFFB in volts. Note
that a design trade off will be made in choosing the value
of the COMP lead capacitor. Larger values of capacitance
will result in better regulation and improved noise immunity, but the soft start interval will be longer and capacitor
price may increase.
VOUT
VIN
L
RL
C
CONTROL
LOGIC
RA
R
RC
RB
PWM
VFFB
VR
COMP
VCONTROL
R1
C2
R2
VFB
EA
C1
1.275V
Figure 6: Voltage mode control equivalent circuit with two pole, one
zero compensation network.
VIN is the switch supply voltage, R represents the load, RL
is the combined resistance of the FET RDS (on) and the
inductor DC resistance, L is the inductor value, C is the
output capacitance, RC is the output capacitor ESR, RA
and RB are the feedback resistors and VR is the peak to
peak amplitude of the artificial ramp signal at the VFFB
pin. C1, C2, R1 and R2 are the components of the compensation network. Based on the application circuit from page
1, values for the 2.8V output equivalent circuit are:
Figure 5: Measured performance of the CS5127 at start up.
CCOMP =100µF, ICOMP(SOURCE)=1.3mA, VFFB = 2.8V, TSOFTSTART = 0.22s.
Normal Operation
VIN =
R=
RL =
C=
RC =
RA =
RB =
L=
During normal operation, the gate driver switching duty
cycle will remain approximately constant as the V2ª control loop maintains the regulated output voltage under
steady state conditions. Changes in supply line or output
load conditions will result in changes in duty cycle to
maintain regulation.
Voltage Mode Control
Voltage Mode Operation
There are two methods by which a user can operate the
CS5127 in voltage mode. The first method is simple, but
the transient response is typically very poor. This method
uses the same components as V2ª operation, but by
increasing the amplitude of the artificial ramp signal, V2ª
control is defeated and the controller operates in voltage
mode. Calculate RR using the formula above and divide
the value obtained by 10. This should provide an adequately large artificial ramp signal and cause operation
under voltage mode control. There may be some dependence on board layout, and further optimization of the
value for RR may be done empirically if required.
5V
0.4½
0.02½
1320µF
0.025½
1540½
1270½
5µH
A resistor change is necessary to increase the artificial
ramp magnitude to VFFB1. Changing R10 from 20k to 2k
will give a peak to peak amplitude of about 2V. Thus, VR =
2V.
The transfer function from VCONTROL to VOUT is
VOUT
VCONTROL =
R ´ VIN ´ (sCRC + 1)
s2LC
(R + RC) + s[L + RLC(R + RC) + RCRC] + R + RC
1
VR
Voltage mode control may be refined by removing the
COMP pin capacitor and adding a two pole, one zero compensation network. Consider the system block diagram
shown in figure 6.
Using the component values provided, this reduces to
11
´
CS5127
Applications Information: continued
divider. This factor will further reduce the overall system
gain.
1 + s(3.3E-5)
s2(2.772E-9) + s(2.902E-5) + 0.42
By adding the two pole, one zero compensation network
shown in figure 6, we can maximize the DC gain and push
out the crossover frequency. The transfer function for the
compensation network is
The zero frequency due to the output capacitor ESR is
given as
1
= 4.8 kHz.
(2¹CRC)
VCONTROL
s C1(R1 + R2) + 1
=
-s C2 R1(s C1 R2 + 1)
VFB
The double pole frequency of the power output stage is
This can be rewritten in terms of pole and zero frequencies
and a gain constant A.
1
R + R1
=
= 1.95 kHz.
LC(R + RC)
(2¹)
VCONTROL
s/(2¹fZ + 1)
=
VFB
-A s ((s/2fP) + 1)
The ESR zero approximately cancels one of the poles, and
the total phase shift is limited to 90. Bode plots are provided below.
fZ =
where
fP =
20
1
and A = R1 C2
2¹ C1R2
Note that, due to the first s term in the denominator, a pole
is located at f = 0. This will provide the maximum DC
gain.
The optimum performance can be obtained by choosing fZ
equal to the output double pole frequency and setting fP to
approximately half of the switching frequency. Gain factors can be chosen somewhat arbitrarily.
0
Gain, (dB)
1
(2¹ C1 (R1 + R2))
-20
-40
-60.0
1
102
10
103
105
104
Values between
1E-6½F and 20E-6½F are practical. We then have a set of
equations that can be solved for component values:
107
106
Frequency (Hz)
Figure 7: Bode plot of gain response for VOUT/VCONTROL.
C1 R1 =
Phase, (degree)
90
0
1
2¹
[
1
fZ
-
1
fP
]
, C1 R2 =
1
2¹fP
, C2 =
A
R1
Since there are only three equations, we must arbitrarily
choose one of the components. One option is to set the
value of R1 fairly large. This provides a high impedance
path between the VFB pin and the COMP pin.
-90
For our design, we have fZ = the double pole frequency =
1.95 kHz and fP = fOSC/2 = 100kHz. LetÕs arbitrarily choose
R1 = 4.7K. Then we solve the first equation for C1 and
obtain C1 = 17nF. Use a standard value of 22 nF.
-180
-270.0
1
10
102
103
104
105
106
107
Frequency (Hz)
We next solve for R2. With C1 =22 nF, R2= 72½. Use a
standard value of 75½.
We can choose a gain factor from somewhere in the
middle of our range and solve for C2. If A = 10E-6½F, we
have
C2 = 2.1 nF. Use a standard value of 2.2 nF.
Figure 8: Bode plot of phase response for VOUT/VCONTROL.
This uncompensated system is stable, but the low gain will
result in poor DC accuracy, and the low cutoff frequency
will result in poor transient response. Note that we have
not yet included the gain factor from the feedback resistor
12
CS5127
Applications Information: continued
Now that we have the compensation components chosen,
we can put together a transfer function for the entire control loop. The transfer function is the product of the VOUT
to VCONTROL transfer function, the gain of the feedback
resistor divider and the negative inverse of the compensation loop transfer function. That is,
Entering the loop transfer function in a mathematics program or a spreadsheet and evaluating the performance
from resulting Bode plots may help to further optimize the
compensation network component values.
Compensation may be further optimized by using a two
poleÐtwo zero compensation network as shown below.
TLOOP = - (TVC-VO ´ TDIVIDER ´ TCOMPENSATION)
C2
or
[
R ´ VIN ´ (sCRC + 1)
s2LC
(R + RC) + s[L + RLC(R + RC) + RCRC] + R + RC
[ ][
´
R3
C1
TLOOP =
1
RB
´
VR
RA + RB
][
´
sC1 (R1 + R2)+ 1
sC2 R1 (sC1 R2 + 1)
]
C3
R1
R2
From VOUT
VFB
COMP
]
Figure 11: Two poleÐtwo zero compensation network.
The two zeros are placed close to the resonant frequency of
the LC output circuit. That is,
Bode plots for this transfer function are shown below.
1
2¹
100
1
2¹ C1 R2
Å
1
2¹ R3 C3
The two poles are placed near half the switching frequency, or
60
Gain, (dB)
LC
Å
20
fSW
2
-20
Å
1
2¹ C1 R1
Å
1
2¹ R3 C2
-60.0
Channel 2 ENABLE Feature
-100.0
1
10
102
103
104
105
106
107
The ENABLE lead controls operation of channel 2. Channel
2 operates normally if the ENABLE lead voltage is greater
than 3.5V. Setting the ENABLE lead voltage below 1.5V
will guarantee that channel 2 is disabled. In this case, the
GATE2 lead will be held low and no switching will occur.
This feature can be used to selectively power up or power
down circuitry that may not always need to be on. For
example, in a laptop computer, channel 1 could power the
microprocessor while channel 2 controlled the disk drive.
Channel 2 could be turned off if the drive was not in use.
Frequency (Hz)
Figure 9: Bode plot of gain response for compensated voltage mode
system.
Phase, (degree)
90
0
-90
Thermal Management for Semiconductor Components
-180
-270.0
1
10
102
103
104
105
106
Semiconductor components will deteriorate in high temperature environments. It is necessary to limit the junction
temperature of control ICs, power MOSFETs and diodes in
order to maintain high levels of reliability. Most semiconductor devices have a maximum junction temperature of
125¡C, and manufacturers recommend operating their
products at lower temperatures if at all possible.
Power dissipation in a semiconductor device results in the
generation of heat in the pin junctions at the surface of the
107
Frequency (Hz)
Figure 10: Bode plot of phase response for compensated voltage mode
system.
13
CS5127
Applications Information: continued
IC. This heat is transferred to the surface of the IC package,
but a thermal gradient exists due to the thermal properties
of the package molding compound. The magnitude of this
thermal gradient is denoted in manufacturerÕs data sheets
as QJA , or junction-to-air thermal resistance. The on-chip
junction temperature can be calculated if QJA , the air temperature at the ICÕs surface and the on-chip power
dissipation are known:
TJ - TA
PD = Q + Q + Q
JC
CS
SA
where PD is on-chip power dissipation in watts, TJ is junction temperature in ¡C, TA is ambient temperature in¡C,
and thermal impedance QJC , QCS , and QSA are in¡C/W.
All these quantities can be calculated or obtained from data
sheets. The choice of a heatsink is based on the value of
QSA required such that the calculated power dissipation
does not cause junction temperature to exceed the manufacturerÕs maximum specification.
TJ = TA + (QJA ´ P)
TJ and TA are given in degrees centigrade, P is IC power
dissipation in watts and QJA is thermal resistance in
degrees centigrade per watt. Junction temperature should
be calculated for all semiconductor devices to ensure they
are operated below the manufacturerÕs maximum junction
temperature specification. If any componentÕs temperature
exceeds the manufacturerÕs maximum specification, some
form of heatsink will be required.
Heatsinking will improve the thermal performance of any
IC. Adding a heatsink will reduce the magnitude of QJA by
providing a larger surface area for heat transfer to the surrounding air. Typical heat sinking techniques include the
use of commercial heatsinks for devices in TO-220 packages, or printed circuit board techniques such as thermal
bias and large copper foil areas for surface mount packages.
EMI Management
Switching regulators generate noise a consequence of the
large values of current being switched on and off in normal
operation. Careful attention to layout of the printed circuit
board will usually minimize noise problems. Layout guidelines are provided in the next section. However, it may be
necessary in some cases to add filter inductors or bypass
capacitors to the circuitry to achieve the desired performance.
Layout Considerations
The following guidelines should be observed in the layout
of PC boards for the CS5127:
When choosing a heatsink, it is important to break QJA
into several different components.
1. Connect the PGND lead to the external ground with a
wide metal trace.
QJA = QJC + QCS + QSA
2. Connect both LGND and PGND together with a wide
trace as close to the IC as possible.
where all components of QJA are given in ¡C/W.
QJC is the thermal impedance from the junction to the surface of the package case. This parameter is also included in
manufacturerÕs data sheets. Its value is dependent on the
mold compound and lead frames used in assembly of the
semiconductor device in question.
QCS is the thermal impedance from the surface of the case
to the heatsink. This component of the thermal impedance
can be modified by using thermal pads or thermal grease
between the case and the heat sink. These materials replace
the air gap normally found between heatsink and case with
a higher thermal conductivity path. Values of QCS are
found in catalogs published by manufacturers of heatsinks
and thermal compounds.
Finally, QSA is the thermal impedance from the heatsink to
ambient temperature. QSA is the important parameter
when choosing a heatsink. Smaller values of QSA allow
higher power dissipation without exceeding the maximum
junction temperature of the semiconductor device. Values
of QSA are typically provided in catalogs published by
heatsink manufacturers.
The basic equation for selecting a heatsink is
3. Make all ground connections to a common ground
plane with as few interruptions as possible. Breaks in
the ground plane metal should be made parallel to an
imaginary line between the supply connections and the
load.
4. Connect the ground side of the COMP lead capacitors
back to LGND with separate traces.
5. Place the VFFB lead capacitors as close to the VFFB leads
as possible.
6. Place the 5V line bypass capacitors as close to the
switch FETs as possible.
7. Place the output capacitor network as close to the load
as possible.
8. Route the GATE lead signals to the FET gates with a
metal trace at least 0.025 inches wide.
9. Use wide straight metal traces to connect between the
5V line and FETs, between FETs and inductors and
between inductors and loads to minimize resistance in
the high current paths. Avoid sharp turns, loops and
long lengths.
14
CS5127
Additional Application Circuits
5V
5V
R1
6.3K
R3
10K
VOUT
Q2
FMMT2907ACT
R1
24K
Q1
Q2
Q3
FMMT2907ACT
FMMT2907ACT
FMMT2907ACT
R2
1k
R4
10K
OVP OUT
TO VFFB1
Q1
FMMT2222ACT
ENABLE 1
SIGNAL
R2
5K
TO COMP1
Q4
FMMT2222ACT
R3
1K
VOVP =
(R1 + R2)(0.65V)
R2
Figure 14: An external circuit can be built to provide an enable function for channel 1. The circuit shown above connects to the VFB1 and
COMP1 pins as indicated. If the ENABLE1 signal is left floating or is
pulled high, channel 1 is enabled. If the ENABLE1 pin is pulled
below 1V, Q1 will conduct, and mirror Q3 pulls VFFB1 up at the same
time as Q2 and Q4 pull COMP1 low. This will force GATE1 to go low
and turn off the switch FET. The circuit above will provide about
1mA of additional drive to the VFFB1 pin components. This additional
current must be sufficient to pull VFFB1 up to about 1V in order to
guarantee GATE1 is held low.
Figure 12: Example external over voltage protection circuit. If VOUT
exceeds VOVP, OVP out goes high. Resistor values shown above provide a +10% tolerance for a 3.3V output.
5V
VOUT
PGOOD OUT
R1
18K
R3
10K
Q2
FMMT2222ACT
Q1
FMMT2222ACT
R2
5K
VPGOOD =
(R1 + R2)(0.65V)
R2
Figure 13: Example external Power GOOD circuit. PGOOD(OUT) is low
until VOUT exceeds VPGOOD. VPGOOD is typically chosen to be 10%
below nominal VOUT. Resistor values above provide a -10% tolerance
on VOUT =3.3V.
15
CS5127
Additional Application Circuits continued
+5V
+12V
C1
680mF
C2
680mF
C3
1UF
C4
680mF
C5
+5V
680mF
+
+
+
m1
R1
3.3K
1
2
3
R2
100K
R3
24K
C6
390pF
5
C7
7pF
Q1
IRL3103S
C10
680mF
2.8V
4
L1
+
R4
1540
6
7
8
5mH
CS5127
VIN
16
CT
VREF
15
RT
ENABLE
SYNC
VFB1
VFB2
14
+C8
1mF
13
C52
7pF
12
COMP1
COMP2
VFFB1
VFFB2
GATE1
GATE2
LGND
PGND
11
Q2
IRL3103S
L2
10
09
R7
D2
1N5821
2400
R10
2K
R6
2K
R7
10
R5
1270
3.3V
+
D1
1N5821
C11
680mF
C13
C12
680UF 680mF
5mH
R65
18K
C14
0.2mF
C16
0.22mF
C50
0.22mF
Q4
2N3906
R11
2.2K
Q7
2N3906
C15
0.01mF
R8
1500
R66
10
C17
0.2mF
C24
0.01mF
R48
100K
C15
0.1mF
Figure 15: CS5127 12V, 5V input to 2.8V @ 7A and 3.3V @ 7A Voltage Mode Control Application Circuit with External Soft Start.
+12V
D3
1N5818
C2
680mF
C1
680mF
D4
1N5818
+
+
C18
0.1mF
50V
Q1
FMMT2222ACT
m1
1
2
3
R1
20K
C7
330PF
Q2
IRL3103S
7
8
L1 5mH
+
R4
1540
R5
1270
5
6
C10
680mF
2.8V
4
R2
27k
C6
0.1mF
R12
30
CS5127
SYNC
VIN
CT
VREF
RT
ENABLE
VFB1
VFB2
COMP1
COMP2
VFFB1
VFFB2
GATE1
GATE2
LGND
PGND
C4
680mF
15
14
C8
1mF
C3
10mF
+
+
13
D5
1N5248
12
C9
0.1mF
Q3
IRL3103S
11
10
C13
680mF
L2
09
5mH
D1
1N5821
C11
680mF
C5
680mF
16
D2
1N5821
3.3V
+
C12
680mF
R7
2400
R8
1500
R9
2K
R10
20K
C14
330PF
C16
100mF
C15
100mF
R6
1K
Figure 16: CS5127 12V only to 2.8V @ 7A and 3.3V @ 7A Application Circuit.
16
C17
330PF
R11
20K
R3
18K
CS5127
Additional Application Circuits continued
+5V
R69
10K
C2
C1
680mF 680mF
Q4
2N2907
Q7
2N2907
Q1
FMMT2222ACT
R67
15k
R73
1K
+
-
3
C7
330PF
4
5
C6
0.1mF
Q2
IRL3103S
2.8V
+
CS5127
VIN
16
CT
VREF
15
RT
ENABLE
SYNC
C4
680mF
R77
15K
VFB1
14
COMP1
COMP2
12
6
VFFB1
8
VFFB2
11
7
GATE1
GATE2
10
8
LGND
PGND
09
C3
1mF
+ C8
1mF
13
VFB2
R78
15K
+
C9
0.1mF
Q3
IRL3103S
C12
C13
680mF 680mF
RDROOP
L2
5mF
D2
1N5821
D1
1N5821
C11
680mF
R4
1.54K
C25
0.1mF
L1
5mH
.008
+
C5
680mF
-
m1
R68
15k
RDROOP
R76
1M
+
LM2903
U4B
2
C10
680mF
R74
1K
LM2903
U4A
1
R1
20K
R75
1M
R72
20K
R70
20K
C24
0.1mF
+12V
R71
10K
R66
1M
R65
1M
+5V
+12V
+12V
+
.008
R7
2.40K
R8
1.50K
R11
20K
R5
1.27K
3.3V
R9
2K
20K
R10
R6
1K
C14
330PF
C17
C15
100mF
C16
100mF
R3
18K
330PF
Figure 17: 200kHz, V2ª, 5V/12V input, [email protected] 7A and 3.3V @ 7A outputs with current limit.
+12V
+5V
C1
680mF
+5V
C2
680mF
C4
680mF
+
C3
1mF
C5
680mF
+
+
Q1
FMMT2222ACT
m1
1
2
3
R1
20K
C7
330PF
C6
0.1mF
Q2
IRL3103S
7
8
L1 10mH
+
R4
1540
R5
1270
5
6
C10
680mF
2.8V
4
R2
27K
CS5127
SYNC
VIN
CT
VREF
RT
ENABLE
VFB1
VFB2
COMP1
COMP2
VFFB1
VFFB2
GATE1
GATE2
LGND
PGND
16
15
14
C8
1mF
C9
0.1mF
12
Q3
IRL3103S
11
10
C13
680mF
L2
09
D1
1N5821
C11
680mF
+
13
10mH
R17
2400
+
C12
680mF
D2
1N5821
3.3V
R7
2400
R8
1500
R9
2K
R10
20K
C14
330pF
R6
1K
C16
100mF
C15
100mF
8
Q4
IRL3103S
+
1
-
2.5V
4
C17
330pF
R11
20K
R3
18K
U2A
1/2 LM358
3
2
R18
2400
C18
47mF
Figure 18: CS5127 12V, 5V input to 2.8V @7A and 3.3V @ 7A Switching Regulator with External 1A, 2.5V Linear Output for Vclock.
17
CS5127
Typical Performance Characteristics
5.005
18
5.004
Line Regulation (mV)
16
VREF (V)
5.003
5.002
5.001
14
12
10
5.000
4.999
8
0
10
20
30
40
50
60
70
0
10
Temperature (C)
30
40
50
60
70
Temperature (C)
Figure 19: VREF vs Temperature, 1mA Load.
Figure 22: Line Regulation vs Temperature 9V to 20V.
130
Short Circuit Current (mA)
18
16
Load Regulation (mV)
20
14
12
10
120
110
100
90
80
70
8
0
10
20
30
40
50
60
0
70
10
20
30
40
50
60
70
Temperature(C)
Temperature (C)
Figure 23: VREF Short Circuit Current vs Temperature.
Figure 20: Load Regulation vs Temperature 1mA to 10mA.
4.992
1.00E+06
4.990
5.00E+05
4.998
2.00E+05
Frequency (kHz)
VREF (V)
150pF
4.988
4.986
390pF
1.00E+05
680pF
5.00E+04
1.5nF
4.980
2.00E+04
4.978
1.00E+04
3.3nF
0
10
20
30
40
50
60
20
70
22
24
26
28
30
32
34
36
RT (kW)
Temperature (C)
Figure 21: VREF vs Temperature, 10mA Load.
Figure 24: Oscillator Frequency vs RT,CT (VIN = 12V, T = 25C)
18
38
40
CS5127
Typical Performance Characteristics: continued
91.5
1.65
1.60
1.55
Sync Threshhold (V)
Maximum Duty Cycle (%)
91.0
90.5
90.0
89.5
1.50
1.45
1.40
1.35
1.30
89.0
1.25
88.5
1.20
0
20
10
30
40
Temperature (C)
60
50
70
10
30
40
Temperature (C)
20
50
70
60
Figure 28: SYNC Threshold vs Temperature.
210
170
208
165
Sync Input Curernt (mA)
Oscillator Frequency (kHz)
Figure 25: Oscillator Maximum Duty Cycle vs Temperature.
0
206
204
202
160
155
150
145
200
140
0
10
20
30
40
50
60
70
0
10
20
Temperature (C)
Figure 26: Oscillator Frequency vs Temperature. CT = 330pF, RT =27k
30
40
Temperature (C)
50
60
70
Figure 29: SYNC Input Current vs Temperature (VSYNC = 2.4V).
95
1.2785
150pF
1.2780
VFB Reference Voltage (V)
Duty Cycle (%)
90
85
390pF
80
680pF
75
3.3nF
1.5nF
70
1.2775
1.2770
1.2765
1.2760
1.2755
20
22
24
26
28
30
32
34
36
38
40
0
RT (kW)
Figure 27: Oscillator Duty Cycle vs CT, RT (VIN = 12V, T = 25C).
10
20
30
40
Temperature (C)
Figure 30: VFB Reference Voltage vs Temperature.
19
50
60
70
CS5127
Typical Performance Characteristics: continued
225
70
60
180
50
40
Gain (dB)
135
30
Phase (degrees)
20
10
0
-10
-20
-30
90
45
0
-45
1.00E +00 1.00E +01 1.00E +02
1.00E +03 1.00E +04 1.00E +05
1.00E +06
1.00E+00 1.00E+01 1.00E+02
1.00E +07
Frequency (Hz)
1.00E+05 1.00E+06
1.00E+07
Figure 34: Error Amplifier Phase vs Frequency.
1.310
450
1.305
Source Current (mA)
430
Input Curernt (mA)
1.00E+04
Frequency (Hz)
Figure 31: Error Amplifier Gain vs Frequency.
410
390
370
1.300
1.295
1.290
1.285
1.280
350
0
10
20
30
40
Temperature (C)
50
60
0
70
10
20
40
40
50
60
70
Temperature (C)
Figure 35: Error Amplifier Source Current vs Temperature.
Figure 32: SYNC Input Current vs Temperature (VSYNC = 5V).
0.90
0.105
0.103
0.85
Output Low Voltage (V)
VFB Bias Current (mA)
1.00E+03
0.101
0.099
0.097
0.095
0.80
0.75
0.70
0
10
20
30
40
Temperature (C)
50
60
70
0
10
20
30
40
50
Temperature (C)
Figure 36: Error Amplifier Output Low Voltage (500µA) vs
Temperature.
Figure 33: VFB Bias Current vs Temperature.
20
60
70
CS5127
Typical Performance Characteristics: continued
2.28
3.35
ENABLE Threshold (V)
Maximum Common Mode Voltage (V)
3.37
3.33
3.31
3.29
2.26
2.24
2.22
2.20
3.27
0
10
20
30
40
50
60
0
70
10
20
Figure 37: PWM Comparator Maximum Common Mode Input Voltage
vs Temperature.
50
60
70
50
60
70
50
60
70
280
270
ENABLE Bias Current (mA)
17.0
16.5
Sink Current (mA)
40
Figure 40: ENABLE Threshold vs Temperature.
17.5
16.0
15.5
15.0
14.5
260
250
240
230
220
210
0
10
20
30
40
50
60
70
0
10
20
Temperature (C)
Figure 38: Error Amplifier Sink Current vs Temperature.
30
40
Temperature (C)
Figure 41: ENABLE Bias Current vs Temperature.
1.07
215
1.06
GATE Low Voltage (mV)
210
1.05
VFFB Bias (mA)
30
Temperature (C)
Temperature (C)
1.04
1.03
1.02
1.01
205
200
195
190
185
1.00
0.99
180
0
10
20
30
40
50
60
70
0
Temperature (C)
Figure 39: VFFB Bias Current vs Temperature.
10
20
30
40
Temperature (C)
Figure 42: GATE Low Voltage (100mA) vs Temperature.
21
CS5127
1.70
18.0
1.65
17.5
Lockout Voltage (mV)
GATE High Voltage (mV)
Typical Performance Characteristics: continued
1.60
1.55
1.50
1.45
17.0
16.5
16.0
15.5
1.40
15.0
0
10
20
30
40
Temperature (C)
50
60
70
0
10
20
30
40
50
60
70
Temperature (C)
Figure 43: GATE High Voltage (100mA) vs Temperature.
Figure 46: GATE Low Voltage (Lockout) vs Temperature.
8.615
48
47
8.613
Start up Threshold (V)
GATE Low Voltage (mV)
46
45
44
43
42
41
8.611
8.609
8.607
40
8.605
39
0
10
20
30
40
Temperature (C)
50
60
0
70
10
20
30
40
Temperature (C)
50
60
70
50
60
70
Figure 47: VIN Start-up Threshold vs Temperature.
Figure 44: GATE low voltage (20mA) vs Temperature.
400
1.60
1.55
380
Start up Current (mA)
GATE High Voltage (V)
1.50
1.45
1.40
1.35
1.30
360
340
320
1.25
300
1.20
0
10
20
30
40
Temperature (C)
50
Figure 45: GATE High Voltage (20mA) vs Temperature.
60
0
70
10
20
30
40
Temperature (C)
Figure 48: Start-up Current vs Temperature.
22
CS5127
Typical Performance Characteristics: continued
18.5
7.924
7.922
18.0
IC Supply Current (mA)
Shutdown Threshhold (V)
7.92
7.918
7.914
7.912
7.91
17.5
17.0
16.5
16.0
7.908
7.906
15.5
0
10
20
30
40
50
60
0
70
Temperature (C)
10
20
40
30
Temperature (C)
50
60
70
Figure 50: IC Supply Current vs Temperature. No Load on GATE pins.
RT = 27k, CT = 330pF
Figure 49: VIN Shutdown Threshold vs Temperature.
23
CS5127
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES)
PACKAGE THERMAL DATA
Thermal Data
RQJC
typ
RQJA
typ
D
Lead Count
16 Lead SOIC Wide
Metric
Max
Min
10.50
10.10
English
Max Min
.413 .398
16 Lead SOIC Wide
23
105
ûC/W
ûC/W
Surface Mount Wide Body (DW); 300mil wide
7.60 (.299)
7.40 (.291)
10.65 (.419)
10.00 (.394)
0.51 (.020)
0.33 (.013)
1.27 (.050) BSC
2.49 (.098)
2.24 (.088)
1.27 (.050)
0.40 (.016)
2.65 (.104)
2.35 (.093)
0.32 (.013)
0.23 (.009)
D
REF: JEDEC MS-013
0.30 (.012)
0.10 (.004)
Ordering Information
Part Number
CS5127GDW16
CS5127GDWR16
Rev. 11/3/98
Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.
Description
16 Lead SOIC Wide
16 Lead SOIC Wide (tape & reel)
24
© 1999 Cherry Semiconductor Corporation