SN74LVCHR32245A 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES601 – AUGUST 2004 – REVISED SEPTEMBER 2005 FEATURES • • • • • • • • Member of the Texas Instruments Widebus+™ Family Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.8 ns at 3.3 V Input and Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors • • • • • Ioff Supports Partial-Power-Down Mode Operation Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Other Products to Consider: SN74LVC32245, SN74LVCH32245A, SN74LVCR32245A Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DESCRIPTION/ORDERING INFORMATION This 32-bit (quad-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVCHR32245A is designed for asynchronous communication control-function implementation minimizes external timing requirements. between data buses. The This device can be used as four 8-bit transceivers, two 16-bit transceivers, or one 32-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. The data I/Os and control inputs are overvoltage tolerant. This feature allows the use of this device for down translation in a mixed-voltage environment. The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and undershoot. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input circuit and is not disabled by OE or DIR. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) LFBGA – GKE LFBGA – ZKE (Pb-free) ORDERABLE PART NUMBER Tape and reel SN74LVCHR32245AKR 74LVCHR32245AZKER TOP-SIDE MARKING LQ245A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2005, Texas Instruments Incorporated SN74LVCHR32245A 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES601 – AUGUST 2004 – REVISED SEPTEMBER 2005 GKE OR ZKE PACKAGE (TOP VIEW) 1 2 3 4 5 6 A B C D E F G H J K L M N P R T TERMINAL ASSIGNMENTS 2 1 2 3 4 5 6 A 1B2 1B1 B 1B4 1B3 1DIR 1OE 1A1 1A2 GND GND 1A3 C 1B6 1A4 1B5 VCC VCC 1A5 D 1A6 1B8 1B7 GND GND 1A7 1A8 E 2B2 2B1 GND GND 2A1 2A2 F 2B4 2B3 VCC VCC 2A3 2A4 G 2B6 2B5 GND GND 2A5 2A6 H 2B7 2B8 2DIR 2OE 2A8 2A7 J 3B2 3B1 3DIR 3OE 3A1 3A2 K 3B4 3B3 GND GND 3A3 3A4 L 3B6 3B5 VCC VCC 3A5 3A6 M 3B8 3B7 GND GND 3A7 3A8 N 4B2 4B1 GND GND 4A1 4A2 P 4B4 4B3 VCC VCC 4A3 4A4 R 4B6 4B5 GND GND 4A5 4A6 T 4B7 4B8 4DIR 4OE 4A8 4A7 SN74LVCHR32245A 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES601 – AUGUST 2004 – REVISED SEPTEMBER 2005 FUNCTION TABLE (EACH 8-BIT SECTION) INPUTS OE DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation LOGIC DIAGRAM (POSITIVE LOGIC) 1DIR A3 2DIR A4 1A1 H4 1OE A5 2A1 A2 H3 E5 E2 1B1 To Seven Other Channels 3DIR J3 4DIR T4 4A1 J2 T3 3OE J5 To Seven Other Channels 2B1 To Seven Other Channels J4 3A1 2OE 4OE N5 N2 3B1 4B1 To Seven Other Channels 3 SN74LVCHR32245A 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES601 – AUGUST 2004 – REVISED SEPTEMBER 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through each VCC or GND θJA Package thermal Tstg Storage temperature range (1) (2) (3) (4) impedance (4) GKE/ZKE package –65 V 40 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage VIH High-level input voltage Operating Data retention only VCC = 1.65 V to 1.95 V MIN MAX 1.65 3.6 1.5 Low-level input voltage VI 1.7 VCC = 2.7 V to 3.6 V 2 VO Output voltage IOH High-level output current 0.35 × VCC 0.7 VCC = 2.7 V to 3.6 V 0.8 0 5.5 High or low state 0 VCC 3-state 0 5.5 VCC = 1.65 V –2 VCC = 2.3 V –4 VCC = 2.7 V –8 VCC = 3 V IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature 4 V V V mA –12 VCC = 1.65 V 2 VCC = 2.3 V 4 VCC = 2.7 V 8 VCC = 3 V (1) V VCC = 2.3 V to 2.7 V Input voltage V 0.65 × VCC VCC = 2.3 V to 2.7 V VCC = 1.65 V to 1.95 V VIL UNIT mA 12 –40 10 ns/V 85 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. SN74LVCHR32245A 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES601 – AUGUST 2004 – REVISED SEPTEMBER 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH IOH = –2 mA 1.65 V 1.2 IOH = –4 mA 2.3 V 1.7 2.7 V 2 Control inputs 2.4 IOH = –12 mA 3V 2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 2 mA 1.65 V 0.45 IOL = 4 mA 2.3 V 0.7 IOL = 8 mA 2.7 V 0.6 3V 0.8 3.6 V ±5 VI = 0 to 5.5 V VI = 0.58 V VI = 0.7 V VI = 0.8 V VI = 0 to 3.6 VI or VO = 5.5 V IOZ (3) VO = 0 V or (VCC to 5.5 V) VI = VCC or GND ∆ICC 75 One input at VCC – 0.6 V, –75 ±500 0 ±10 µA 2.3 V to 3.6 V ±5 µA IO = 0 3.6 V ≤ VI ≤ 5.5 V (4) µA –45 3.6 V V (2) Ioff ICC 45 3V VI = 2 V 40 3.6 V Other inputs at VCC or GND µA –25 2.3 V VI = 1.7 V V 25 1.65 V VI = 1.07 V II(hold) UNIT V 3V IOL = 12 mA II MAX 1.65 V to 3.6 V VCC – 0.2 IOH = –8 mA VOL MIN TYP (1) VCC 40 2.7 V to 3.6 V 500 µA µA Ci Control inputs VI = VCC or GND 3.3 V 3 pF Cio A or B port VO = VCC or GND 3.3 V 12 pF (1) (2) (3) (4) All typical values are at VCC = 3.3 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. For the total leakage current in an I/O port, please consult the II(hold) specification for the input voltage condition 0 V < VI < VCC, and the IOZ specification for the input voltage conditions VI = 0 V or VI = VCC to 5.5 V. The bus-hold current, at input voltage greater than VCC, is negligible. This applies in the disabled state only. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A or B ten OE tdis OE PARAMETER VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN MAX MIN B or A 1 12.5 A or B 1 15.8 A or B 1 19.2 VCC = 2.7 V VCC = 3.3 V ± 0.3 V UNIT MAX MIN MAX MIN MAX 1 9.5 1 5.7 1.5 4.8 ns 1 12.2 1 7.9 1.5 6.3 ns 1 11.9 1 8.3 2.2 7.4 ns 5 SN74LVCHR32245A 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES601 – AUGUST 2004 – REVISED SEPTEMBER 2005 Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Cpd (1) 6 Power dissipation capacitance Outputs enabled Outputs disabled This information was not available at the time of publication. f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP (1) (1) 39 (1) (1) 4 UNIT pF SN74LVCHR32245A 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES601 – AUGUST 2004 – REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH - V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 7 PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74LVCHR32245AZKER ACTIVE LFBGA ZKE 96 1000 Green (RoHS & no Sb/Br) SN74LVCHR32245AKR ACTIVE LFBGA GKE 96 1000 TBD Lead/Ball Finish MSL Peak Temp (3) SNAGCU Level-3-250C-168 HR SNPB Level-3-220C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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