TI SN74LVC540AQPWRQ1

SN74LVC540A-Q1
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS712A – SEPTEMBER 2003 – REVISED JULY 2005
FEATURES
•
•
•
•
•
•
•
•
•
•
•
(1)
Qualification in Accordance With AEC-Q100 (1)
Qualified for Automotive Applications
Customer-Specific Configuration Control Can
Be Supported Along With Major-Change
Approval
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Operates From 2 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 5.3 ns at 3.3 V
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2 V at
VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With 3.3-V
VCC)
Ioff Supports Partial-Power-Down Mode
Operation
DW OR PW PACKAGE
(TOP VIEW)
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
Contact factory for details. Q100 qualification data available
on request.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
DESCRIPTION/ORDERING INFORMATION
The SN74LVC540A octal buffer/driver is designed for 2.7-V to 3.6-V VCC operation.
This device is ideal for driving bus lines or buffer-memory address registers. This device features inputs and
outputs on opposite sides of the package that facilitate printed circuit board layout.
The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2)
input is high, all outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 125°C
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
SOIC – DW
Reel of 2000
SN74LVC540AQDWRQ1
L540AQ1
TSSOP – PW
Reel of 2000
SN74LVC540AQPWRQ1
L540AQ1
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated
SN74LVC540A-Q1
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS712A – SEPTEMBER 2003 – REVISED JULY 2005
FUNCTION TABLE
INPUTS
OE1
OE2
A
OUTPUT
Y
L
L
L
H
L
L
H
L
H
X
X
Z
X
H
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
OE1
OE2
A1
1
19
2
18
Y1
To Seven Other Channels
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range (2)
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
state (2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
2
DW package
58
PW package
83
–65
150
V
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
SN74LVC540A-Q1
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS712A – SEPTEMBER 2003 – REVISED JULY 2005
Recommended Operating Conditions
(1)
Operating
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
(1)
Data retention only
MIN
MAX
2
3.6
1.5
2
UNIT
V
V
0.8
V
0
5.5
V
High or low state
0
VCC
3-state
0
5.5
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 2.7 V
12
VCC = 3 V
24
–40
125
V
mA
mA
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –100 µA
VOH
VOL
2.7 V to 3.6 V
2.2
3V
2.4
IOH = –24 mA
3V
2.2
IOL = 100 µA
2.7 V to 3.6 V
0.2
IOL = 12 mA
2.7 V
0.4
3V
0.55
IOH = –12 mA
UNIT
VCC – 0.2
2.7 V
IOL = 24 mA
V
V
II
VI = 0 to 5.5 V
3.6 V
±5
µA
IOZ
VO = 0 to 5.5 V
3.6 V
±15
µA
ICC
∆ICC
(1)
(2)
MIN TYP (1) MAX
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V (2)
One input at VCC – 0.6 V, Other inputs at VCC or GND
IO = 0
10
3.6 V
10
2.7 V to 3.6 V
500
µA
µA
Ci
VI = VCC or GND
3.3 V
4
pF
Co
VO = VCC or GND
3.3 V
5.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This applies in the disabled state only.
3
SN74LVC540A-Q1
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS712A – SEPTEMBER 2003 – REVISED JULY 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
ten
OE
tdis
OE
PARAMETER
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN
UNIT
MAX
MIN
MAX
Y
7.1
1
5.3
ns
Y
8
1
6.6
ns
Y
8.2
1
7.4
ns
Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
4
Power dissipation capacitance per buffer/driver
Outputs enabled
Outputs disabled
f = 10 MHz
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
56
31
3
3
UNIT
pF
SN74LVC540A-Q1
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS712A – SEPTEMBER 2003 – REVISED JULY 2005
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
2.7 V
2.7 V
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
1.5 V
1.5 V
6V
6V
50 pF
50 pF
500 Ω
500 Ω
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
SN74LVC540AQDWRQ1
SN74LVC540AQPWRQ1
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
Package
Type
Package
Drawing
ACTIVE
SOIC
DW
20
2000
TBD
Call TI
Call TI
ACTIVE
TSSOP
PW
20
2000
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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