TI SN74LVC162244ADGVR

SCAS664E − MARCH 2001 − REVISED SEPTEMBER 2003
D Member of the Texas Instruments
D
D
D
D
D
D
D
D
D
D
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Widebus  Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.4 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V VCC)
Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 1000-V Charged-Device Model (C101)
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
description/ordering information
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
This 16-bit buffer/driver is designed for 1.65-V to
3.6-V VCC operation.
The SN74LVC162244A is designed specifically to improve both the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as four 4-bit
buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable
(OE) inputs.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot
and undershoot.
ORDERING INFORMATION
TOP-SIDE
MARKING
Tube
SN74LVC162244ADL
Tape and reel
SN74LVC162244ADLR
TSSOP − DGG
Tape and reel
SN74LVC162244ADGGR
LVC162244A
TVSOP − DGV
Tape and reel
SN74LVC162244ADGVR
LD2244A
SSOP − DL
−40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
VFBGA − GQL
VFBGA − ZQL (Pb-free)
LVC162244A
SN74LVC162244AGQLR
Tape and reel
SN74LVC162244AZQLR
LD2244A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright  2003, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
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1
SCAS664E − MARCH 2001 − REVISED SEPTEMBER 2003
description/ordering information (continued)
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator
in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
GQL OR ZQL PACKAGE
(TOP VIEW)
1
2
3
4
5
terminal assignments
6
1
2
3
5
6
A
A
1OE
NC
NC
NC
NC
2OE
B
B
1Y2
1Y1
GND
GND
1A1
1A2
C
1Y4
1Y3
2Y1
VCC
GND
1A4
2Y2
VCC
GND
1A3
D
2A1
2A2
E
2Y4
2Y3
2A3
2A4
C
D
E
F
G
F
3Y1
3Y2
3A2
3A1
G
3Y3
3Y4
GND
GND
3A4
3A3
H
4Y1
4Y2
VCC
GND
4A2
4A1
4A4
4A3
NC
NC
3OE
H
J
4Y3
4Y4
VCC
GND
J
K
4OE
NC
NC
K
NC − No internal connection
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
2
4
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
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SCAS664E − MARCH 2001 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
Pin numbers shown are for the DGG, DGV, and DL packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
GQL/ZQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
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3
SCAS664E − MARCH 2001 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 4)
Operating
VCC
VIH
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
High-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VIL
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
MAX
1.65
3.6
UNIT
V
1.5
0.65 × VCC
1.7
V
2
0.35 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
Low-level input voltage
VI
MIN
0.7
V
0.8
0
5.5
V
High or low state
0
3-state
0
VCC
5.5
V
VCC = 1.65 V
VCC = 2.3 V
−2
VCC = 2.7 V
VCC = 3 V
−8
−4
mA
−12
VCC = 1.65 V
VCC = 2.3 V
2
VCC = 2.7 V
VCC = 3 V
8
4
mA
12
10
ns/V
TA
Operating free-air temperature
−40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SCAS664E − MARCH 2001 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −100 µA
IOH = −2 mA
VOH
VCC
MIN
1.65 V to 3.6 V
1.65 V
VCC−0.2
1.2
IOH = −4 mA
IOH = −6 mA
IOH = −8 mA
IOH = −12 mA
IOL = 100 µA
IOZ
ICC
∆ICC
Ci
Other inputs at VCC or GND
2
3V
2
0.45
0.7
2.7 V
0.4
3V
0.55
2.7 V
0.6
3V
0.8
VI or VO = 5.5 V
VO = 0 to 5.5 V
One input at VCC − 0.6 V,
2.7 V
±5
µA
0
±10
µA
3.6 V
±10
µA
3.6 V
20
2.7 V to 3.6 V
Co
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This applies in the disabled state only.
V
3.6 V
20
VI = VCC or GND
VO = VCC or GND
UNIT
V
2.3 V
IOL = 12 mA
VI = 0 to 5.5 V
IO = 0
2.4
1.65 V
IOL = 4 mA
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V‡
2.2
3V
0.2
IOL = 6 mA
IOL = 8 mA
II
Ioff
1.7
MAX
1.65 V to 3.6 V
IOL = 2 mA
VOL
2.3 V
2.7 V
TYP†
500
µA
A
µA
3.3 V
5.5
pF
3.3 V
6
pF
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tdis
OE
Y
PARAMETER
VCC = 1.8 V
± 0.15 V
MIN
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1.5
6
1
4.3
1
5.6
1.1
4.4
ns
1.5
7.3
1
5
1
6.9
1
5.5
ns
1.5
8.9
1
5.5
1
6.8
1.8
6.3
ns
operating characteristics, TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
Power dissipation capacitance
per buffer/driver
VCC = 1.8 V
TYP
Outputs enabled
Outputs disabled
POST OFFICE BOX 655303
f = 10 MHz
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VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
31
33
35
2
3
4
UNIT
pF
5
SCAS664E − MARCH 2001 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
RL
From Output
Under Test
CL
(see Note A)
VLOAD
Open
S1
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
tPHL
VOH
VM
Output
VM
VOL
tPHL
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VM
VM
VM
0V
tPLZ
tPZL
VLOAD/2
VM
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VOH
Output
VI
Output
Control
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
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MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
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MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
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