ERICSSON PBL386141

Preliminary Information
February 2000
PBL 386 14/1
Subscriber Line
Interface Circuit
Description
Applications
The PBL 386 14/1 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated
circuit for use in ISDN Network Terminal Adapters and other short loop
telecommunication equipment which often are remote powered, and by that, the
available power is limited. The PBL 386 14/1 has been optimized for low total line
interface cost, low power and requires a minimum of external components.
The PBL 386 14/1 has constant current feed, programmable to max 30mA. The SLIC
uses a first battery voltage for On-hook . A second battery voltage is used for
Off-hook and must be connected, to reduce short loop power dissipation. The SLIC
automatically switches between the two battery supply voltages without need for
external components or external control. The loop current controls the switching
between On-hook and Off-hook battery.
The SLIC incorporates loop current, ground key and ring trip detection functions.
The PBL 386 14/1 is compatible with loop start signalling. Two- to four-wire and
four- to two-wire voice frequency (vf) signal conversion is accomplished by the SLIC
in conjunction with either a conventional CODEC/filter or with a programmable
CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable line terminating
impedance could be complex or real to fit every market. Longitudinal voltages are
suppressed by a feedback loop in the SLIC and the longitudinal balance specifications meet Bellcore TR909 requirements.
The PBL 386 14/1 package is a very PCB space efficient 28-pin SSOP.
• ISDN Network terminals
• Shortloop applications
Ring Relay
Driver
RRLY
DT
C1
Ring Trip
Comparator
DR
TIPX
Ground Key
Detector
RINGX
C2
Input
Decoder and
Control
C3
VCC
DET
HP
TS
Two-wire
Interface
Line Feed
Controller
and
Longitudinal
Signal
Suppression
PSG
LP
Key Features
• Small footprint with SSOP package
• On-hook and Off-hook battery with
automatic switching, controlled by
loop current
• On-hook battery current is limited
to 6 mA
• 37 mW on-hook power dissipation in
active state
• Metering 0.5 Vrms (0.7 Vpeak)
• Adaptive Overhead Voltage
The overhead voltage follows
1Vpeak<signals<2.5Vpeak
• Battery supply as low as -10V
• Only +5V in addition to GND
and battery (VEE optional)
• Open loop voltage tracks On-hook
battery
• Full longitudinal current capability
during On-hook
• 43.5V open loop voltage @ -48V
battery feed
• Automatic compensation for
line leakage up to 5 mA
• On-hook transmission
• Programmable loop & ring-trip
detector threshold
• Ground key detector
• Analog temperature guard with status
exclusively viewed at detector output
• Integrated Ring Relay Driver
• Linevoltage measurement
REF
PLC
VBAT2
Off-hook
Detector
PLD
4/1
AGND
VBAT
61
L 38
VTX
BGND
VF Signal
Transmission
RSN
PB
VEE
(optional)
Figure 1. Block diagram.
Package: 28-pin SSOP
1
PBL 386 14/1
Maximum Ratings
Parameter
Symbol
Min
Max
Unit
Temperature, Humidity
Storage temperature range
Operating temperature range
Operating junction temperature range, Note 1
TStg
TAmb
TJ
-55
-40
-40
+150
+110
+140
°C
°C
°C
Power supply, 0°C ≤ TAmb ≤ +70°C
VCC with respect to AGND
VEE with respect to AGND
VBat2 with respect to A/BGND
VBat with respect to BGND, continuous
VBat2 with respect to BGND, 10 ms
VCC
VEE
VBat2
VBat
VBat2
-0.4
VBat
VBat
-75
-80
6.5
0.4
0.4
0.4
0.4
V
V
V
V
V
Power dissipation
Continuous power dissipation at TAmb ≤ +70°C
PD
0.8
W
VCC
V
BGND +13
75 mA
V
Ground
Voltage between AGND and BGND
Relay Driver
Ring relay supply voltage
Ring relay current
VG
-5
Ring trip comparator
Input voltage
Input current
VDT, VDR
IDT, IDR
VBat
-5
VCC
5
V
mA
Digital inputs, outputs (C1, C2, C3, DET)
Input voltage
VID
-0.4
VCC
V
Output voltage (DET not active)
VOD
-0.4
VCC
V
Output current (DET)
IOD
30
mA
TIPX and RINGX terminals, 0°C < TAmb < +70°C, VBat = -50 V
TIPX or RINGX current
TIPX or RINGX voltage, continuous (referenced to AGND), Note 2
TIPX or RINGX, pulse < 10 ms, tRep > 10 s, Note 2
TIPX or RINGX, pulse < 1 µs, tRep > 10 s, Note 2
TIP or RING, pulse < 250 ns, tRep > 10 s, Note 3
ITIPX, IRINGX
VTA, VRA
VTA, VRA
VTA, VRA
VTA, VRA
-110
VBat
VBat - 20
VBat - 40
VBat - 70
+110
2
5
10
15
mA
V
V
V
V
Parameter
Symbol
Min
Max
Unit
Ambient temperature
VCC with respect to AGND
VEE with respect to AGND
VBat with respect to BGND
VBat2 with respect to BGND
TAmb
VCC
VEE
VBat
VBat2
0
4.75
VBat
-58
VBat
+70
5.25
-4.75
-10
-10
°C
V
V
V
V
Recommended Operating Condition
Notes
2
1.
The circuit includes thermal protection. Operation above max. junction temperature may degrade device reliability.
2.
A diode in series with the VBat input increases the permitted continuous voltage and pulse < 10 ms to -85 V.
A pulse ≤1µs is increased to the greater of |-70V| and |VBat -40V|.
3.
RF1 and RF2 ≥ 20 Ω is also required. Pulse is supplied to TIP and RING outside RF1 and RF2.
PBL 386 14/1
Electrical Characteristics
0 °C ≤ TAmb ≤ +70 °C, VCC = +5V ±5 %, VEE = -5V ± 5%, VBat = -58V to -40V, VBat2 = -22V, RLC=18.7kΩ (IL = 27 mA),
RL = 600 Ω, RLD = 50 kΩ, RF1, RF2 = 0 Ω, RRef = 15kΩ, CHP = 68nF, CLP=0.47 µF, RT = 120 kΩ, RRX = 120 kΩ, Current definition:
current is positive if flowing into a pin. Active state includes active normal unless otherwise specified.
Battery definition: VBat = On-hook battery, VBat2 = Off-hook battery.
Parameter
Ref
fig
Conditions
Min
Typ
Max
Unit
Two-wire port
Overload level, VTRO
Off-Hook, ILDC ≥ 10 mA
On-Hook, ILDC ≤ 5 mA
Metering ILDC ≥ 10 mA
Input impedance, ZTR
Longitudinal impedance, ZLoT, ZLoR
Longitudinal current limit, ILoT, ILoR
Longitudinal to metallic balance, BLM
2
Active state
1% THD, Note 1
1.0
1.0
ZLTTX = 200 Ω, f = 16 kHz
Note 2
0 < f < 100 Hz
active state
12
IEEE standard 455-1985, ZTRX = 736 Ω
0.2 kHz < f < 1.0 kHz
53
1.0 kHz < f < 3.4 kHz
53
Longitudinal to metallic balance, BLME
E
BLME = 20 • Log Lo
VTR
3
Longitudinal to four-wire balance, BLFE
E
BLFE = 20 • Log Lo
VTX
3
Metallic to longitudinal balance, BMLE
V
BMLE = 20 • Log TR
;ERX = 0
VLo
4
0.7
ZT/200
20
VPeak
VPeak
VPeak
35
Ω/wire
mArms /wire
70
70
dB
dB
53
53
70
70
dB
dB
59
59
70
70
dB
dB
40
58
dB
active state
0.2 kHz ≤ f ≤ 1.0 kHz
1.0 kHz < f < 3.4 kHz
active state
0.2 kHz ≤ f ≤ 1.0 kHz
1.0 kHz < f < 3.4 kHz
active state
0.2 kHz < f < 3.4 kHz
C
TIPX
Figure 2. Overload level, VTRO, two-wire
port
RL
VTRO
ILDC
1
<< RL, RL= 600 Ω
wC
VTX
PBL 386 14/1
RINGX
RT
E RX
RSN
RRX
RT = 120 kΩ, RRX = 120 kΩ
Figure 3. Longitudinal to metallic (BLME)
and Longitudinal to four-wire (BLFE)
balance
TIPX
ELo
C
V TR
1
wC
<< 150 Ω, RLR = RLT = RL /2= 300Ω
VTX
RLT
PBL 386 14/1
RT
V TX
RLR
RINGX
RSN
RRX
RT = 120 kΩ, RRX = 120 kΩ
3
PBL 386 14/1
Parameter
Ref
fig
Conditions
Four-wire to longitudinal balance, BFLE
4
active state
ERX
VLo
0.2 kHz < f < 3.4 kHz
|ZTR + ZL|
r = 20 • Log
|ZTR - ZL|
0.2 kHz < f < 0.5 kHz
0.5 kHz < f < 1.0 kHz
1.0 kHz < f < 3.4 kHz, Note 3
active normal, IL = 0
active normal, IL = 0
active, IL = 0
Min
Typ
40
58
Max
Unit
BFLE = 20 • Log
Two-wire return loss, r
TIPX idle voltage, VTi
RINGX idle voltage, VRi
|VTR |
Four-wire transmit port (VTX)
Overload level, VTXO
Off-hook, IL ≥ 10mA
On-hook, IL ≤ 5mA
Output offset voltage, ∆VTX
Output impedance, zTX
6
0.5
0.5
-60
5
IRSN = 0 mA
0.2 kHz < f < 3.4 kHz
0.3 kHz < f < 3.4 kHz
GND +25
10
50
mV
Ω
400
ratio
RLT
RT
PBL 386 14/1
0
0.15
0.1
dB
dB
1
<< 150 Ω, RLT = RLR = RL /2 =300Ω
ωC
E RX
RLR
RSN
RT = 120 kΩ, RRX = 120 kΩ
RRX
C
TIPX
Figure 5. Overload level, VTXO, four-wire
transmit port
VTX
RL
ILDC
PBL 386 14/1
RINGX
RT
VTXO
1
<< RL, RL = 600 Ω
ωC
RT = 120 kΩ, RRX = 120 kΩ
RSN
RRX
4
-0.15
-0.5
Figure 4. Metallic to longitudinal and
four-wire to longitudinal balance
VTX
RINGX
EL
60
20
VPeak
VPeak
mV
Ω
0.2 kHz < f < 3.4 kHz
relative to 0 dBm, 1.0 kHz. ERX = 0 V
0.3 kHz < f < 3.4 kHz
f = 8.0 kHz, 12 kHz, 16 kHz
TIPX
V TR
dB
dB
dB
V
V
V
- 1.3
VBat +3.1
|VBat +5.5| |VBat + 4.5|
Load impedance > 20 kΩ,
1% THD, Note 4
Frequency response
Two-wire to four-wire, g2-4
VLo
25
27
23
5
Four-wire receive port (RSN)
Receive summing node (RSN) dc voltage
Receive summing node (RSN) impedance
Receive summing node (RSN)
current (IRSN) to metallic loop current (IL)
gain,αRSN
C
dB
PBL 386 14/1
Parameter
Ref
fig
Four-wire to two-wire, g4-2
6
Four-wire to four-wire, g4-4
6
Four-wire to two-wire, G4-2
6
Gain tracking
Two-wire to four-wire RLDC≤ 2kΩ
Four-wire to two-wire RLDC≤ 2kΩ
relative to 0 dBm, 1.0 kHz. EL = 0 V
0.3 kHz < f < 3.4 kHz
f = 8 kHz, 12 kHz,
16 kHz
relative to 0 dBm, 1.0 kHz. EL = 0 V
0.3 kHz < f < 3.4 kHz
6
Insertion loss
Two-wire to four-wire, G2-4
0 dBm, 1.0 kHz, Note 5
V
G2-4 = 20 • Log TX ,ERX = 0
VTR
0 dBm, 1.0 kHz, Notes 5, 6
V
G4-2 = 20 • Log TR ,EG = 0
ERX
6
Ref. -10 dBm, 1.0 kHz, Note 7
-40 dBm to +3 dBm
-55 dBm to -40 dBm
Ref. -10 dBm, 1.0 kHz, Note 7
-40 dBm to +3 dBm
-55 dBm to -40 dBm
6
Noise
Idle channel noise at two-wire
(TIPX-RINGX)
Harmonic distortion
Two-wire to four-wire
Four-wire to two-wire
Conditions
Min
Typ
Max
Unit
-0.15
-1.0
-1.0
-0.2
-0.3
0.15
0
0
dB
dB
dB
0.15
dB
-5.82
dB
-0.2
0.2
dB
-0.1
-0.2
0.1
0.2
dB
dB
-0.1
-0.2
0.1
0.2
dB
dB
12
-78
dBrnC
dBmp
-50
-50
dB
dB
-0.15
-6.22
C-message weighting
Psophometrical weighting
Note 8
6
0 dBm, 1.0 kHz test signal
0.3 kHz < f < 3.4 kHz
13
ILProg = 500
RLC
18 < ILProg < 30 mA
-6.02
7
-83
Battery feed characteristics
Constant loop current, ILConst
Figure 6.
Frequency response, insertion loss,
gain tracking.
C
0.95 ILProg
TIPX
ILProg
1.05 ILProg mA
VTX
RL
1
<< RL, RL = 600 Ω
ωC
VTR
EL
RT = 120 kΩ, RRX = 120 kΩ
ILDC
PBL 386 14/1
RINGX
RT
E RX
VTX
RSN
RRX
5
PBL 386 14/1
Parameter
Ref
fig
Conditions
Min
Typ
Max
Unit
ILTh = 500
RLD
0.9•ILTh
ILTh
1.1•ILTh
mA
Ground key detector
Ground key detector threshold
ILTIPX and ILRINGX current difference to trigger ground key det.
11
15
19
mA
Ring trip comparator
Offset voltage, ∆VDTDR
Input bias current, IB
Input common mode range, VDT, VDR
-20
-50
VBat+1
0
-20
20
-1
mV
nA
V
0.5
100
V
µA
0.5
VCC
200
200
V
V
µA
µA
0.1
10
0.6
V
kΩ
15
37
40
415
200
18
44
47
mW
mW
mW
mW
mW
Loop current detector
Programmable threshold, IDET
ILTh > 10 mA
Ring relay driver
Saturation voltage, VOL
Off state leakage current, ILk
Digital inputs (C1, C2, C3)
Input low voltage, VIL
Input high voltage, VIH
Input low current, |IIL|
Input high current, IIH
Detector output (DET)
Output low voltage, VOL
Internal pull-up resistor to VCC
Source resistance, RS = 0 Ω
IB = (IDT + IDR)/2
IOL = 50 mA
VOH = 12 V
0.2
0
2.5
VIL = 0.5
VIH = 2.5 V
IOL = 1 mA
Power dissipation (VBat = -48V, VBat2 = -22V, note 9)
Open circuit state
P1
Active State ILo = 0 mA, IL = 0 mA
P2 @ VEE=-5V
P3 @ VEE=VB2
Active State ILo = 0 mA, IL = 0 mA
P4 @ VEE = -5V
Active RL = 300Ω (off-hook)
P5 @ VEE = -5V
Active RL = 600Ω (off-hook)
Power supply currents (VBat = -48V)
VCC current, ICC
Open circuit state
VEE current, IEE
Open circuit state
VBat current, IBat
Open circuit state
VCC current, ICC
Active State ILo= 0 mA, IL = 0 mA
VEE current, IEE
Active State ILo= 0 mA, IL = 0 mA
VBat current, IBat , On-hook
Active State ILo= 0 mA, IL = 0 mA
-0.8
1.3
-0.1
-0.1
2.1
0.1
-0.5
Power supply rejection ratios
VCC to 2- or 4-wire port
VEE to 2- or 4-wire port
VBat to 2- or 4-wire port
VBat2 to 2- or 4-wire port
30
28.5
45
28.5
45
55
60
60
Temperature guard
Junction threshold temperature, TJG
Active State, f = 1 kHz, Vn = 100mV
Active State, f = 1 kHz, Vn = 100mV
Active State, f = 1 kHz, Vn = 100mV
Active State, f = 1 kHz, Vn = 100mV
-0.2
-0.2
3.5
0.3
mA
mA
mA
mA
mA
mA
dB
dB
dB
dB
°C
140
Thermal resistance
28-pin SSOP, θJP28SSOP
6
55
°C/W
PBL 386 14/1
Notes
1.
2.
3.
The overload level is automatically expanded to 2.5 VPeak
when the signal level > 1.0 VPeak and is specified at the
two-wire port with the signal source at the four-wire
receive port.
The two-wire impedance is programmable by selection of
external component values according to:
ZTR = ZT/|G2-4S αRSN| where:
ZTR = impedance between the TIPX and RINGX
terminals
ZT = programming network between the VTX and RSN
terminals
G2-4S = transmit gain, nominally = -0.5
α RSN = receive current gain, nominally = 400 (current
defined as positive flowing into the receivesumming node, RSN, and when flowing from tip to ring).
Higher return loss values can be achieved by adding a
reactive component to RT, the two-wire terminating
impedance programming resistance, e.g. by dividing RT
into two equal halves and connecting a capacitor from the
common point to ground.
4.
5.
6.
7.
8.
9.
The overload level is automatically expanded as needed up
to 1.25 VPeak when the signal level >0.5 VPeak and is
specified at the four-wire transmit port, VTX, with the signal
source at the two-wire port. Note that the gain from the
two-wire port to the four-wire transmit port is G2-4S = -0.5.
Secondary protection resistors RF impact the insertion loss.
The specified insertion loss is for RF = 0.
The specified insertion loss tolerance does not include
errors caused by external components.
The level is specified at the four-wire receive port and
referenced to a 600 Ω programmed two-wire impedance
level.
The two-wire idle noise is specified with the four-wire
receive port grounded (ERX = 0; see figure 6).
The four-wire idle noise at VTX is the two-wire value -6 dB
and is specified with the two-wire port terminated in 600 Ω
(RL). The noise specification is referenced to a 600 Ω
programmed two-wire impedance level at VTX. The fourwire receive port is grounded (ERX = 0).
The VBat2 voltage is optimized for RL=600 Ω with a
programmed linecurrent, IL=27 mA. This gives VBat2=22 V at
the terminal (e.g. calculated to 21.9V).
7
PBL 386 14/1
Pin Description
Refer to figure 7.
SSOP
Symbol
Description
1
2
3
4
RRLY
TS
HP
RINGX
5
6
BGND
TIPX
Ring Relay driver output.
Tip Sense should be connected to TIPX.
High Pass connection for ac/dc separation capacitor CHP. Other end of CHP connects to RINGX (pin 26).
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
Battery Ground, should be tied together with AGND.
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
7
8
9
VBAT
VBAT2
NC
On-hook battery voltage. Negative with respect to BGND.
Off-hook battery voltage, connected in series with a diode.
No Connect. Must be left open.
10
11
PSG
LP
12
DT
13
DR
14
15
NC
NC
Programmable Saturation Guard. Must be connected to VBAT2.
Low Pass saturation guard filter capacitor connected here to filter out noise and improve PSRR. Other end of
CLP connects to VBAT2.
Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level
low, indicating off-hook condition. The ring trip network connects to this input.
Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level
low, indicating off-hook condition. The ring trip network connects to this input.
No Connect. Must be left open.
No Connect. Must be left open.
16
17
18
19
VEE
REF
NC
PLC
20
PLD
21
VCC
22
23
24
25
C3
C2
C1
DET
26
RSN
27
28
AGND
VTX
8
}
-5V power supply, if not -5 V available connect to VB2 or VBAT (VB2 lower power dissipation than VBAT).
A 15kΩ resistor must be connected between this pin and AGND.
No Connect. Must be left open.
Prog. Line Current, the constant current part of the DC feed characteristic is programmed by a resistor
connected from this pin to AGND.
Programmable Loop Detector threshold. The loop detection threshold is programmed by a resistor
connected from this pin to AGND.
+5 V power supply.
C1, C2 and C3 are digital inputs Controlling the SLIC operating states. Refer to section
Operating states for details.
Detector output. Active low when indicating loop or ring trip detection, active high when indicating ground
key detection, active low when indicating temperature alarm.
Receive Summing Node. 400 times the current flowing into this pin equals the metallic (transversal) current
flowing from TIPX to RINGX. Programming networks for two-wire impedance and receive gain connect to the
receive summing node.
Analog Ground, should be tied together with BGND.
Transmit vf output. The ac voltage difference between TIPX and RINGX, the ac metallic voltage, is
reproduced as an unbalanced GND referenced signal at VTX with a gain of -0.5. The two-wire impedance
programming network connects between VTX and RSN.
PBL 386 14/1
RRLY 1
28
VTX
TS 2
27
AGND
HP 3
26
RSN
RINGX 4
25
DET
BGND 5
24
C1
TIPX 6
23
C2
22
C3
VBAT2 8
21
VCC
*NC 9
20
PLD
PSG 10
19
PLC
LP 11
18
NC*
DT
12
17
REF
DR 13
16
VEE
15
NC*
VBAT 7
*NC
28-pin SSOP
14
* Pins must be left open.
Figure 7. Pin configuration 28 pin SSOP package, top view.
SLIC Operating States
State
C3
C2
C1
SLIC operating state
Active detector
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Open circuit
Ringing state
Active state
Active state
Active state
Active state
Not applicable
Not applicable
Detector is set high
Ring trip detector (active low)
Loop detector (active low)
Line Voltage measurament (pulse train)
Temperature guard (active low)
Ground key detector (active high)
Table 1. SLIC operating states.
9
PBL 386 14/1
TIPX
TIP
+
IL
RF
ZL
ZTR
VTR
RHP
EL
+
-
+
G2-4S
-
VTX
+
VTX
RF
RING
IL
RINGX
-
ZT
Z RX
+
RSN
VRX
I L /α RSN
-
PBL 386 14/1
Figure 9. Simplified AC transmission circuit.
Functional Description and Applications
Information Transmission
General
A simplified AC model of the transmission
circuits is shown in figure 9. Circuit analysis
yields:
VTX
VTR =
(1)
- I • 2RF
G2-4S L
VTX VRX
I
(2)
+
= L
ZRX αRSN
ZT
VTR = IL • ZL - EL
VRX
αRSN
RHP
is the analogue ground referenced
receive signal.
is the receive summing node
current to metallic loop current
gain. The nominal value of
αRSN = 400
Internal resistor appprox. 180 kΩ
(3)
Two-Wire Impedance
where:
VTX
is a ground referenced version
of the ac metallic voltage
between the TIPX and RINGX
terminals.
VTR
is the ac metallic voltage
between tip and ring.
EL
is the line open circuit ac metallic
voltage.
IL
is the ac metallic current.
RF
is a fuse resistor.
G2-4S is the SLIC two-wire to fourwire gain (transmit direction) with
a nominal value of -0.5.
(phase shift 180°.)
ZL
is the line impedance.
ZT
determines the SLIC TIPX to
RINGX impedance for signal in
the 0 - 20kHz frequency range.
ZRX
controls four- to two-wire gain.
10
To calculate ZTR, the impedance presented
to the two-wire line by the SLIC including
the fuse resistor RF, let VRX = 0.
From (1) and (2):
ZT
ZTR =
- 2RF
αRSN • G2-4S
Thus with ZTR, G2-4S, αRSN, and RF known:
ZT = αRSN • G2-4S • (2RF - |ZTR|)
Two-Wire to Four-Wire Gain
From (1) and (2) with VRX = 0:
G2-4 =
VTX
=
VTR
ZT/αRSN
ZT
- 2RF
αRSN • G2-4S
Four-Wire to Two-Wire Gain
From (1), (2) and (3) with EL = 0:
G4-2 =
VTR ZT
ZL
•
=
VRX ZRX ZT
- G2-4S • ( ZL + 2RF)
αRSN
In applications where
2RF - ZT/(αRSN • G2-4S) is chosen to be equal
to ZL, the expression for G4-2 simplifies to:
G4-2 = -
ZT
1
•
ZRX 2 • G2-4S
Four-Wire to Four-Wire Gain
From (1), (2) and (3) with EL = 0:
G4-4 =
VTX ZT
G2-4S • ( ZL + 2RF)
•
=
VRX ZRX ZT
- G2-4S • ( ZL + 2RF)
αRSN
PBL 386 14/1
Hybrid Function
The hybrid function can easily be implemented utilizing the uncommitted amplifier
in conventional CODEC/filter combinations.
Please, refer to figure 10. Via impedance
ZB a current proportional to VRX is injected
into the summing node of the combination
CODEC/filter amplifier. As can be seen
from the expression for the four-wire to
four-wire gain a voltage proportional to VRX
is returned to VTX. This voltage is converted
by RTX to a current flowing into the same
summing node. These currents can be
made to cancel by letting:
VTX VRX
+
= 0 (EL = 0)
RTX ZB
The four-wire to four-wire gain, G4-4, includes the required phase shift and thus
the balance network ZB can be calculated
from:
V
ZB = - RTX • RX =
VTX
Z
- RTX • RX •
ZT
ZT
αRSN - G2-4S • ( ZL + 2RF)
G2-4S • ( ZL + 2RF)
When choosing RTX, make sure the
output load of the VTX terminal is (RTX//RT
in Figure 14) > 20 kΩ.
If calculation of the ZB formula above
yields a balance network containing an
inductor, an alternate method is recommended.
The PBL 386 14/1 SLIC may also be
used together with programmable CODEC/
filters. The programmable CODEC/filter
allows for system controller adjustment of
hybrid balance to accommodate different
line impedances without change of hardware. In addition, the transmit and receive
gain may be adjusted. Please, refer to the
programmable CODEC/filter data sheets
for design information.
Longitudinal Impedance
A feed back loop counteracts longitudinal
voltages at the two-wire port by injecting
longitudinal currents in opposing phase.
Thus longitudinal disturbances will appear as longitudinal currents and the TIPX
and RINGX terminals will experience very
small longitudinal voltage excursions, leaving metallic voltages well within the SLIC
common mode range.
The SLIC longitudinal impedance per wire,
ZLoT and ZLoR, appears as typically 20 Ω to
longitudinal disturbances. It should be noted that longitudinal currents may exceed
the dc loop current without disturbing the vf
transmission.
Capacitors CTC and CRC
If RFI filtering is needed, the capacitors
designated CTC and CRC in figure 13, connected between TIPX and ground as well
as between RINGX and ground, may be
mounted.
CTC and CRC work as RFI filters in conjunction with suitable series impedances
(i.e. resistances, inductances). Resistors
RF1 and RF2 may be sufficient, but series
inductances can be added to form a second order filter. Current-compensated inductors are suitable since they suppress
common-mode signals with minimum influence on return loss. Recommended values
for CTC and CRC are below 1 nF. Lower
values impose smaller degradation on return loss and longitudinal balance, but also
attenuate radio frequencies to a smaller
extent. The influence on the impedance
loop must also be taken into consideration
when programming the CODEC. CTC and
CRC contribute to a metallic impedance of
1/(π•f•CTC) = 1/(π•f•CRC), a TIPX to ground
impedance of 1/(2•π•f•CTC) and a RINGX to
ground impedance of 1/(2•π•f•CRC).
AC - DC Separation Capacitor, CHP
The high pass filter capacitor connected
between terminals HP and RINGX p r o vides the separation of the ac and dc
signals. CHP positions the low end frequency response break point of the ac loop in the
SLIC. Refer to table 1 for recommended
value of CHP.
Example: A CHP value of 68 nF will
position the low end frequency response
3dB break point of the ac loop at 13 Hz (f3dB)
according to f3dB = 1/(2•π•RHP•CHP) where
RHP = 180 kΩ.
RTX
VTX
VT
PBL
386 14/1
ZT
ZB
Z RX
Combination
CODEC/Filter
V RX
RSN
Figure 10. Hybrid function.
11
PBL 386 14/1
High-Pass Transmit Filter
When CODEC/filter with a single 5 V power
supply is used, it is necessary to separate
the different signal reference voltages between the SLIC and the CODEC/filter. In
the transmit direction this can be done by
connecting a capacitor between the VTX
output of the SLIC and the CODEC/filter
input. This capacitor will also form, together with RTX and/or the input impedance of
the CODEC/filter, a high-pass RC filter. It is
recommended to position the 3 dB break
point of this filter between 30 and 80 Hz to
get a fast enough response for the dc steps
that may occur with DTMF signaling.
1 VPeak
2.50 V
2.50 V
Capacitor CLP
The capacitor CLP, which connects between
the terminals LP and VBAT2, positions the
high end frequency break point of the low
pass filter in the dc loop in the SLIC. CLP
together with CHP and ZT (see section TwoWire Impedance) forms the total two wire
output impedance of the SLIC.
RFEED
CLP
CHP
[Ω]
[nF]
[nF]
2•25
470
68
Table 1. CLP and CHP values.
Adaptive Overhead Voltage, AOV
The Adaptive Overhead Voltage feature
minimizes the power dissipation and at the
same time provides a flexible solution for
different system requirements and possible future changes concerning voice, metering and other signal levels. This is done
by using an overhead voltage which automatically adapts to the signal level (voice +
metering).
The PBL38615/1 will behave as a SLIC
with fixed overhead for signals in the 020kHz range and with an amplitude less
than 1Vpeak. For signal amplitudes between
1VPeak and 2.5VPeak the adaptive overhead
function will expand the overhead voltage
making it possible for the signal to propagate through the SLIC without distortion (
This is the total sum of voice and metering
signal). The expansion of the overhead
occurs instantaneously. When the signal
amplitude decreases, the overhead returns
to its initial value with a time constant of
approximately one second (see figure 11).
12
2.50 V
Figure 11. The AOV funktion when the AOV-pin is left open. (Observe, burst
undersampled).
During operation the influence of the adaptive overhead function will not effect the
SLIC performance in the constant current
region of operation (see figure 11). If,
however, the SLIC is in the off-hook,
constant voltage region of operation then
the influence of the adaptive headroom will
be apparent as a slight decrease in line
voltage (and hence line current) as the
SLIC adjusts to accommodate the larger
(voice + metering) signal.
Line Feed
If VTR < | VBAT2 | -5.7 approx (See formula
C in Figure 16). the PBL 386 14/1 SLIC will
emulate constant current feed. (references
A-C in Figure 16). The constant current
region is adjustable between 18 mA and 30
mA.
If VTR > | VBAT2 | -5.7 approx (See
formula C in Figure 16). the PBL 38615/1
SLIC will emulate a constant voltage feed
with 2 x 25 Ω source impedance (references C-E in Figure 16). This section is
made as steep as possible to switch battery
faster.
If the loop current is less than 5.5mA then
the SLIC will automatically switch to supply
the DC feed via Vbat rather than Vbat2
(references E in Figure 16). This will not
give any disturbances on the line.
The open loop voltage, VTRMAX, measured
between the TIPX and RINGX terminals
tracks the battery voltage VBAT(references
J in Figure 16). According to the formula:
VTRMAX = | VBAT | -4.6
When the line current is approaching
open loop conditions (references G in Figure
16) the overhead voltage is reduced. The
line voltage is kept nearly constant with a
steep slope corresponding to 2x25 Ω
(references H in Figure 16), to ensure
maximum open loop voltage, even with a
leaking telephone line.
Constant Current Region
The constant current (reference A-C in
Figure 16) is adjusted by connecting a
resistor, RLC, between terminal PLC and
ground according to the equation:
RLC =
500 10.4 • In (ILProg • 32)
ILProg
ILProg
Can simplifies to:
500
RLC =
ILProg
PBL 386 14/1
Battery Switch
To reduce short loop power dissipation, a
second battery voltage, Off-hook, must be
connected to the device via an external
diode at terminal VBAT2. The SLIC automatically switches between the two battery
supply voltages without need for external
control. The silent battery switching to VBAT
occurs when the line current is below 5.5
mA. This means that the current in the Onhook battery is limited to 6 mA. To calculate
the switching voltage use this formula (See
formula C in Figure 16):
mA
30
25
IB2
20
15
IB
10
5
0
0Ω 1000Ω
VTR =| VB2 | -4.4 - 50 · ILProg
If metering is used see section Metering
Applications down below.
2500Ω
5000Ω
7500Ω
10000Ω
∞Ω
Figure 12. Chart describing current in Vbat and Vbat2.
VBAT 2
mW
Connect the terminal VBAT2 to the
second power supply via the diode DB2 in
Figure 14. A diode DBB connected between
VB and the VB2 power supply, see Figure
14, will make sure that the SLIC continues
to work on the second battery even if the
first battery voltage disappears.
800
The current commute between the different batteries as shown in figure 12, note
that some current is sourced from VB (typ.
0.5 mA, internal bias current) when the line
current is sourced from VB2. The next chart
(figure 13) is showing what power dissipation the SLIC is using with different batteries and variation of the line.
300
28 V
700
25 V
600
22 V
500
400
200
100
0
0Ω 1000Ω
2500Ω
5000Ω
7500Ω
10000Ω
∞Ω
Figure 13. Chart describing Power dissipation with different Vbat2.
Metering Applications, TTX
It is very easy to use PBL 386 14/1 in
metering applications; simply connect a
suitable resistor (RTTX) in series with a
capacitor (CTTX) between pin RSN and the
metering source. Capacitor CTTX decouples
all DC-voltages that may be superimposed
on the metering signal. The metering signal
gain can be calculated from the equation:
G4-2TTX =
VTR
=
VTTX
ZT .
ZLTTX
RTTX ZT + G2-4S . (ZLTTX + 2RF)
αRSN
where:
VTTX is the wanted metering voltage
between the TIP and RING terminals
ZLTTX is the line impedance seen by the 12
or 16 kHz metering signal,
G2-4S is the transmit gain through the SLIC,
i e 0.5.
It is possible to mix voice voltage and
metering voltage up to 2.5 Vpeak (1.7 Vrms),
using AOV. Use following formula to
calculate the switching voltage of the Battery
Switch to get enough signal space.
VTR =| VB2 | -3.4 -Vvoice-VTTX- 50 · ILProg
where:
Vvoice is the voice voltage, normaly 1 Vpeak
VTTX is the the metering voltage in peak.
13
PBL 386 14/1
Analog Temperature Guard
The widely varying environmental
conditions in which SLICs operate may
lead to the chip temperature limitations
being exceeded. The PBL 386 14/1 SLIC
reduces the dc line current and the
longitudinal current limit when the chip
temperature reaches approximately 145°C
and increases it again automatically when
the temperature drops.
The detector output, DET, is forced to a
logic low level when the temperature guard
is active.
The Active state temperature guard is
exclusively viewed at detector output see
section Active Temperature guard.
Loop Monitoring Functions
The loop current, ground key and ring trip
detectors report their status through a common output, DET. The status of the detector pin, DET, is selected via the three bit
control interface C1, C2 and C3. Please
refer to section Control Inputs for a description of the control interface.
Loop Current Detector
The loop current detector indicates that
the telephone is off hook and that DC
current is flowing in the loop by putting the
output pin DET, to a logic low level when
selected. The loop current detector threshold value, ILTh, where the loop current detector changes state, is programmable with
the RLD resistor. RLD connects between pin
PLD and ground and is calculated according to:
500
RLD =
ILTh
Ground Key Detector
The ground key detector indicates when
the ground key is pressed (active) by putting the output pin DET to a logic high level
when selected. The ground key detector
circuit senses the difference between TIPX
and RINGX currents. The detector is triggered when the difference exceeds the
current threshold.
14
Ring Trip Detector
Ring trip detection is accomplished by
connecting an external network to a comparator in the SLIC with inputs DT and DR.
The ringing source can be balanced or
unbalanced e g superimposed on the battery voltage or ground. The unbalanced
ringing source may be applied to either the
ring lead or the tip lead with return via the
other wire. A ring relay driven by the SLIC
ring relay driver connects the ringing source
to tip and ring.
The ring trip function is based on a polarity change at the comparator input when
the line goes off-hook. In the on-hook state
no dc current flows through the loop and
the voltage at comparator input DT is more
positive than the voltage at input DR. When
the line goes off-hook, while the ring relay
is energized, dc current flows and the comparator input voltage reverses polarity.
Figure 14 gives an example of a ring trip
detection network. This network is applicable, when the ring voltage superimposed
on the battery voltage is injected on the ring
lead of the two-wire port. The dc voltage
across sense resistor RRT is monitored by
the ring trip comparator input DT and DR
via the filter network R1, R2, R3, R4, C1 and
C2. DT is more positive than DR, with the
line on-hook (no dc current). The DET
output will report logic level high, i.e. the
detector is not tripped. When the line goes
off-hook, while ringing, a dc current will flow
through the loop including sense resistor
RRT and will cause the input DT to become
more negative than input DR. This changes the output on the DET pin to logic level
low, i.e. tripped detector condition. The
system controller (or line card processor)
responds by de-energizing the ring relay
via the SLIC, i.e. ring trip.
Complete filtering of the 20 Hz ac component at terminals DT and DR is not necessary. A toggling DET output can be examined by a software routine to determine the
duty cycle. Off-hook condition is indicated
when the DET output is at logic level low for
more than half the time.
Detector Output (DET)
The PBL 386 14/1 SLIC incorporates a
detector output driver designed as open
collector (npn) with a current sinking capability of min 3 mA, and a 10 kΩ pull-up
resistor. The emitter of the drive transistor
is connected to AGND. A LED can be
connected in series with a resistor (≈1 kΩ)
at the DET output to visualize, for example
loop status.
Relay driver
The PBL 386 14/1 SLIC incorporates a
ring relay driver designed as open collector
(npn) with a current sinking capability of 50
mA.The emitter of the drive transistor is
connected to BGND. The relay driver has
an internal zener diode clamp to protect the
SLIC from inductive kick-back voltages. No
external clamp is needed.
Control Inputs
The PBL 386 14/1 SLIC has three digital
control inputs, C1, C2 and C3.
A decoder in the SLIC interprets the control
input condition and sets up the commanded operating state.
C1 to C3 are internal pull-up inputs.
Open Circuit State
In the Open Circuit State the TIPX and
RINGX line drive amplifiers as well as other
circuit blocks are powered down. This causes the SLIC to present a high impedance to
the line. Power dissipation is at a minimum
and no detectors are active.
PBL 386 14/1
PBL 386 14/1
KR
RTX
+12 V /+5V
RRLY
-
VTX
CGG
CHP
RF1
RING
OVP
CRC
VB
RF2
TIP
CTC
VB
R1
CB
CLP
ERG
RRF
HP
RSN
RINGX
DET
BGND
C1
TIPX
C2
RRT
R2
out
RT
+
RB
RRX
out
CODEC/
Filter
C3
VBAT2
VCC
NC
PLD
VCC
RLD
CB2
DBB
AGND
VBAT
DB2
VB2
DB
TS
C1
R3
R4
PSG
PLC
LP
NC
DT
REF
DR
VEE
NC
NC
RLC
SYSTEM CONTROL
INTERFACE
RREF
VEE
C2
VCC
+5 V
CVCC
CVEE
VBAT<VEE<-5 V
RESISTORS (values according to IEC63 E96 series):
RLD
RLC
RREF
RT
RTX
RB
RRX
R1
R2
R3
R4
RRT
RRF
RF1, RF2
= 49.9 kΩ 1% 1/10 W
= 18.7 kΩ 1% 1/10 W
= 15 kΩ
1% 1/10 W
= 105 kΩ 1% 1/10 W
= 32.4 kΩ 1% 1/10 W
= 57.6 kΩ 1% 1/10 W
= 105 kΩ 1% 1/10 W
= 604 kΩ 1% 1/10 W
= 604 kΩ 1% 1/10 W
= 249 kΩ 1% 1/10 W
= 280 kΩ 1% 1/10 W
= 332 Ω
5% 2 W
= 332 Ω
5% 2 W
= Line resistor, 40 Ω 1% match
CAPACITORS: (values according to
IEC-63 E6 series):
CB
CB2
CVCC
CVEE
CTC
CRC
CHP
CLP
CGG
C1
C2
CSPR
= 100 nF
= 150 nF
= 100 nF
= 100 nF
= 1.0 nF
= 1.0 nF
= 68 nF
= 470 nF
= 220 nF
= 330 nF
= 330 nF
= optional
100 V 20%
100 V 20%
10 V 20%
10 V* 20%
100 V 20%
100 V 20%
100 V 20%
100 V 20%
100 V 20%
63 V 10%
63 V 10%
10 V 20%
DIODES:
DB
DB2
DBB
VEE
= 1N4448
= 1N4448
= 1N4448
OVP:
Secondary protection ( e g Power
Innovations TISP PBL2). The ground terminals of the secondary protection should be
connected to the common ground on the
Printed Board Assembly with a track as short
and wide as possible, preferably a
groundplane.
*100V if VEE pin connected to VBAT, VBAT2
Figure 14. Single-channel subscriber line interface with PBL 386 14/1 and combination CODEC/filter
Ringing State
Active State
In the ringing state the SLIC will behave as
in the active state with the exception that
the ring relay driver and the ring trip detector are activated. The ring trip detector will
indicate off hook with a logic low level at the
detector output.
TIPX is the terminal closest to ground and
sources loop current while RINGX is the
more negative terminal and sinks loop current. The loop current or the ground key
detector is activated. The loop current detector indicates off hook with a logic low
level and the ground key detector indicates
active ground key with a logic high level
present at the detector output.
Active Temperature guard state
The temperature guard indicates if an error
has occurred and the temperature guard is
activated. The output pin DET is forced to
a logic low level when activated .
15
PBL 386 14/1
Line Voltage measurement
The line voltage is presented on the detector output as a pulse train (see Figure 15)
with a frequency inversely proportional to
the voltage according to the equation:
freq =
106
[Hz]
|VTR| + 1
The line voltage measurement will be
started when entering this state from any
other state and the SLIC will be as in active
state except for the detector. The data can
be used in variety of ways, for example to
set transmission parameters in a programmable CODEC, in line testing where short
circuits on the line can be detected and to
control the metering signal amplitude.
Overvoltage Protection
PBL 386 14/1 must be protected against
overvoltages on the telephone line. The
overvoltages could be caused for instance
by lightning, ac power contact and induction. Refer to Maximum Ratings, TIPX and
RINGX terminals, for maximum continuous and transient voltages.
Secondary Protection
The circuit shown in Figure 14 utilizes series
resistors together with a programmable
overvoltage protector (e g Power Innovations TISP PBL2), serving as a secondary
protection.
The TISP PBL2 is a dual forward-conducting buffered p-gate overvoltage protector. The protector gate references the
protection (clamping) voltage to negative
supply voltage (i.e. the battery voltage, VB).
As the protection voltage will track the
negative supply voltage the overvoltage
stress on the SLIC is minimized.
Positive overvoltages are clamped to
ground by a diode. Negative overvoltages
are initially clamped close to the SLIC negative supply rail voltage and the protector
will crowbar into a low voltage on-state
condition, by firing an internal thyristor.
16
Figure 15. Line voltage measurment
A gate decoupling capacitor, CGG, is needed to carry enough charge to supply a high
enough current to quickly turn on the thyristor in the protector. CGG should be placed
close to the overvoltage protection device.
Without the capacitor even the low inductance in the track to the VB supply will limit
the current and delay the activation of the
thyristor clamp.
The fuse resistors RF serve the dual
purposes of being non- destructive
energy dissipators, when transients are
clamped and of being fuses, when the
line is exposed to a power cross. If a
PTC is chosen for RF , note that it is
important to always use the PTC´s in
series with resistors not sensitive to
temperature, as the PTC will act as a
capacitance for fast transients and
therefore will not protect the TISP.
Power-up Sequence
No special power-up sequence is necessary except that ground has to be present
before all other power supply voltages.
The digital inputs C1 to C3 are internal
pull-up terminals.
Printed Circuit Board Layout
Care in Printed Circuit Board (PCB) layout
is essential for proper function;
The components connecting to the RSN
input should be placed in close proximity to
that pin, such that no interference is injected into the RSN pin. Ground plane surrounding the RSN pin is advisable.
Analog ground (AGND) should be connected to battery ground (BGND) on the
PCB in one point.
RLC and RREF should be connected to
AGND with short leads. Pin LP and pin
PSG are sensitive to leakage currents.
RSG and CLP connections to VBAT2 should
be short and very close to each other.
CB and CB2 must be connected with short
wide leads.
PBL 386 14/1
A
C
B
I L [mA]
D
E
G
H
F
J
V TR [V]
A:
IL (@ VTR = 0) = ILConst
ILConst (typ) = ILProg
=
500
RLC (13)
B,C:
IL = ILConst , VTR(@C)= VApp - RFeed . ILProg
D:
RFeed = 2 x 25 Ω
E:
IL ≈ 5.5 mA , VTR= VApp - RFeed . 5.5 mA
F:
VAPP (@IL =0) = VB2 - VF*-3.7
G:
IL ≈ 5 mA
H:
RFeed = 2 x 25 Ω
J:
VTRMAX = |VBat| - 4.6 @ IL = 0 mA
* Is the forward voltage of diode DVBAT2.
Figure 16. Battery feed characteristics (without the protection resistors on the line).
17
PBL 386 14/1
Ordering Information
Package
Temp. Range
Part No.
28pin SSOP Tape & Reel
0° - + 70 °C
PBL 386 14/1 SHT
Information given in this data sheet is believed to be
accurate and reliable. However no responsibility is
assumed for the consequences of its use nor for any
infringement of patents or other rights of third
parties which may result from its use. No license is
granted by implication or otherwise under any patent
or patent rights of Ericsson Microelectronics AB.
These products are sold only according to Ericsson
Microelectronics general conditions of sale, unless
otherwise confirmed in writing.
Specifications subject to change without
notice.
1522-PBL 386 14/1 Uen Rev. R1A
© Ericsson Microelectronics AB, 2000
This product is an original Ericsson
product protected by US, European and
other patents.
Ericsson Microelectronics
SE-164 81 Kista-Stockholm, Sweden
Telephone: +46 8 757 50 00
18