PRELIMINARY FPD6836SOT343 LOW NOISE, HIGH LINEARITY PACKAGED PHEMT • PERFORMANCE (1850 MHz) ♦ 0.5 dB Noise Figure ♦ 20 dBm Output Power (P1dB) ♦ 20 dB Small-Signal Gain (SSG) ♦ 32 dBm Output IP3 ♦ Evaluation Boards Available • DESCRIPTION AND APPLICATIONS The FPD6836SOT343 is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT). It utilizes a 0.25 µm x 360 µm Schottky barrier Gate, defined by high-resolution stepper-based photolithography. The recessed and offset Gate structure minimizes parasitics to optimize performance, with an epitaxial structure designed for improved linearity over a range of bias conditions and input power levels. The FPD6836 is available in die form and in other packages. Typical applications include drivers or output stages in PCS/Cellular base station high-interceptpoint LNAs, WLL and WLAN systems, and other types of wireless infrastructure systems. • ELECTRICAL SPECIFICATIONS AT 22°C Parameter Symbol Test Conditions Min Typ Max Units 0.9 dB RF SPECIFICATIONS MEASURED AT f = 1850 MHz USING CW SIGNAL Minimum Noise Figure Output Third-Order Intercept Point NF IP3 (from 15 to 5 dB below P1dB) VDS = 3.0 V; IDS = 50% IDSS 0.5 VDS = 3.0 V; IDS = 25% IDSS 0.4 VDS = 3.0 V; IDS = 50% IDSS 32 VDS = 3.0 V; IDS = 25% IDSS dBm 30 Tuned for Optimum IP3 Small-Signal Gain SSG VDS = 3.0 V; IDS = 50% IDSS 18 VDS = 3.0 V; IDS = 25% IDSS Power at 1dB Gain Compression P1dB VDS = 3.0 V; IDS = 50% IDSS 20 dB 18 18 VDS = 3.0 V; IDS = 25% IDSS 20 dBm 18 Saturated Drain-Source Current IDSS VDS = 1.3 V; VGS = 0 V Maximum Drain-Source Current IMAX VDS = 1.3 V; VGS ≅ +1 V 200 mA Transconductance GM VDS = 1.3 V; VGS = 0 V 100 mS Gate-Source Leakage Current IGSO VGS = -5 V 1 10 µA Pinch-Off Voltage |VP| VDS = 1.3 V; IDS = 0.75 mA 0.7 1.0 1.3 V Gate-Source Breakdown Voltage |VBDGS| IGS = 0.75 mA 12 18 V Gate-Drain Breakdown Voltage |VBDGD| IGD = 0.75 mA 12 18 V Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis 90 135 mA Revised: 09/15/05 Email: [email protected] PRELIMINARY FPD6836SOT343 LOW NOISE, HIGH LINEARITY PACKAGED PHEMT • ABSOLUTE MAXIMUM RATINGS1 Parameter Symbol Test Conditions Drain-Source Voltage VDS Gate-Source Voltage Max Units -3V < VGS < +0V 6 V VGS 0V < VDS < +8V -3 V Drain-Source Current IDS For VDS > 2V IDSS mA Gate Current IG Forward or reverse current 5 mA PIN Under any acceptable bias state 60 mW Channel Operating Temperature TCH Under any acceptable bias state 175 ºC Storage Temperature TSTG Non-Operating Storage 150 ºC Total Power Dissipation PTOT See De-Rating Note below 0.5 W Comp. Under any bias conditions 5 dB RF Input Power 2 Gain Compression 3 Min -40 Simultaneous Combination of Limits 2 or more Max. Limits 80 2 TAmbient = 22°C unless otherwise noted Max. RF Input Limit must be further limited if input VSWR > 2.5:1 3 Users should avoid exceeding 80% of 2 or more Limits simultaneously % 1 Notes: • Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device. • Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where: PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power • Total Power Dissipation to be de-rated as follows above 22°C: PTOT= 0.5W – (0.0056W/°C) x TPACK where TPACK = source tab lead temperature above 22°C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 65°C source lead temperature: PTOT = 0.5W – (0.0056 x (65 – 22)) = 0.26W • HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model. Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263. • APPLICATIONS NOTES & DESIGN DATA Applications Notes are available from your local Filtronic Sales Representative or directly from the factory. Complete design data, including S-parameters, noise data, and large-signal models are available on the Filtronic web site. Evaluation Boards available upon request. Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Revised: 09/15/05 Email: [email protected] PRELIMINARY FPD6836SOT343 LOW NOISE, HIGH LINEARITY PACKAGED PHEMT • BIASING GUIDELINES ¾ Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is applied before Drain bias, otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for additional information. ¾ Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices such as the FPD750SOT343. ¾ Self-biased circuits employ an RF-bypassed Source resistor to provide the negative Gate-Source bias voltage, and such circuits provide some temperature stabilization for the device. A nominal value for circuit development is 5.45 Ω for a 50% of IDSS operating point. ¾ For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. Note that pHEMTs, since they are “quasi- E/D mode” devices, exhibit Class AB traits when operated at 50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25% to 33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3 performance. • PACKAGE OUTLINE (dimensions in mm) All information and specifications subject to change without notice. Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Revised: 09/15/05 Email: [email protected] PRELIMINARY FPD6836SOT343 LOW NOISE, HIGH LINEARITY PACKAGED PHEMT Gain (dB) 25.00 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 20.00 15.00 10.00 Frequency (GHz) Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis 5.90 5.40 4.90 4.40 3.90 3.40 2.90 2.40 1.90 1.40 0.90 0.40 5.00 NF (dB) Gain & Noise Figure vs Frequency Gain NF Revised: 09/15/05 Email: [email protected]