PRELIMINARY • FPD6836P70 HI-FREQUENCY PACKAGED PHEMT PERFORMANCE ♦ 22 dBm Output Power (P1dB) ♦ 19 dB Power Gain (G1dB) at 1.85 GHz ♦ 0.5 dB Noise Figure at 1.85 GHz ♦ 32 dBm Output IP3 ♦ 50% Power-Added Efficiency at 1.85 GHz ♦ Useable Gain to 20 GHz ♦ Evaluation Boards Available GATE LEAD IS ANGLED • DESCRIPTION AND APPLICATIONS The FPD6836P70 is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT). It utilizes a 0.25 µm x 360 µm Schottky barrier Gate, defined by high-resolution stepper-based photolithography. . The FPD6836 is also available in die form . Typical applications include gain blocks and medium power stages for applications to 22 GHz. • ELECTRICAL SPECIFICATIONS AT 22°C Parameter Symbol Test Conditions Min Typ Max Units RF SPECIFICATIONS MEASURED AT f = 1850 MHz USING CW SIGNAL (except as noted) Power at 1dB Gain Compression P1dB VDS = 5 V; IDS = 50% IDSS 22 dBm Gain at 1dB Gain Compression SSG VDS = 5 V; IDS = 50% IDSS 19 dB Power-Added Efficiency PAE VDS = 5 V; IDS = 50% IDSS; POUT = P1dB 45 % Maximum Stable Gain (S21/S12) MSG VDS = 5 V; IDS = 50% IDSS f = 12 GHz 13 f = 18 GHz 11 Noise Figure NF VDS = 5 V; IDS = 25% IDSS 0.5 dB Output Third-Order Intercept Point IP3 VDS = 5V; IDS = 50% IDSS 32 dBm Saturated Drain-Source Current IDSS VDS = 1.3 V; VGS = 0 V Maximum Drain-Source Current IMAX VDS = 1.3 V; VGS ≅ +1 V 215 mA Transconductance GM VDS = 1.3 V; VGS = 0 V 140 mS Gate-Source Leakage Current IGSO VGS = -5 V 1 10 µA Pinch-Off Voltage |VP| VDS = 1.3 V; IDS = 0.2 mA 0.7 0.9 1.3 V Gate-Source Breakdown Voltage |VBDGS| IGS = 0.2 mA 12 14 V Gate-Drain Breakdown Voltage |VBDGD| IGD = 0.2 mA 14.5 16 V Thermal Resistivity (see Notes) θJC VDS > 3V 275 °C/W POUT = 11 dBm SCL Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis 85 105 125 mA Revised: 7/15/05 Email: [email protected] PRELIMINARY • FPD6836P70 HI-FREQUENCY PACKAGED PHEMT ABSOLUTE MAXIMUM RATINGS1 Parameter Symbol Test Conditions Drain-Source Voltage VDS -3V < VGS < +0V Min Max Units 8 V Gate-Source Voltage VGS 0V < VDS < +8V -3 V Drain-Source Current IDS For VDS > 2V IDSS mA Gate Current IG Forward or reverse current 15 mA PIN Under any acceptable bias state 170 mW Channel Operating Temperature TCH Under any acceptable bias state 175 ºC Storage Temperature TSTG Non-Operating Storage 150 ºC Total Power Dissipation PTOT See De-Rating Note below 550 mW Comp. Under any bias conditions 5 dB RF Input Power 2 Gain Compression 3 -40 Simultaneous Combination of Limits 2 or more Max. Limits 80 2 TAmbient = 22°C unless otherwise noted Max. RF Input Limit must be further limited if input VSWR > 2.5:1 3 Users should avoid exceeding 80% of 2 or more Limits simultaneously % 1 Notes: • Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device. • Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where: PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power • Total Power Dissipation to be de-rated as follows above 22°C: PTOT= 550mW – (3.6mW/°C) x TPACK where TPACK = source tab lead temperature above 22°C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 65°C source lead temperature: PTOT = 550mW – (3.6 x (65 – 22)) = 323mW • HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 0 (< 250V) per JESD22-A114-B, Human Body Model, and Class A (< 200V) per JESD22-A115-A, Machine Model. • APPLICATIONS NOTES & DESIGN DATA Applications Notes are available from your local Filtronic Sales Representative or directly from the factory. Complete design data, including S-parameters, noise data, and large-signal models are available on the Filtronic web site. Evaluation Boards available upon request. Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Revised: 7/15/05 Email: [email protected] PRELIMINARY FPD6836P70 HI-FREQUENCY PACKAGED PHEMT • BIASING GUIDELINES ¾ Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is applied before Drain bias, otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for additional information. ¾ Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices such as the FPD6836P70. ¾ For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. Note that pHEMTs, since they are “quasi- E/D mode” devices, exhibit Class AB traits when operated at 50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25% to 33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3 performance. • PACKAGE OUTLINE AND RECOMMENDED PC BOARD LAYOUT (DIMENSIONS IN mm) All information and specifications subject to change without notice. Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Revised: 7/15/05 Email: [email protected]