SCLS573 − MARCH 2004
D Injection Current Cross−Coupling
D
D
D
D
D
D, DGV, N, OR PW PACKAGE
(TOP VIEW)
<1mV/mA (see Figure 1)
Low Crosstalk Between Switches
Pin Compatible with SN74HC4052,
SN74LV4052A, and CD4052B
2-V to 6-V VCC Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
2Y0
2Y2
2-COM
2Y3
2Y1
INH
NC
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
1Y2
1Y1
1-COM
1Y0
1Y3
A
B
NC − No internal connection
description/ordering information
This dual 4-to-1 CMOS analog multiplexer/demultiplexer is pin compatible with the 4052 function and also
features injection-current effect control. This feature has excellent value in automotive applications where
voltages in excess of normal supply voltages are common.
The injection-current effect control allows signals at disabled analog input channels to exceed the supply
voltage without affecting the signal of the enabled analog channel. This eliminates the need for external
diode/resistor networks typically used to keep the analog channel signals within the supply voltage range.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
PDIP − N
SOIC − D
−40°C to 125°C
TSSOP − PW
Tube
SN74HC4852N
Tube
SN74HC4852D
Tape and reel
SN74HC4852DR
Tube
SN74HC4852PW
Tape and reel
SN74HC4852PWR
TOP-SIDE
MARKING
SN74HC4852N
HC4852
HC4852
TVSOP − DGV
Tape and reel
SN74HC4852DGVR
HC4852
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
A
ON
CHANNEL
L
L
1Y0, 2Y0
L
H
1Y1, 2Y1
INH
B
L
L
L
H
L
1Y2, 2Y2
L
H
H
1Y3, 2Y3
H
X
X
None
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
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1
SCLS573 − MARCH 2004
logic diagram (positive logic)
13
12
A
14
9
11
1
5
2
INH
1Y0
10
15
B
1-COM
6
4
3
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
2-COM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7.0 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Switch I/O voltage range, VIO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
I/O diode current, IIOK (VIO < 0 or VIO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Switch through current, IS (VIO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCLS573 − MARCH 2004
recommended operating conditions (see Note 4)
MIN
VCC
VIH
Supply voltage
2
VCC = 2 V
VCC = 3 V
High-level input voltage,
control inputs
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VIO
Low-level input voltage,
control inputs
2.3
V
3.15
4.2
0.5
0.9
VCC = 4.5 V
VCC = 6 V
1.35
1
V
1.8
0
Input/output voltage
0
VCC = 3.3 V
VCC = 4.5 V
V
2.1
Control input voltage
Input transition rise or fall rate
6
UNIT
1.5
VCC = 3 V
VCC = 3.3 V
VCC = 2 V
VCC = 3 V
∆t/∆v
MAX
VCC
VCC
V
V
1000
800
700
ns
500
VCC = 6 V
400
TA
Operating free-air temperature
−40
125
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
SCLS573 − MARCH 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
ron
∆ron
II
IS(off)
IS(on)
ICC
CIC
TEST CONDITIONS
IS ≤ 2 mA
VI = VCC to GND,
VINH = VIL
(see Figure 5)
On-state
switch resistance
IS ≤ 2 mA
VI = VCC/2
VINH = VIL
Difference in
on-state resistance
between switches
Control input current
Off-state switch
leakage current
(any one channel)
VI = VCC or GND
VI = VCC or GND
VINH = VIH
(see Figure 6)
Off-state switch
leakage current
(common channel)
VI = VCC or GND
VINH = VIH
(see Figure 7)
On-state switch
leakage current
VI = VCC or GND,
VINH = VIL
(see Figure 8)
Supply current
Control input capacitance
VI = VCC or GND
A, B, INH
VCC
MIN
TA = 25°C
TYP
MAX
−40 TO 85°C
MIN
MAX
−40 TO 1255C
MIN
MAX
2.V
500
650
670
700
3V
215
280
320
360
3.3 V
210
270
305
345
4.5 V
160
210
240
270
6V
150
195
220
250
2.V
4
18
22
24
3V
2
12
14
16
3.3 V
2
12
14
16
4.5 V
2
8
12
16
6V
3
9
13
18
±0.1
±0.1
±1
±0.1
±0.5
±1
6V
UNIT
Ω
Ω
µA
µA
A
6V
6V
±0.2
±2
±4
±0.1
±0.5
±1
µA
2
5
10
µA
3.5
10
10
10
pF
6V
CIS
Common
terminal capacitance
Switch off
22
40
40
40
pF
COS
Switch terminal capacitance
Switch off
6.7
15
15
15
pF
injection-current coupling specifications, TA = −40°C to 125°C (see Figure 1)
PARAMETER
VCC
3.3 V
5V
3.3 V
V∆out
5V
Maximum shift of output voltage of enabled analog channel
3.3 V
5V
3.3 V
5V
TEST CONDITIONS
II‡ ≤ 1 mA,
RS ≤ 3.9 kΩ
II‡ ≤ 10 mA,
II‡ ≤ 1 mA,
RS ≤ 20 kΩ
II‡ ≤ 10 mA,
† Typical values are measured at TA = 25°C.
‡ II = total current injected into all disabled channels.
4
POST OFFICE BOX 655303
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TYP†
MAX
0.05
1
0.1
1
0.345
5
0.067
5
0.05
2
0.11
2
0.05
20
0.024
20
UNIT
mV
SCLS573 − MARCH 2004
switching characteristics over recommended operating free-air temperature range,
VCC = 2 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
−40 TO 85°C
−40 TO 125°C
MIN
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
COM or Yn
Yn or COM
14.5
19.5
33
12
34
11
35
ns
tPLH
tPHL
Propagation
delay time
Channel Select
COM or Yn
19.6
24.5
38
15.4
40
13.8
42
ns
tPZH
tPZL
Enable
delay time
INH
COM or Yn
19.4
23.6
47.5
15.8
52.5
14.5
57.5
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
39.5
48.4
100
39.3
105
39
115
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN
TYP
MAX
−40 TO 85°C
−40 TO 125°C
MIN
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
COM or Yn
Yn or COM
8.6
12
16.5
6.5
18
5.8
19.5
ns
tPLH
tPHL
Propagation
delay time
Channel Select
COM or Yn
12.4
14.6
20
9.3
21.5
8.2
23
ns
tPZH
tPZL
Enable
delay time
INH
COM or Yn
12.1
13.8
45
9.2
50
8.5
55
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
35.2
44.5
90
35.5
100
35
110
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
−40 TO 85°C
−40 TO 125°C
MIN
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
COM or Yn
Yn or COM
7.9
11
15
5.8
16.5
5
18.5
ns
tPLH
tPHL
Propagation
delay time
Channel Select
COM or Yn
11.4
13.5
17.5
8.5
19
7.5
22
ns
tPZH
tPZL
Enable
delay time
INH
COM or Yn
11.2
12.7
42.5
8.4
47.5
7.4
52.5
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
34.6
43.9
85
34.6
95
34.5
105
ns
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5
SCLS573 − MARCH 2004
switching characteristics over recommended operating free-air temperature range,
VCC = 4.5 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
−40 TO 85°C
−40 TO 125°C
MIN
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
COM or Yn
Yn or COM
6.3
8.6
11.6
4.6
12.5
4.5
13.5
ns
tPLH
tPHL
Propagation
delay time
Channel Select
COM or Yn
9.3
11
14
6.5
15
5.6
17
ns
tPZH
tPZL
Enable
delay time
INH
COM or Yn
8
9.9
40
5.3
45
4.4
50
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
28.5
41.4
80
28.2
90
28
100
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 6 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN
TYP
MAX
−40 TO 85°C
−40 TO 125°C
MIN
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
COM or Yn
Yn or COM
5.5
8
10.2
4.1
11
3.6
12
ns
tPLH
tPHL
Propagation
delay time
Channel Select
COM or Yn
7.4
9.5
12.6
4.7
14.5
3.8
16.5
ns
tPZH
tPZL
Enable
delay time
INH
COM or Yn
6.8
8.4
39
4.8
40
3.8
40
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
14.4
38
78
13.5
80
13
80
ns
operating characteristics, TA = 25°C (see Figure 15)
PARAMETER
Cpd
6
Power dissipation capacitance
VCC
3.3 V
5V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TEST CONDITIONS
TYP
UNIT
48
No load
60
pF
SCLS573 − MARCH 2004
APPLICATION INFORMATION
VCC = 5 V
IIO
VIN2 < VSS or VCC < VIN2
Any Disabled Channel
VSS < VIN1 < VCC
Enabled Channel
Vout = VI1 V ± V∆out
RS
Figure 1. Injection-Current Coupling Specification
5V
5V
5V
VCC
VCC
HC4052A
Sensor
Channel 1Y0
Channel 1Y1
Microcontroller
Channel 1Y2
Channel 1Y3
1-COM
A/D − Input 1
2-COM
A/D − Input 2
Channel 2Y0
Channel 2Y1
(8y Identical
Circuitry)
Channel 2Y2
Channel 2Y3
Figure 2. Actual Technology Requires 32 Passive Components and One Extra 6-V Regulator
to Suppress Injection Current Into a Standard HC4052 Multiplexer
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7
SCLS573 − MARCH 2004
APPLICATION INFORMATION
VCC
5V
VCC
HC4052A
Sensor
Channel 1Y0
Channel 1Y1
Microcontroller
Channel 1Y2
Channel 1Y3
1-COM
A/D − Input 1
2-COM
A/D − Input 2
Channel 2Y0
Channel 2Y1
(8x Identical
Circuitry)
Channel 2Y2
Channel 2Y3
Figure 3. Solution by Applying the HC4852 Multiplexer
Gate = VCC
(Disabled)
Common Analog Output
Vout > VCC
Disabled Analog Mux Input
VIn > VCC + 0.7 V
P+
P+
+
+
+
N − Substrate (on VCC potential)
Figure 4. Diagram of Bipolar Coupling Mechanism
(Appears if VIn Exceeds VCC, Driving Injection Current Into the Substrate)
8
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SCLS573 − MARCH 2004
PARAMETER MEASUREMENT INFORMATION
VCC
VINH = VIL
VCC
VI = VCC to GND
VO
(ON)
GND
r on +
VI – VO
W
IT
IS
V
VI − VO
Figure 5. On-State Resistance Test Circuit
VCC
16
GND
VCC
OFF
A
VCC
NC
VINH =VIH
OFF
COMMON O/I
6
8
Figure 6. Maximum Off-Channel Leakage Current, Any One Channel, Test Setup
VCC
VCC
VCC
16
GND
VCC
16
A
ON
ANALOG I/O
OFF
VCC
VINH =VIH
OFF
GND
A
COMMON O/I
6
OFF
VCC
NC
COMMON O/I
ANALOG I/O
VINH =VIL
8
6
8
Figure 7. Maximum Off-Channel Leakage Current,
Common Channel, Test Setup
POST OFFICE BOX 655303
Figure 8. Maximum On-Channel Leakage Current,
Channel to Channel, Test Setup
• DALLAS, TEXAS 75265
9
SCLS573 − MARCH 2004
PARAMETER MEASUREMENT INFORMATION
VCC
16
VCC
ON/OFF
ANALOG I/O
COMMON O/I
TEST POINT
OFF/ON
CL†
VCC
CHANNEL
SELECT
50%
GND
tPLH
6
tPHL
8
ANALOG
OUT
50%
CHANNEL SELECT
† Includes all probe and jig capacitance
Figure 9. Propagation Delays, Channel Select to
Analog Out
Figure 10. Propagation Delay, Channel Select to
Analog Out, Test Setup
VCC
16
ANALOG
I/O
COMMON O/I
TEST POINT
CL†
VCC
ANALOG
IN
50%
GND
tPLH
ANALOG
OUT
ON
tPHL
6
50%
8
† Includes all probe and jig capacitance
Figure 11. Propagation Delays, Analog In
to Analog Out
10
POST OFFICE BOX 655303
Figure 12. Propagation Delay, Analog In to Analog
Out, Test Setup
• DALLAS, TEXAS 75265
SCLS573 − MARCH 2004
PARAMETER MEASUREMENT INFORMATION
tf
tf
90%
50%
10%
ENABLE
tPZL
ANALOG
OUT
tPZH
ANALOG
OUT
2
50 %
ON/OFF
2
TEST POINT
CL
VOL
tPHZ
90%
VCC
10 kΩ
ANALOG
I/O
1
HIGH
IMPEDANCE
10%
16
VCC
GND
tPLZ
50 %
Position 1 when testing tPHZ and tPZH
Position 2 when testing tPLZ and tPZL
1
VCC
ENABLE
VOH
6
8
HIGH
IMPEDANCE
Figure 13. Propagation Delays, Enable to Analog
Out
Figure 14. Propagation Delay, Enable to Analog
Out, Test Setup
VCC
A
16
VCC
ON/OFF
COMMON O/I
NC
ANALOG I/O
OFF/ON
VCC
6
11
8
CHANNEL SELECT
Figure 15. Power-Dissipation Capacitance, Test
Setup
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11
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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