SN74AUC1G66 SINGLE BILATERAL ANALOG SWITCH SCES386F – MARCH 2002 – REVISED APRIL 2003 D D D D D D D D D D Available in the Texas Instruments NanoStar and NanoFree Packages Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Sub 1-V Operable Low Power Consumption, 10-µA Max ICC High On-Off Output Voltage Ratio High Degree of Linearity High Speed – Max 0.2 ns (VCC = 1.8 V, CL = 15 pF) Low On-State Impedance – Typically ≈9 Ω (VCC = 2.3 V) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DBV OR DCK PACKAGE (TOP VIEW) A B GND 1 5 VCC 4 C 2 3 YEA OR YZA PACKAGE (BOTTOM VIEW) GND B A 3 4 C 2 1 5 VCC description/ordering information This single analog switch is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC1G66 can handle both analog and digital signals. It permits signals with amplitudes of up to 3.6-V (peak) to be transmitted in either direction. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. ORDERING INFORMATION –40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING‡ NanoStar WCSP (DSBGA) – YEA Tape and reel SN74AUC1G66YEAR NanoFree WCSP (DSBGA) – YZA (Pb-free) Tape and reel SN74AUC1G66YZAR SOT (SOT-23) – DBV Tape and reel SN74AUC1G66DBVR U66_ SOT (SC-70) – DCK Tape and reel SN74AUC1G66DCKR U6_ _ _ _U6_ U6 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74AUC1G66 SINGLE BILATERAL ANALOG SWITCH SCES386F – MARCH 2002 – REVISED APRIL 2003 FUNCTION TABLE CONTROL INPUT (C) SWITCH L OFF H ON logic diagram (positive logic) 1 2 A B 4 C absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Switch I/O voltage range, VI/O (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Control input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA I/O port diode current, IIOK (VI/O < 0 or VI/O > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA On-state switch current, IT (VI/O = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AUC1G66 SINGLE BILATERAL ANALOG SWITCH SCES386F – MARCH 2002 – REVISED APRIL 2003 recommended operating conditions (see Note 4) VCC Supply voltage VIH High-level input voltage VCC = 0.8 V VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V MIN MAX 0.8 2.7 UNIT V VCC 0.65 × VCC V 1.7 VCC = 0.8 V VCC = 1.1 V to 1.95 V 0 0.35 × VCC VIL Low-level input voltage VI/O VI I/O port voltage 0 Control input voltage 0 ∆t/∆v Input transition rise or fall rate VCC = 2.3 V to 2.7 V V 0.7 VCC 3.6 V V 20 ns/V TA Operating free-air temperature –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP† MAX VI = VCC or GND, VC = VIH (see Figure 1) IS = 4 mA 1.65 V 10 20 IS = 8 mA 2.3 V 9 15 VI = VCC to GND, VC = VIH (see Figure 1) IS = 4 mA 1.65 V 32 80 IS = 8 mA 2.3 V 15 20 UNIT Ω ron On state switch resistance On-state ron(p) ( ) Peak on resistance IS(off) S( ff) Off state switch leakage current Off-state VI = VCC and VO = GND, or VI = GND and VO = VCC, VC = VIL (see Figure 2) 27V 2.7 IS(on) S( ) On state switch leakage current On-state VI = VCC or GND,, VC = VIH, VO = Open (see Figure 3) 27V 2.7 II Control input current VI = VCC or GND ICC Supply current VI = VCC or GND, Cic Control input capacitance 2.5 V 2 pF Cio(off) Switch input/output capacitance 2.5 V 3.5 pF Cio(on) Switch input/output capacitance 2.5 V 7 pF ±1 IO = 0 ±0.1† Ω µA ±1 ±0.1† µA 0 to 2.7 V ±5 µA 0.8 V to 2.7 V 10 µA † All typical values are at TA = 25°C. switching characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 4) FROM (INPUT) TO (OUTPUT) VCC = 0.8 V tpd‡ A or B B or A 0.9 ten C A or B 4.1 PARAMETER TYP VCC = 1.2 V ± 0.1 V MIN MAX VCC = 1.5 V ± 0.1 V MIN 0.3 0.5 2.6 MAX VCC = 1.8 V ± 0.15 V MIN TYP 0.2 0.5 1.7 VCC = 2.5 V ± 0.2 V MAX MIN 0.2 0.5 0.8 1.1 0.5 UNIT MAX 0.1 ns 1 ns tdis C 5 0.7 3.6 0.5 2.6 0.5 1.7 2.9 0.5 2.2 ns A or B ‡ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74AUC1G66 SINGLE BILATERAL ANALOG SWITCH SCES386F – MARCH 2002 – REVISED APRIL 2003 switching characteristics over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 4) FROM (INPUT) TO (OUTPUT) tpd† A or B B or A ten C A or B PARAMETER VCC = 1.8 V ± 0.15 V MIN TYP VCC = 2.5 V ± 0.2 V MAX MIN 0.3 0.5 1.4 2.3 0.8 UNIT MAX 0.3 ns 1.4 ns tdis C 0.5 1.7 2.9 0.5 1.5 ns A or B † The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AUC1G66 SINGLE BILATERAL ANALOG SWITCH SCES386F – MARCH 2002 – REVISED APRIL 2003 analog switch characteristics, TA = 25°C PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS CL = 50 pF, F, RL = 600 Ω, fin = sine wave (see Figure 5) Frequency q y response† (switch ON) A or B Crosstalk (control input to signal output) C CL = 50 pF, F, RL = 600 Ω, fin = 1 MHz (square wave) (see Figure 6) A or B CL = 50 pF, F, RL = 600 Ω, fin = 1 MHz (sine wave) (see Figure 7) Feed-through g attenuation‡ (switch OFF) A or B A or B CL = 50 pF, F, RL = 10 kΩ, fin = 1 kHz (sine wave) (see Figure 8) B or A A or B B or A 60 1.1 V 60 80 120 2.3 V 170 0.8 V >500 1.1 V >500 1.4 V >500 1.65 V >500 2.3 V >500 0.8 V 9 1.1 V 14 1.4 V 15 1.65 V 16 2.3 V 20 0.8 V –60 1.1 V –60 1.4 V –60 1.65 V –60 2.3 V –60 0.8 V –55 1.1 V –55 1.4 V –55 1.65 V –55 2.3 V –55 0.8 V 7.5 1.1 V 0.16 1.4 V 0.04 1.65 V 0.03 2.3 V 0.02 0.8 V 4.2 1.1 V 0.2 Sine wave distortion Sine-wave CL = 50 pF, F, RL = 10 kΩ, fin = 10 kHz (sine wave) (see Figure 8) 0.8 V 1.4 V B or A CL = 5 pF, F, RL = 50 Ω, fin = 1 MHz (sine wave) (see Figure 7) TYP 1.65 V B or A CL = 5 pF, F, RL = 50 Ω, fin = sine wave (see Figure 5) VCC 1.4 V 0.03 1.65 V 0.02 2.3 V 0.02 UNIT MHz mV dB % † Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB. ‡ Adjust fin voltage to obtain 0 dBm at input. operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 0.8 V TYP 3 POST OFFICE BOX 655303 VCC = 1.2 V TYP VCC = 1.5 V TYP 3 • DALLAS, TEXAS 75265 3 VCC = 1.8 V TYP 3 VCC = 2.5 V TYP 3 UNIT pF 5 SN74AUC1G66 SINGLE BILATERAL ANALOG SWITCH SCES386F – MARCH 2002 – REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION VCC VCC B or A A or B VI = VCC or GND VIH VO C VC (ON) GND IS r on V Figure 1. On-State Resistance Test Circuit VCC VCC A VIL B or A A or B C VC (OFF) GND Condition 1: VI = GND, VO = VCC Condition 2: VI = VCC, VO = GND Figure 2. Off-State Switch Leakage-Current Test Circuit 6 POST OFFICE BOX 655303 I S VI – VO VI + V *I V • DALLAS, TEXAS 75265 VO O W SN74AUC1G66 SINGLE BILATERAL ANALOG SWITCH SCES386F – MARCH 2002 – REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION VCC VCC VI = VCC or GND A VIH B or A A or B VO VO = Open C VC (ON) GND Figure 3. On-State Leakage-Current Test Circuit POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74AUC1G66 SINGLE BILATERAL ANALOG SWITCH SCES386F – MARCH 2002 – REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test CL (see Note A) VLOAD Open S1 GND RL LOAD CIRCUIT TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND INPUTS VCC 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V VI tr/tf VCC VCC VCC VCC VCC VCC VCC ≤2 ns ≤2 ns ≤2 ns ≤2 ns ≤2 ns ≤2 ns ≤2 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 2 × VCC 2 × VCC 2 × VCC 2 × VCC 2 × VCC 2 × VCC 2 × VCC 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF 2 kΩ 2 kΩ 2 kΩ 2 kΩ 2 kΩ 1 kΩ 500 Ω 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.15 V 0.15 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM VM 0V tPZL tPLZ VLOAD/2 VM tPZH VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH – V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 4. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AUC1G66 SINGLE BILATERAL ANALOG SWITCH SCES386F – MARCH 2002 – REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION VCC VCC 0.1 µF 50 Ω fin VIH B or A A or B C VC VO RL (ON) GND CL VCC/2 RL/CL: 600 Ω / 50 pF RL/CL: 50 Ω / 5 pF Figure 5. Frequency Response (Switch ON) VCC VCC Rin 600 Ω VCC/2 A or B B or A VO RL 600 Ω C VC GND 50 Ω CL 50 pF VCC/2 Figure 6. Crosstalk (Control Input – Switch Output) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74AUC1G66 SINGLE BILATERAL ANALOG SWITCH SCES386F – MARCH 2002 – REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION VCC VCC 0.1 µF RL 50 Ω fin B or A A or B VO C VC VIL CL RL (OFF) GND VCC/2 VCC/2 RL/CL: 600 Ω / 50 pF RL/CL: 50 Ω / 5 pF Figure 7. Feed Through, Switch Off VCC VCC 10 µF fin 600 Ω VIH VO RL 10 kΩ C VC (ON) GND VCC = 0.8 V, VI = __ VP-P VCC = 1.1 V, VI = __ VP-P VCC = 1.4 V, VI = __ VP-P VCC = 1.65 V, VI = 1.4 VP-P VCC = 2.3 V, VI = 2.5 VP-P Figure 8. Sine-Wave Distortion 10 10 µF B or A A or B POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC/2 CL 50 pF MECHANICAL DATA MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002 DCK (R-PDSO-G5) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 5 0,10 M 4 1,40 1,10 1 0,13 NOM 2,40 1,80 3 Gage Plane 2,15 1,85 0,15 0°–8° 0,46 0,26 Seating Plane 1,10 0,80 0,10 0,00 0,10 4093553-2/D 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. 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