TI TPS72013YZUT

TPS720xx
www.ti.com ............................................................................................................................................................. SBVS100A – JUNE 2008 – REVISED JUNE 2008
350mA, Ultra-Low VIN, RF Low-Dropout Linear Regulator with Bias Pin
FEATURES
DESCRIPTION
1
• 350mA High-Performance LDO
• Low Quiescent Current: 38µA
• Excellent Load Transient Response:
±15mV for ILOAD = 0mA to 350mA in 1µs
• Excellent Line Transient Response:
ΔVOUT = ±2mV for ΔVBIAS = ±600mV in 1µs
ΔVOUT = ±200µV for ΔVIN = ±400mV in 1µs
• Low Noise: 48µVRMS (10Hz to 100kHz)
• 80dB VIN PSRR (10Hz to 10kHz)
• 70dB VBIAS PSRR (10Hz to 10kHz)
• Fast Start-Up Time: 140µs
• Inrush Current-Controlled Soft-Start with
Monotonic VOUT Rise and VIN Current Limited
to 100mA + ILOAD
• Over-Current and Thermal Protection
• Low Dropout: 110mV at ILOAD = 350mA
• Stable with 2.2µF Output Capacitor
• Available in 1,33mm x 0,96mm 5-Pin WCSP
The TPS720xx family of dual rail, low-dropout linear
regulators (LDOs) offers outstanding ac performance
(PSRR, load and line transient response), while
consuming a very low quiescent current of 38µA.
2
The VBIAS rail that powers the control circuit of the
LDO draws very low current (on the order of the
quiescent current of the LDO) and can be connected
to any power supply that is equal to or greater than
1.4V above the output voltage. The main power path
is through VIN, which can be a lower voltage than
VBIAS; it can be as low as VOUT + VDO, increasing the
efficiency of the solution in many power-sensitive
applications. For example, VIN can be an output of a
high-efficiency, dc-dc step-down regulator.
The TPS720xx supports a novel feature in which the
output of the LDO regulates under light loads when
the IN pin is left floating. The light-load drive current
is sourced from VBIAS under this condition. This
feature is particularly useful in power-saving
applications where the dc/dc converter connected to
the IN pin is disabled but the LDO is still required to
regulate the voltage to a light load.
APPLICATIONS
•
•
•
•
The TPS720xx is stable with ceramic capacitors and
uses an advanced BICMOS fabrication process that
yields a dropout of 110mV at a 350mA output load.
The TPS720xx has the unique feature of providing a
monotonic VOUT rise (overshoot limited to ±3%) with
VIN inrush current limited to 100mA + ILOAD with an
output capacitor of 2.2µF.
Digital Cameras
Cellular Camera Phones
Wireless LAN
Handheld Products
The TPS720xx uses a precision voltage reference
and feedback loop to achieve overall accuracy of 2%
over load, line, process, and temperature extremes.
An ultra-small wafer chip-scale package (WCSP)
makes the TPS720xx ideal for handheld applications.
This family of devices is fully specified over the
temperature range of TJ = –40°C to +125°C.
TPS720xx
YZU PACKAGE
WCSP-5
(TOP VIEW)
VBATT
BIAS
Standalone
dc/dc
Converter
or PMU
1.8V
IN
OUT
1.3V
VCORE
TPS720xx
EN
GND
2.2mF
Ceramic
BIAS
B2
GND
A3
VEN
C1
C3
EN
OUT
A1
IN
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TPS720xx
SBVS100A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
VOUT (2)
PRODUCT
TPS720xxyyyz
(1)
(2)
XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V).
YYY is the package designator.
Z is tape and reel quantity (R = 3000, T = 250).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Output voltages from 0.9V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS (1)
At TJ = –40°C to +125°C (unless otherwise noted). All voltages are with respect to GND.
PARAMETER
TPS720xx
UNIT
–0.3 to +5.0
V
+5.5
V
Bias voltage range, VBIAS
–0.3 to +6.0
V
Enable voltage range, VEN
–0.3 to +6.0
V
Output voltage range, VOUT
–0.3 to +5.0
V
Input voltage range (steady-state), VIN
(2)
Peak transient input voltage, VIN_PEAK (3)
Peak output current, IOUT
Internally limited
Output short-circuit duration
Indefinite
Total continuous power dissipation, PDISS
See Dissipation Ratings Table
Human body model (HBM)
2000
V
Charged device model (CDM)
500
V
ESD rating
100
V
Operating junction temperature range, TJ
Machine model (MM)
–55 to +125
°C
Storage temperature range, TSTG
–55 to +150
°C
(1)
(2)
(3)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
To ensure proper operation of the device it is necessary that VIN ≤ VBIAS under all conditions.
For durations no longer than 1ms each, for a total of no more than 1000 occurrences over the lifetime of the device.
DISSIPATION RATINGS
BOARD
High-K
(1)
2
(1)
PACKAGE
RθJC
RθJA
DERATING FACTOR
ABOVE TA = +25°C
TA < +25°C
TA = +70°C
TA = +85°C
YZU
51°C/W
248°C/W
4mW/°C
403mW
222mW
160mW
The JEDEC high-K (2s2p) board used to derive this data was a 3- × 3-inch, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on top and bottom of the board.
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Copyright © 2008, Texas Instruments Incorporated
TPS720xx
www.ti.com ............................................................................................................................................................. SBVS100A – JUNE 2008 – REVISED JUNE 2008
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4V) or 2.5V (whichever is greater); VIN ≥ VOUT +
0.5V, IOUT = 1mA, VEN = 1.1V, COUT = 2.2µF, unless otherwise noted. Typical values are at TJ = +25°C.
PARAMETER
TEST CONDITIONS
TYP
MAX
UNIT
Input voltage range
1.1 (1)
4.5
V
VBIAS
Bias voltage range
2.5
5.5
V
Output voltage range (3)
0.9
3.6
V
VOUT (2)
ΔVOUT/ΔVIN
Output
accuracy
Nominal
TJ = +25°C
–3.0
+3.0
mV
Over VBIAS, VIN, IOUT,
TJ = –40°C to +125°C
VOUT + 1.4V ≤ VBIAS ≤ 5.5V,
VOUT + 0.5V ≤ VIN ≤ 4.5V,
0mA ≤ IOUT ≤ 350mA
–2.0
+2.0
%
VIN floating
VOUT + 1.4V ≤ VBIAS ≤ 5.5V,
0µA ≤ IOUT ≤ 500µA
VIN line regulation
ΔVOUT/ΔVBIAS VBIAS line regulation
ΔVOUT/ΔIOUT
VDO_IN
VDO_BIAS
ICL
%
VIN = (VOUT + 0.5V) to 4.5V, IOUT = 1mA
16
µV/V
VBIAS = (VOUT + 1.4V) or 2.5V (whichever is
greater) to 5.5V, IOUT = 1mA
16
µV/V
µV
ΔVIN = 400mV, tRISE = tFALL = 1µs
±200
VBIAS line transient
ΔVBIAS = 600mV, tRISE = tFALL = 1µs
±0.8
mV
Load regulation
0mA ≤ IOUT ≤ 350mA (no load to full load)
–15
µV/mA
Load transient
0mA ≤ IOUT ≤ 350mA, tRISE = tFALL = 1µs
±15
mV
VIN dropout voltage (4)
VIN = VOUT(NOM) – 0.1V,
(VBIAS – VOUT(NOM)) = 1.4V,
IOUT = 350mA
110
200
mV
VBIAS dropout voltage (5)
VIN = VOUT(NOM) + 0.3V, IOUT = 350mA
1.09
1.4
V
Output current limit
VOUT = 0.9 × VOUT(NOM)
525
800
mA
IGND
Ground pin current
ISHDN
Shutdown current (IGND)
VBIAS power-supply rejection ratio
420
µA
IOUT = 100µA
38
IOUT = 0mA to 350mA
54
80
µA
VEN ≤ 0.4V, TJ = -40°C to +85°C
0.5
2
µA
VIN – VOUT ≥ 0.5V,
VBIAS = VOUT + 1.4V,
IOUT = 350mA
PSRR
VIN – VOUT ≥ 0.5V,
VBIAS = VOUT + 1.4V,
IOUT = 350mA
f = 10Hz
85
dB
f = 100Hz
85
dB
f = 1kHz
85
dB
f = 10kHz
80
dB
f = 100kHz
70
dB
f = 1MHz
50
dB
f = 10Hz
80
dB
f = 100Hz
80
dB
f = 1kHz
75
dB
f = 10kHz
65
dB
f = 100kHz
55
dB
f = 1MHz
35
dB
48
µVRMS
VN
Output noise voltage
BW = 10Hz to 100kHz, VBIAS ≥ 2.5V,
VIN = VOUT + 0.5V
IVIN_INRUSH
Inrush current on VIN
VBIAS = (VOUT +1.4V) or 2.5V (whichever is
greater), VIN = VOUT + 0.5V
Startup time
VOUT = 95% VOUT(NOM), IOUT = 350mA,
COUT = 2.2µF
tSTR
±1.0
VIN line transient
VIN power-supply rejection ratio
(1)
(2)
(3)
(4)
(5)
MIN
VIN
VEN(HI)
Enable pin high (enabled)
1.1
VEN(LO)
Enable pin low (disabled)
0
100 +
ILOAD
mA
140
µs
V
0.4
V
Performance specifications are ensured up to a minimum VIN = VOUT + 0.5V.
Minimum VBIAS = (VOUT + 1.4V) or 2.5V (whichever is greater) and VIN= VOUT + 0.5V.
VO nominal value is factory programmable through the onchip EEPROM.
Measured for devices with VOUT(NOM) ≥ 1.2V.
VBIAS – VOUT with VOUT = VOUT(NOM) – 0.1V. Measured for devices with VOUT(NOM) ≥ 1.8V.
Copyright © 2008, Texas Instruments Incorporated
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TPS720xx
SBVS100A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4V) or 2.5V (whichever is greater); VIN ≥ VOUT +
0.5V, IOUT = 1mA, VEN = 1.1V, COUT = 2.2µF, unless otherwise noted. Typical values are at TJ = +25°C.
PARAMETER
IEN
UVLO
4
TEST CONDITIONS
Enable pin current
VEN = 5.5V, VIN = 4.5V, VBIAS = 5.5V
Undervoltage lockout
VBIAS rising
Hysteresis
VBIAS falling
TSD
Thermal shutdown temperature
TJ
Operating junction temperature
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MIN
TYP
MAX
1.0
2.41
2.45
2.49
UNIT
µA
V
150
mV
Shutdown, temperature increasing
+160
°C
Reset, temperature decreasing
+140
–40
°C
+125
°C
Copyright © 2008, Texas Instruments Incorporated
TPS720xx
www.ti.com ............................................................................................................................................................. SBVS100A – JUNE 2008 – REVISED JUNE 2008
DEVICE INFORMATION
IN
OUT
Current
Limit
Thermal
Shutdown
BIAS
UVLO
EN
Bandgap
Functional Block Diagram
PIN CONFIGURATION
YZU PACKAGE
WCSP-5
(TOP VIEW)
TPS720xx
C3
C1
BIAS
EN
B2
GND
A3
OUT
A1
IN
PIN DESCRIPTIONS
TPS720xx
NAME
YZU
DESCRIPTION
IN
A1
Input pin. This pin can be a maximum of 4.5V; VIN must not exceed VBIAS. Bypass this input with a ceramic
capacitor to ground.
OUT
A3
Output pin. A 2.2µF ceramic capacitor is connected from this pin to ground, for stability and to provide load
transients.
GND
B2
Ground pin.
BIAS
C1
Bias supply pin. It is recommended that this input be bypassed with a ceramic capacitor to ground for better
transient performance.
EN
C3
Enable pin. A logic high signal on this pin turns the device on and regulates the voltage from IN to OUT. A logic low
on this pin turns off the device.
Copyright © 2008, Texas Instruments Incorporated
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TPS720xx
SBVS100A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4V) or 2.5V (whichever is greater);
VIN = VOUT + 0.5V, IOUT = 1mA, VEN = 1.1V, COUT = 2.2µF, unless otherwise noted. Typical values are at TJ = +25°C.
VIN LINE REGULATION
IOUT = 0mA (TPS72013YZU)
1.40
1.40
1.38
1.38
1.36
1.36
+85°C
-10°C
+25°C
1.34
-40°C
1.32
1.30
1.28
+105°C
1.26
1.32
1.30
1.28
+105°C
+125°C
1.24
1.22
1.22
1.20
1.20
2.5
3.0
3.5
4.5
4.0
2.5
3.0
3.5
VIN (V)
Figure 2.
VBIAS LINE REGULATION
IOUT = 0mA (TPS72013YZU)
VBIAS LINE REGULATION
IOUT = 350mA (TPS72013YZU)
1.40
1.40
1.38
1.38
1.36
-40°C
1.32
1.30
1.28
+105°C
1.26
1.32
1.30
1.28
+105°C
+125°C
1.24
1.22
1.22
1.20
1.20
2.5
3.0
3.5
4.5
4.0
5.5
5.0
2.5
3.5
4.5
4.0
VBIAS (V)
Figure 3.
Figure 4.
LOAD REGULATION UNDER LIGHT LOADS
(TPS72013YZU)
LOAD REGULATION
(TPS72013YZU)
1.40
1.40
1.38
1.38
+85°C
-10°C
+25°C
1.34
3.0
VBIAS (V)
1.36
1.36
-40°C
1.32
1.30
1.28
+105°C
1.26
5.0
5.5
-40°C
1.32
1.30
1.28
+105°C
1.26
+125°C
1.24
+85°C
+25°C -10°C
1.34
VOUT (V)
VOUT (V)
-40°C
1.26
+125°C
1.24
+85°C
-10°C
+25°C
1.34
VOUT (V)
VOUT (V)
+85°C
-10°C
+25°C
1.34
4.5
4.0
VIN (V)
Figure 1.
1.36
+125°C
1.24
1.22
1.22
1.20
1.20
0
6
-40°C
1.26
+125°C
1.24
+85°C
-10°C
+25°C
1.34
VOUT (V)
VOUT (V)
VIN LINE REGULATION
IOUT = 350mA (TPS72012YZU)
1
2
3
4
5
6
7
8
9
10
0
50
100
150
200
IOUT (mA)
IOUT (mA)
Figure 5.
Figure 6.
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250
300
350
Copyright © 2008, Texas Instruments Incorporated
TPS720xx
www.ti.com ............................................................................................................................................................. SBVS100A – JUNE 2008 – REVISED JUNE 2008
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4V) or 2.5V (whichever is greater);
VIN = VOUT + 0.5V, IOUT = 1mA, VEN = 1.1V, COUT = 2.2µF, unless otherwise noted. Typical values are at TJ = +25°C.
LOAD REGULATION WITH VIN FLOATING
(TPS72013YZU)
LOAD REGULATION WITH VIN FLOATING
(TPS72013YZU)
1.40
1.40
TJ = +25°C
1.38
1.36
1.36
1.34
VBIAS = 3.0V
1.32
VBIAS = 4.0V
VBIAS = 5.0V
VOUT (mA)
VOUT (mA)
1.34
1.30
1.28
TJ = +125°C
1.32
1.30
TJ = -40°C
1.28
TJ = +25°C
1.26
1.26
TJ = 0°C
1.24
1.24
VBIAS = 2.7V
1.22
VBIAS = 3.5V
VBIAS = 4.5V
0
0.5
1.0
1.5
2.0
2.5
TJ = +85°C
1.22
VBIAS = 5.5V
1.20
3.0
TJ = +105°C
1.20
3.5
4.0
0
0.1
0.2
0.3
0.4
0.6
0.7
0.8
IOUT (mA)
Figure 7.
Figure 8.
VIN DROPOUT VOLTAGE
vs OUTPUT CURRENT (TPS72013YZU)
VBIAS DROPOUT VOLTAGE
vs TEMPERATURE (TPS72033YZU)
0.9
1.0
1.15
+125°C
+105°C
120
100
80
60
-10°C -40°C
+25°C
40
VDO_BIAS = VBIAS - VOUT (V)
1.14
140
+85°C
20
1.13
1.12
1.11
1.10
1.09
1.08
1.07
1.06
VOUT = VOUT(NOM) - 0.1
IOUT = 350mA
1.05
1.04
0
0
50
100
150
200
250
350
300
-40 -25 -10
5
20
35
50
65
80
95
110 125
TJ (°C)
IOUT (mA)
Figure 9.
Figure 10.
OUTPUT VOLTAGE
vs TEMPERATURE (TPS72013YZU)
GROUND PIN CURRENT
vs VBIAS INPUT VOLTAGE (TPS72013YZU)
1.345
50
45
1.325
IOUT = 1mA
40
IOUT = 0mA
35
IOUT = 1mA
1.305
IGND (mA)
VOUT (V)
0.5
IOUT (mA)
160
VDO_IN (mV)
VBIAS = 2.7V
1.38
1.285
IOUT = 350mA
30
25
20
+125°C +105°C
+85°C
+25°C
-10°C
-40°C
15
1.265
10
5
0
1.245
-40 -25 -10
5
20
35
50
TJ (°C)
Figure 11.
Copyright © 2008, Texas Instruments Incorporated
65
80
95
110 125
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VBIAS (V)
Figure 12.
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TPS720xx
SBVS100A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4V) or 2.5V (whichever is greater);
VIN = VOUT + 0.5V, IOUT = 1mA, VEN = 1.1V, COUT = 2.2µF, unless otherwise noted. Typical values are at TJ = +25°C.
GROUND PIN CURRENT
vs OUTPUT CURRENT (TPS72013YZU)
GROUND PIN CURRENT
vs TEMPERATURE (TPS72013YZU)
60
70
IOUT = 350mA
60
+125°C +105°C
+85°C
50
+25°C
50
IGND (mA)
IGND (mA)
40
40
30
20
-40°C
-10°C
20
30
10
10
0
0
0
50
100
150
200
250
350
300
-40 -25 -10
5
20
35
50
65
80
95
110 125
IOUT (mA)
TJ (°C)
Figure 13.
Figure 14.
SHUTDOWN CURRENT
vs VBIAS INPUT VOLTAGE (TPS72013YZU)
CURRENT LIMIT
vs VBIAS INPUT VOLTAGE (TPS72013YZU)
3.0
675
2.5
650
-10°C
+25°C
-40°C
+25°C
-10°C
-40°C
+85°C
1.5
+125°C
625
ICL (V)
ISHDN (mA)
2.0
600
1.0
+85°C
+105°C
+105°C
+125°C
575
0.5
0
550
2.5
3.0
3.5
4.5
4.0
5.0
5.5
2.5
3.0
3.5
VBIAS (V)
4.5
4.0
5.0
5.5
VBIAS (V)
Figure 15.
Figure 16.
CURRENT LIMIT
vs VIN INPUT VOLTAGE (TPS72013YZU)
VIN POWER-SUPPLY RIPPLE REJECTION
vs FREQUENCY (TPS72015YZU)
675
120
-10°C
+25°C
-40°C
100
650
(VIN - VOUT) = 0.5V
(VBIAS - VOUT) = 1.4V
IOUT = 0mA
PSRR (dB)
ICL (mA)
80
625
600
+85°C
+105°C
IOUT = 350mA
40
+125°C
575
20
550
0
2.5
3.0
3.5
VIN (V)
Figure 17.
8
IOUT = 50mA
60
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4.0
4.5
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Figure 18.
Copyright © 2008, Texas Instruments Incorporated
TPS720xx
www.ti.com ............................................................................................................................................................. SBVS100A – JUNE 2008 – REVISED JUNE 2008
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4V) or 2.5V (whichever is greater);
VIN = VOUT + 0.5V, IOUT = 1mA, VEN = 1.1V, COUT = 2.2µF, unless otherwise noted. Typical values are at TJ = +25°C.
VIN POWER-SUPPLY RIPPLE REJECTION
vs FREQUENCY (TPS72015YZU)
VBIAS POWER-SUPPLY RIPPLE REJECTION
vs FREQUENCY (TPS72015YZU)
100
100
IOUT = 350mA
(VIN - VOUT) = 350mV
80
80
PSRR (dB)
PSRR (dB)
IOUT = 1mA
60
(VIN - VOUT) = 300mV
40
60
40
(VIN - VOUT) = 250mV
IOUT = 350mA
20
20
(VIN - VOUT) = 0.5V
(VBIAS - VOUT) = 1.4V
0
0
Output Spectral Noise Density (mV/ÖHz)
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 19.
Figure 20.
OUTPUT SPECTRAL NOISE DENSITY
vs FREQUENCY (TPS72015YZU)
VIN INRUSH CURRENT
VIN = 1.8V, VOUT = 1.3V, VBIAS = 2.7V, IOUT = 0mA
10
VOUT = 1.3V
IIN = 110mA
1
IIN
50mA/div
0.1
EN
500mV/div
200mV/div
VOUT
0.01
100
1k
10k
20ms/div
100k
Frequency (Hz)
Figure 21.
VIN
Figure 22.
VIN LINE TRANSIENT RESPONSE
VIN = 1.6V to 2.0V, VOUT = 1.3V, VBIAS = 2.7V,
VIN SLEW RATE = 1V/µs, IOUT = 350mA
VIN INRUSH CURRENT
= 1.8V, VOUT = 1.3V, VBIAS = 2.7V, IOUT = 350mA
VOUT = 1.3V
IIN = 400mA
1mV/div
VOUT
IIN
200mA/div
2.0V
EN
500mV/div
200mV/div
200mV/div
VIN 1.6V
VOUT
20ms/div
100ms/div
Figure 23.
Figure 24.
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TPS720xx
SBVS100A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4V) or 2.5V (whichever is greater);
VIN = VOUT + 0.5V, IOUT = 1mA, VEN = 1.1V, COUT = 2.2µF, unless otherwise noted. Typical values are at TJ = +25°C.
VBIAS LINE TRANSIENT RESPONSE
VIN = 1.8V, VOUT = 1.3V, VBIAS = 2.7V to 3.3V,
VBIAS SLEW RATE = 600m/µs, IOUT = 350mA
1mV/div
VOUT
LOAD TRANSIENT RESPONSE
VIN = 1.8V, VOUT = 1.3V, VBIAS = 2.7V, tRISE = 1µs
10mV/div
VOUT
3.3V
200mV/div
10
300mA
VBIAS 2.7V
100mA/div
IOUT 0mA
100ms/div
100ms/div
Figure 25.
Figure 26.
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TPS720xx
www.ti.com ............................................................................................................................................................. SBVS100A – JUNE 2008 – REVISED JUNE 2008
APPLICATION INFORMATION
The TPS720xx belongs to a family of new generation
LDO regulators that use innovative circuitry to
achieve ultra-wide bandwidth and high loop gain,
resulting in extremely high PSRR (up to 1MHz) at
very low headroom (VIN – VOUT). The implementation
of the BIAS pin on the TPS720 vastly improves
efficiency of low VOUT applications by allowing the use
of a preregulated, low-voltage input supply. The
TPS720xx supports a novel feature in which the
output of the LDO regulates under light loads
(<500µA) when the IN pin is left floating. The
light-load drive current is sourced from VBIAS under
this condition. This feature is particularly useful in
power-saving applications where the dc/dc converter
connected to the IN pin is disabled but the LDO is still
required to regulate the voltage to a light load. These
features, combined with low noise, low ground pin
current, and ultra-small packaging, make this device
ideal for portable applications. This family of
regulators offers sub-bandgap output voltages,
current limit and thermal protection, and is fully
specified from –40°C to +125°C.
BOARD LAYOUT RECOMMENDATIONS TO
IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for VIN and VOUT, with the ground plane connected
only at the GND pin of the device. In addition, the
ground connection for the output capacitor should be
connected directly to the GND pin of the device. High
equivalent series resistance (ESR) capacitors may
degrade PSRR. The BIAS pin draws very little current
and can be routed as a signal (make sure to shield it
from high-frequency coupling).
INTERNAL CURRENT LIMIT
The TPS720xx internal current limits help protect the
regulator during fault conditions. During current limit,
the output sources a fixed amount of current that is
largely independent of output voltage. For reliable
operation, the device should not be operated in a
current limit state for extended periods of time.
The NMOS pass element in the TPS720xx has a
built-in body diode that conducts current when the
voltage at OUT exceeds the voltage at IN. This
current is not limited, so if extended reverse voltage
operation is anticipated, external limiting to 5% of
rated output current may be appropriate.
INRUSH CURRENT LIMIT
The TPS720xx family of LDO regulators implement a
novel inrush current-limit circuit architecture: the
current drawn through the IN pin is limited to a finite
value. This IINRUSHLIMIT charges the output to its final
voltage. All the current drawn through VIN goes to
charge the output capacitance when the load is
disconnected. The following equation shows the
inrush current limit performed by the circuit:
IINRUSHLIMIT(A) = COUT(µF) × 0.0454545(V/µs) +
ILOAD(A)
(1)
Assuming a COUT of 2.2µF with the load disconnected
(that is, ILOAD = 0) the IINRUSHLIMIT is calculated to be
100mA. The inrush current charges the LDO output
capacitor. If the output of the LDO regulates to 1.3V,
then the LDO charges the output capacitor to the final
output value in approximately 28.6µs.
Another consideration is when a load is connected to
the output of an LDO. The connected load tries to
steer a portion of the current away from VOUT. The
TPS720xx inrush current-limit circuit employs a new
technique that supplies not only the IINRUSHLIMIT, but
also the additional current needed by the load. If
ILOAD = 350mA, then the IINRUSHLIMIT calculates to be
approximately 450mA (from Equation 1).
SHUTDOWN
The enable pin (EN) is active high and is compatible
with standard and low voltage, TTL-CMOS levels.
When shutdown capability is not required, EN can be
connected to the IN pin.
DROPOUT VOLTAGE
The TPS720xx uses a NMOS pass transistor to
achieve low dropout. When (VIN – VOUT) is less than
the dropout voltage (VDO), the NMOS pass device is
in the linear region of operation and the
input-to-output resistance is the RDS(ON) of the NMOS
pass element. VDO approximately scales with output
current because the NMOS device behaves as a
resistor in dropout.
As with any linear regulator, PSRR and transient
response are degraded as (VIN – VOUT) approaches
dropout. This effect is shown in Figure 19 in the
Typical Characteristics section.
TRANSIENT RESPONSE
As with any regulator, increasing the size of the
output capacitor reduces over/undershoot magnitude
but increases duration of the transient response.
Copyright © 2008, Texas Instruments Incorporated
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TPS720xx
SBVS100A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com
UNDERVOLTAGE LOCK-OUT (UVLO)
The TPS720xx uses an undervoltage lock-out circuit
to keep the output shut off until the internal circuitry is
operating properly. The UVLO circuit has a deglitch
feature so that it typically ignores undershoot
transients on the input if they are less than 50µs
duration.
THERMAL INFORMATION
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C, the
output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage as a result of
overheating.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
condition of the particular application. This
configuration produces a worst-case junction
temperature of +125°C at the highest expected
ambient temperature and worst-case load.
12
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The internal protection circuitry of the TPS720xx has
been designed to protect against overload conditions.
It was not intended to replace proper heatsinking.
Continuously running the TPS720xx into thermal
shutdown degrades device reliability.
POWER DISSIPATION
The ability to remove heat from the die is different for
each
package
type,
presenting
different
considerations in the printed circuit board (PCB)
layout. The PCB area around the device that is free
of other components moves the heat from the device
to the ambient air. Performance data for JEDEC lowand high-K boards are given in the Dissipation
Ratings table. Using heavier copper increases the
effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating
layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT), as
shown in Equation 2:
PD = (VIN – VOUT) × IOUT
(2)
PACKAGE MOUNTING
Solder pad footprint recommendations for the
TPS720xx are available from the Texas Instruments
web site at www.ti.com.
Copyright © 2008, Texas Instruments Incorporated
TPS720xx
www.ti.com ............................................................................................................................................................. SBVS100A – JUNE 2008 – REVISED JUNE 2008
0,994
0,934
1,362
1,302
NOTES:
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.
Figure 27. YZU Wafer Chip-Scale Package Dimensions (in mm)
Copyright © 2008, Texas Instruments Incorporated
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TPS720xx
SBVS100A – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com
Revision History
Changes from Revision original (June 2008) to Revision A .......................................................................................... Page
•
•
•
•
14
Changed conditions for Electrical Characteristics table......................................................................................................... 3
Changed IGND, ISHDN, and IEN test conditions for Electrical Characteristics table ................................................................... 3
Changed footnotes 4 and 5 Electrical Characteristics table .................................................................................................. 3
Changed first paragraph of Application Information section................................................................................................ 11
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Copyright © 2008, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS72013YZUR
ACTIVE
DSBGA
YZU
5
3000 Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
TPS72013YZUT
ACTIVE
DSBGA
YZU
5
250
Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
TPS72015YZUR
ACTIVE
DSBGA
YZU
5
3000 Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
TPS72015YZUT
ACTIVE
DSBGA
YZU
5
250
Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
TPS72017YZUT
PREVIEW
DSBGA
YZU
5
250
TBD
Call TI
Call TI
TPS72018YZUR
PREVIEW
DSBGA
YZU
5
3000
TBD
Call TI
Call TI
TPS72018YZUT
PREVIEW
DSBGA
YZU
5
250
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
TPS72013YZUR
DSBGA
YZU
5
3000
178.0
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.4
1.09
1.42
0.81
4.0
8.0
Q1
TPS72013YZUT
DSBGA
YZU
5
250
178.0
8.4
1.09
1.42
0.81
4.0
8.0
Q1
TPS72015YZUR
DSBGA
YZU
5
3000
178.0
8.4
1.09
1.42
0.81
4.0
8.0
Q1
TPS72015YZUT
DSBGA
YZU
5
250
178.0
8.4
1.09
1.42
0.81
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS72013YZUR
DSBGA
YZU
5
3000
217.0
193.0
35.0
TPS72013YZUT
DSBGA
YZU
5
250
217.0
193.0
35.0
TPS72015YZUR
DSBGA
YZU
5
3000
217.0
193.0
35.0
TPS72015YZUT
DSBGA
YZU
5
250
217.0
193.0
35.0
Pack Materials-Page 2
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