ADE-203-311A (Z) HN27C4000G Series 524288-Word × 8-Bit/262144-Word × 16-Bit CMOS UV Erasable and Programmable ROM Rev. 1 Nov. 10, 1994 The Hitachi HN27C4000 is a 4-Mbit UV erasable and electrically programmable ROM that is organized either as 524288-word × 8 bit or as 262144-word × 16 bit, featuring extra-high speed burst mode that gives two times faster 4-word or 8byte serial access than normal. And also high speed and fast programming are served as well as the existing Hitachi 4M device HN27C4096 and HN27C4001. Fabricated on advanced fine process and high speed circuitry technique, HN27C4000 makes high speed access time and low power dissipation in either active or stand-by mode. Therefore, it is suitable for all systems featuring high speed microprocessor such as the 80386, 80486, 68030, 68040 and so on. Features • Organization: 524288-word × 8-bit/262144word × 16-bit (BYTE/VPP enables selection byte-wide or word-wide) • High speed: Access time 100 ns/120 ns/150 ns (max) Burst access time 50 ns/60 ns/60 ns (max) • Low power dissipation: Standby mode; 5 µW (typ), Active mode; 150 mW/MHz (typ) • Fast high reliability page programming, fast high-reliability programming and option programming: Program voltage; +12.5 V DC Program time; 3.5 sec (min) (Theoretical in Page programming) • Inputs and outputs TTL compatible during both read and program modes • Pin arrangement: 40-pin EIAJ standard pin compatible with HN62414/ HN62434 • Device identifier mode: Manufacturer code and device code HN27C4000G Series Pin Arrangement HN27C4000G Series A17 A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE I/O0 I/O8 I/O1 I/O9 I/O2 I/O10 I/O3 I/O11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE/VPP VSS I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC (Top view) Ordering Information Pin Description Type No. Access time Package HN27C4000G-10 100 ns 600-mil HN27C4000G-12 120 ns 40-pin cerdip HN27C4000G-15 150 ns (DG-40A) 2 Pin name Function A0 – A17 Address I/O0 – I/O14 Input/output I/O15/A-1 Input/output/address CE Chip enable OE Output enable VCC Power supply BYTE/VPP Byte/word selection/ Programming power supply VSS Ground HN27C4000G Series Block Diagram A7 : : : : : : : : : : : : A17 2,048 x 2,048 Memory Matrix XDecoder I/O0 : : : Y-Gating Input Data Control I/O15 Y-Decoder CE A0 . . . . . . . . . . . . . A6 OE VCC VPP H H VSS : High threshold inverter Mode Selection Pin CE OE A9 BYTE/VPP VCC I/O0 – I/O7, I/O8 – I/O14, I/O15/A-1 DG-40A (10) (12) (39) (31) (21) (13 – 20, 22 – 28, 29) Read (X16 bit) VIL VIL X VIH VCC Dout Dout Dout Read (X8 bit) VIL VIL X VIL VCC Dout High-Z VIH/VIL Output disable (X16 bit) VIL VIH X VIH VCC High-Z High-Z High-Z Output disable (X8 bit) VIL VIH X VIL VCC High-Z High-Z VIH/VIL Mode 3 HN27C4000G Series Mode Selection (cont) Pin CE OE A9 BYTE/VPP VCC I/O0 – I/O7, I/O8 – I/O14, I/O15/A-1 DG-40A (10) (12) (39) (31) (21) (13 – 20, 22 – 28, 29) VIH X X VSS – VCC VCC High-Z High-Z High-Z VIH VH*2 X VPP VCC High-Z High-Z High-Z VIL VH*2 X VPP VCC Din Din Din VIL VIH X VPP VCC High-Z High-Z High-Z Page program verify VIH VIL X VPP VCC Dout Dout Dout Page program reset VIH VIH X VCC VCC High-Z High-Z High-Z Mode Standby Page Page program set prog. Page data latch Page program Word Program prog. Program verify VIL VIH X VPP VCC Din Din Din VIH VIL X VPP VCC Dout Dout Dout Optional verify VIL VIL X VPP VCC Dout Dout Dout Program inhibit VIH VIH X VPP VCC High-Z High-Z High-Z VSS – VCC VCC Code Code Code Identifier VIL VIL *2 VH Notes: 1. X: Don’t care. 2. VH: 12.0 V ± 0.5 V Absolute Maximum Ratings Item Symbol Value Vin, Vout –0.6*2 to +7.0 V Voltage on pin A9 and OE VID –0.6*2 to +13.0 V VPP voltage *1 VPP –0.6 to +13.5 V VCC voltage *1 VCC –0.6 to +7.0 V Operating temperature range Topr 0 to +70 °C *3 Tstg –65 to +125 °C Tbias –20 to +80 °C All input and output voltages*1 Storage temperature range Storage temperature under bias Unit Notes: 1. Relative to VSS. 2. Vin, Vout, VID min = –2.0 V for pulse width ≤ 20 ns 3. Storage temperature range of device before programming. 4 HN27C4000G Series Capacitance (Ta = 25°C, f = 1 MHz) Item Symbol Min Typ Max Unit Test conditions Notes Input capacitance Cin — — 12 pF Vin = 0 V Except BYTE/VPP Output capacitance Cout — — 20 pF Vout = 0 V Read Operation DC Characteristics (VCC = 5 V ± 10%, VPP = VSS to VCC, Ta = 0 to +70°C) Item Symbol Min Typ Max Unit Test conditions Input leakage current ILI — — 2 µA Vin = 5.5 V Output leakage current ILO — — 2 µA Vout = 5.5 V/0.45 V VPP current IPP1 — 1 20 µA VPP = 5.5 V Standby VCC current ISB1 — — 1 mA CE = VIH ISB2 — 1 20 µA CE = VCC ± 0.3 V ICC1 — — 35 mA Iout = 0 mA, f = 1 MHz ICC2 — — 120 mA Iout = 0 mA, f = 10 MHz VIL –0.3*1 — 0.8 V VIH 2.2 — VCC + 1*2 V VOL — — 0.45 V IOL = 2.1 mA VOH 2.4 — — V IOH = –400 µA Operating VCC current Input voltage Output voltage Notes: 1. VIL min = –1.0 V for pulse width ≤ 50 ns VIL min = –2.0 V for pulse width ≤ 20 ns 2. VIH max = VCC +1.5 V for pulse width ≤ 20 ns If VIH is over the specified maximum value, read operation cannot be guaranteed. 5 HN27C4000G Series AC Characteristics (VCC = 5 V ± 10%, VPP = VSS to VCC, Ta = 0 to +70°C) Test Conditions • • • • Input pulse levels: 0.45 to 2.4 V Input rise and fall times: ≤ 10 ns Output load: 1 TTL gate +100 pF Reference levels for measuring timing: 0.8 V, 2.0 V HN27C4000 HN27C4000 HN27C4000 -10 -12 -15 Item Symbol Min Max Min Max Min Max Unit Test conditions Address to output delay tACC — 100 — 120 — 150 ns CE = OE = VIL CE to output delay tCE — 100 — 120 — 150 ns OE = VIL OE to output delay tOE — 60 — 60 — 70 ns CE = VIL Burst address to output delay tBAC — 50 — 60 — 60 ns CE = VIL OE high to output float *1 tDF 0 35 0 40 0 50 ns CE = VIL Address to output hold tOH 5 — 5 — 5 — ns CE = OE = VIL Note: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. Read Timing Waveform Address CE Standby mode Active mode Standby mode tCE OE tDF tOE tOH t ACC Data Out 6 Data Out Valid HN27C4000G Series Read Timing Waveform (Burst access mode) In Burst Access mode, fast read-out of 4 word data is selected by address A0, A1. (Valid only for Read × 16 mode) A2 to A17 t ACC t CE CE t OE OE t BAC t BAC tBAC tBAC A0, A1 t OH Data Out Valid Output t OH Valid Output t OH t OH Valid Output Valid Output 7 HN27C4000G Series In Burst Access mode, fast read-out of 8 byte data is selected by address A-1, A0, A1. (Valid only for Read × 8 mode) A2 to A17 t ACC t CE CE t OE OE tBAC t BAC tBAC tBAC tBAC tBAC tBAC tBAC A-1, A0, A1 Data Out 8 t OH t OH t OH t OH t OH t OH t OH t OH Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output HN27C4000G Series Page Program Set Fast High-Reliability Page Programming Apply 12 V to OE pin after applying 12.5 V to VPP to set a page program mode. This device can be applied the high performance page programming algorithm shown in the following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. The device operates in a page program mode until reset. Page Program Reset Set V PP to V CC level or less to reset a page program mode. START SET PAGE PROG LATCH MODE VPP= 12.5 ± 0.3 V VCC = 6.25 ± 0.25 V OE = 12.0 ± 0.5 V Address = 0 n=0 Latch Address + 1 → Address Latch Address + 1 → Address Latch Address + 1 → Address Latch n + 1 →n SET PAGE PROG./VERIFY MODE VPP = 12.5 ± 0.3 V VCC = 6.25 ± 0.25 V Address + 1 → Address Program tPW = 50 µs ± 5% VERIFY NO NOGO GO LAST address? n = 10? YES SET READ MODE VCC = 5.0 ± 0.5 V VPP = VCC READ all address NO YES NOGO GO END FAIL Fast High-Reliability Page Programming Flowchart 9 HN27C4000G Series DC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C) Item Symbol Min Typ Max Unit Test conditions Input leakage current ILI — — 2 µA Vin = 6.5 V/0.45 V Output voltage during verify VOL — — 0.45 V IOL = 2.1 mA VOH 2.4 — — V IOH = –400 µA ICC — — 50 mA VIL –0.1*5 — 0.8 V VIH 2.2 — VCC + 0.5*6 V VH 11.5 12.0 12.5 V IPP — — 70 mA Operating VCC current Input voltage VPP supply current CE = VIL Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. VPP must not exceed 13 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12.5 V. 4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low. 5. VIL min = –0.6 V for pulse width ≤ 20 ns. 6. If VIH is over the specified maximum value, programming operation cannot be guaranteed. 10 HN27C4000G Series AC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C) Test Conditions • Input pulse levels: 0.45 to 2.4 V • Input rise and fall times: ≤ 20 ns • Reference levels for measuring timing: Inputs; 0.8 V, 2.0 V, Outputs; 0.8 V, 2.0 V Item Symbol Min Typ Max Unit Address setup time tAS 2 — — µs OE setup time tOES 2 — — µs Data setup time tDS 2 — — µs Address hold time tAH 0 — — µs Data hold time tDH 2 — — µs OE high to output float delay tDF*1 0 — 130 ns VPP setup time tVPS 2 — — µs VCC setup time tVCS 2 — — µs CE initial programming pulse width tPW 47.5 50.0 52.5 µs CE setup time tCES 2 — — µs Data valid from OE tOE 0 — 150 ns CE pulse width during data latch tLW 1 — — µs OE = VH setup time tOHS 2 — — µs OE = VH hold time tOHH 2 — — µs tVRS 1 — — µs VPP hold time*2 Test conditions Notes: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. Page program mode will be reset when VPP is set to VCC or less. 11 HN27C4000G Series Fast High-Reliability Page Programming Timing Waveform Page program mode Program data latch Page program Program verify A2 – A17 t AH t AS t AS t AH A0, A1 t DH t OE t DF t DS Data in stable Data Data out valid t VPS VPP VPP VCC t VCS VCC + 1.25 VCC t OHH VCC t CES t PW t OES t OHS CE t LW OE VH VIH VIL 12 t VRS HN27C4000G Series Fast High-Reliability Programming This device can be applied the fast high-reliability programming algorithm shown in the following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. START SET PROG./VERIFY MODE VPP = 12.5 ± 0.3 V VCC = 6.25 ± 0.25 V Address = 0 n=0 n+1 n Program tPW = 50 µs ± 5% Address + 1 VERIFY GO Address NO NOGO n = 10? LAST address? NO YES YES SET READ MODE VCC = 5.0 ± 0.5 V VPP = VCC READ all address NOGO GO END FAIL Fast High-Reliability Programming Flowchart 13 HN27C4000G Series DC Characteristics (VCC = 6.25 V ± 0.25 V, VPP =12.5 V ± 0.3 V, Ta=25°C ± 5°C) Item Symbol Min Typ Max Unit Test conditions Input leakage current ILI — — 2 µA Vin = 6.5 V/0.45 V VPP supply current IPP — — 40 mA CE = VIL Operating VCC current ICC — — 50 mA VIL –0.1*5 — 0.8 V VIH 2.2 — VCC + 0.5*6 V VOL — — 0.45 V IOL = 2.1 mA VOH 2.4 — — V IOH = –400 µA Input voltage Output voltage Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. VPP must not exceed 13 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12.5 V. 4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low. 5. VIL min = –0.6 V for pulse width ≤ 20 ns. 6. If VIH is over the specified maximum value, programming operation cannot be guaranteed. AC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C) Test Conditions • Input pulse levels: 0.45 to 2.4 V • Input rise and fall times: ≤ 20 ns • Reference levels for measuring timings: 0.8 V, 2.0 V Item Symbol Min Typ Max Unit Address setup time tAS 2 — — µs OE setup time tOES 2 — — µs Data setup time tDS 2 — — µs Address hold time tAH 0 — — µs Data hold time tDH 2 — — µs OE to output float delay tDF *1 0 — 130 ns VPP setup time tVPS 2 — — µs VCC setup time tVCS 2 — — µs CE initial programming pulse width tPW 47.5 50.0 52.5 µs Data valid from OE tOE 0 — 150 ns Note: 14 Test conditions 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. HN27C4000G Series Fast High-Reliability Programming Timing Waveform Program Program Verify Address t AH t AS Data Data In Stable t DS V PP Data Out Valid t DF t DH V PP V CC t VPS V CC V CC+1.25 V CC t VCS CE t PW t OES t OE OE Optional Page Programming This device can be applied the optional page programming algorithm shown in the following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. This programming algorithm is the combination of page programming and word verify. It can avoid the increase of programming verify time when a programmer with slow machine cycle is used, and shorten the total programming time. Regarding the timing specifications for page programming and word verify, please refer to the specifications for fast high-reliability page programming and fast high-reliability programming. 15 HN27C4000G Series START SET PAGE PROG LATCH MODE VPP= 12.5 ± 0.3 V VCC = 6.25 ± 0.25 V OE = 12.0 ± 0.5 V Address = 0 Latch Address + 1 Address Latch Address + 1 Address Latch Address + 1 Address Latch SET PAGE PROG. MODE VPP = 12.5 ± 0.3 V V CC = 6.25 ± 0.25 V Address + 1 Program tPW = 50 µs ± 5% Address NO LAST address? YES PAGE PROG. RESET VPP = VCC = 6.25 ± 0.25 V SET WORD PROG./VERIFY MODE VPP = 12.5 ± 0.3 V V CC = 6.25 ± 0.25 V Address = 0 n=0 GO VERIFY NOGO n+1 Address + 1 Address n Program tPW = 50 µs ± 5% VERIFY NOGO GO LAST all address? n = 10? YES SET READ MODE VCC = 5.0 ± 0.5 V VPP = VCC READ all address YES NOGO GO END Optional Page Programming Flowchart 16 FAIL NO HN27C4000G Series DC Characteristics (VCC = 6.25 V ± 0.25 V, VPP =12.5 V ± 0.3 V, Ta = 25°C ± 5°C) Item Symbol Min Typ Max Unit Test conditions Input leakage current ILI — — 2 µA Vin = 6.5 V/0.45 V Output voltage during verify VOL — — 0.45 V IOL = 2.1 mA VOH 2.4 — — V IOH = –400 µA ICC — — 50 mA VIL –0.1*5 — 0.8 V VIH 2.2 — VCC + 0.5*6 V VH 11.5 12.0 12.5 V IPP — — 70 mA Operating VCC current Input voltage VPP supply current CE = VIL Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. VPP must not exceed 13 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12.5 V. 4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low. 5. VIL min = –0.6 V for pulse width ≤ 20 ns. 6. If VIH is over the specified maximum value, programming operation cannot be guaranteed. 17 HN27C4000G Series AC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C) Test Conditions • Input pulse levels: 0.45 to 2.4 V • Input rise and fall times: ≤ 20 ns • Reference levels for measuring timings: Inputs; 0.8 V, 2.0 V Outputs; 0.8 V, 2.0 V Item Symbol Min Typ Max Unit Address setup time tAS 2 — — µs OE setup time tOES 2 — — µs Data setup time tDS 2 — — µs Address hold time tAH 0 — — µs Data hold time tDH 2 — — µs OE high to output float delay tDF *1 0 — 130 ns VPP setup time tVPS 2 — — µs VCC setup time tVCS 2 — — µs CE initial programming pulse width tPW 47.5 50.0 52.5 µs CE setup time tCES 2 — — µs Data valid from OE tOE 0 — 150 ns CE pulse width during data latch tLW 1 — — µs OE = VH setup time tOHS 2 — — µs tOHH 2 — — µs tVLW 1 — — µs tVRS 1 — — µs OE = VH hold time Page programming reset time VPP hold time *2 *2 Test conditions Notes: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. Page program mode will be reset when VPP is set to VCC or less. 18 HN27C4000G Series Option Page Programming Timing Waveform Word program mode Page program mode Program data latch Page program Program verify Program A2 – A17 t AH t AS t AH t AS t AH A0, A1 t DH t DS t DS Data out valid Data in stable Data Data in stable t VPS t OE t DF t VPS VPP t DF VPP VCC t VRS t VCS t VLW VCC+ 1.25 VCC VCC t OHH t CES t CES t OHS CE t OES t LW t PW OE t PW VH VIH VIL 19 HN27C4000G Series Erase Mode Description Erasure of this device is performed by exposure to ultraviolet light of 2537 Å and all the output data are changed to “1” after this erasure procedure. The minimum integrated dose (i.e. UV intensity X exposure time) for erasure is 15 W•sec/cm2. Device Identifier Mode The device identifier mode allows the reading out of binary codes that identify manufacturer and type of device, from outputs of EPROM. By this mode, the device will be automatically matched its own corresponding programming algorithm, using programming equipment. HN27C4000G Identifier Code A0 Identifier DG-40 (9) I/O8 – I/O15 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 — (28) (26) (24) (22) (19) (17) (15) (13) Hex Data Manufacturer code VIL X 0 0 0 0 0 1 1 1 07 Device code VIH X 1 0 1 0 0 0 0 1 A1 Notes: 1. 2. 3. 4. 5. 20 VCC = 5.0 V ± 10% A9 = 12.0 V ± 0.5 V CE, OE = VIL A1 – A8, A10 – A17: Don’t care. X: Don’t care.