HL15203 HL15203 LCD Driver IC Preliminary 2Q. 1999 Hyundai Electronics Industries System IC Division 1 Preliminary HL15203 Contents 1. General Description 2. Features 3. Block Diagram 4. Pin Diagram 5. Pin Description 6. Serial I/O Data Format 7. Registers 8. Key Scan Function 9. LCD Function 10. INH and Display Control 11. Power Down Mode 12. Oscillator Port 13. Electrical Characteristics 14. Application 2 Preliminary HL15203 1. General Description The HL15203 is 1/3 duty LCD display driver. It can drive directly maximum 156 segments. 2. Features • LCD display ..................................... 52 segments x 3 commons 1/3 duty - 1/2 bias 1/3 duty - 1/3 bias Power down mode ..........................…. Sleep mode and all segments off mode Serial I/O .............................................. Data transfer and receive RC oscillator Package ............................................... 64QFP • • • • Package Dimensions 64QFP(12¡ ¿ 12) 64QFP(14¡ ¿ 14) 17.2 10.0 0.15 33 32 48 49 33 32 1.25 10.0 12.0 0.8 14.0 17.2 1.0 48 49 0.8 0.5 1.0 12.0 1.6 1.0 0.15 0.5 1.6 14.0 17 16 1.0 64 1 64 17 1 0.35 16 0.35 2.70 0.1 0.5 1.25 1.7max 0.1 Unit : mm Unit : mm 3 Preliminary HL15203 SEG1 COM1 COM2 COM3 SEG52 SEG51 . . . . . . . . . . . 3. Block Diagram • VCL1 VCL2 • • • • COMMON DRIVER • LATCH & DRIVER INH SHIFT REGISTER VDD VSS ADDRESS DETECTOR • CE SI OSC CLOCK GENERATOR • SCK • SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 4. Pin Diagram 33 32 48 49 HL15203 17 16 64 1 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG49 SEG50 SEG51 SEG52 COM1 COM2 COM3 VDD INH VCL1 VCL2 VSS OSC CE SCK SI 4 Preliminary HL15203 5. Pin Description PIN Name I/O Pin Number SEG[52:1] O 52 LCD SEG Pins COM [3:1] O 3 LCD Common Pins VCL[2:1] I 2 LCD Bias Pins OSC I 1 Oscillator Input Pin CE I 1 Serial I/O Control Pin SCK I 1 Serial I/O Clock Pin SI I 1 Serial I/O Data Input Pin INH I 1 Display off control pin VDD I 1 Power Supply Pin VSS I 1 Ground Pin 5 Contents Preliminary HL15203 DATA Writing i ) SCK is stopped at the low level CE SCK SI XX 1 1 0 0 0 0 1 0 D1 D2 D154 D155 D156 D3 DR SC BU ¡ ¿ A0 A1 A2 A3 A4 A5 A6 A7 Display data 156bits Address 8 bits Control data 4 bits ii ) SCK is stopped at the high level CE SCK SI XX 1 0 0 0 0 0 1 0 D1 D2 D154 D155 D156 D3 DR SC BU ¡ ¿ A0 A1 A2 A3 A4 A5 A6 A7 Display data 156bits Address 8 bits Control data 4 bits ADDRESS : 41H D1 ~ D156 : Display data Dn(n=1~156)=1 … … … .. Display on Dn(n=1~156)=0 … … … .. Display off DR : 1/2-bias drive or 1/3-bias drive switching control data SC : Segments on/off control data BU : Normal mode/power-saving mode control data 6 Preliminary HL15203 DATA Writing Examples i ) When 146 segments are used 146bits of display data (D11 to D156) must be sent. CE SCK SI XX 1 1 0 0 0 0 1 0 D11 D154 D155 D156 D12 D13 DR SC BU ¡ ¿ A0 A1 A2 A3 A4 A5 A6 A7 Display data 146bits Address 8 bits Control data 4 bits ii ) When 122 segments are used 122bits of display data (D35 to D156) must be sent. CE SCK SI XX 1 1 0 0 0 0 1 0 D35 D154 D155 D156 D36 D37 DR SC BU ¡ ¿ A0 A1 A2 A3 A4 A5 A6 A7 Display data 122bits Address 8 bits Control data 4 bits iii ) When 37 segments are used 37bits of display data (D120 to D156) must be sent. CE SCK SI XX 1 0 0 0 0 0 1 0 D120 D121 D122 D154 D155 D156 DR SC BU ¡ ¿ A0 A1 A2 A3 A4 A5 A6 A7 Display data 37bits Address 8 bits 7 Control data 4 bits Preliminary HL15203 7. Registers 1) Display Registers Output Pin SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 COM3 D1 D4 D7 D10 D13 D16 D19 D22 D25 D28 D31 D34 D37 D40 D43 D46 D49 D52 D55 D58 D61 D64 D67 D70 D73 D76 D79 D82 D85 D88 D91 D94 D97 D100 D103 D106 D109 D112 D115 D118 D121 D124 COM2 D2 D5 D8 D11 D14 D17 D20 D23 D26 D29 D32 D35 D38 D41 D44 D47 D50 D53 D56 D59 D62 D65 D68 D71 D74 D77 D80 D83 D86 D89 D92 D95 D98 D101 D104 D107 D110 D113 D116 D119 D122 D125 8 COM1 D3 D6 D9 D12 D15 D18 D21 D24 D27 D30 D33 D36 D39 D42 D45 D48 D51 D54 D57 D60 D63 D66 D69 D72 D75 D78 D81 D84 D87 D90 D93 D96 D99 D102 D105 D108 D111 D114 D117 D120 D123 D126 Preliminary HL15203 Output Pin SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 COM3 D127 D130 D133 D136 D139 D142 D145 D148 D151 D154 COM2 D128 D131 D134 D137 D140 D143 D146 D149 D152 D155 COM1 D129 D132 D135 D138 D141 D144 D147 D150 D153 D156 2) Control Registers i) 1/2-bias drive or 1/3-bias drive switching control data DR 0 1 Bias Selection 1/3 Bias 1/2 Bias ii) Segments on/off control data Control Data SC 0 1 Display Status SEG1 ~ SEG52 On Off iii) Normal mode/power-saving mode control data BU 0 1 Mode Normal Mode Power-saving mode. In this mode the OSC pin oscillator is stopped and the common and segment pins output Vss levels. 9 Preliminary HL15203 9. LCD Display Function 1) 1/2 Bias, 1/3 Duty Waveforms COM1 VDD VCL1,VCL2 0 COM2 VDD VCL1,VCL2 0 COM3 VDD VCL1,VCL2 0 LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are turned off. VDD VCL1,VCL2 0 LCD driver output when all LCD segments corresponding to COM1 are on. VDD VCL1,VCL2 0 LCD driver output when all LCD segments corresponding to COM2 are on. VDD VCL1,VCL2 0 LCD driver output when all LCD segments corresponding to COM1 and COM2 are on. VDD VCL1,VCL2 0 LCD driver output when all LCD segments corresponding to COM3 are on. VDD VCL1,VCL2 0 LCD driver output when all LCD segments corresponding to COM1 and COM3 are on. VDD VCL1,VCL2 0 LCD driver output when all LCD segments corresponding to COM2 and COM3 are on. VDD VCL1,VCL2 0 VDD VCL1,VCL2 0 LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are on. 10 Preliminary HL15203 2) 1/3 Duty 1/3 Bias Waveforms COM1 VDD VCL1 VCL2 0 COM2 VDD VCL1 VCL2 0 COM3 VDD VCL1 VCL2 0 LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are turned off. VDD VCL1 VCL2 0 LCD driver output when all LCD segments corresponding to COM1 are on. VDD VCL1 VCL2 0 LCD driver output when all LCD segments corresponding to COM2 are on. VDD VCL1 VCL2 0 LCD driver output when all LCD segments corresponding to COM1 and COM2 are on. VDD VCL1 VCL2 0 LCD driver output when all LCD segments corresponding to COM3 are on. VDD VCL1 VCL2 0 LCD driver output when all LCD segments corresponding to COM1 and COM3 are on. VDD VCL1 VCL2 0 VDD VCL1 VCL2 0 LCD driver output when all LCD segments corresponding to COM2 and COM3 are on. VDD VCL1 VCL2 0 LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are on. 11 Preliminary HL15203 10. INH and Display Control Since the LSI internal data (D1 to D156, DR, SC, and BU) is undefined when power is first applied, then display is off(SEG1 to SEG52,COM1 to COM3=low) by setting the INH pin low at the same time as power is applied.Then meaningless display at the power-on can be prevented by transferring serial data from the controller while the display is off and setting INH pin high after the transfer completes. • • VDD R INH • C VDD INH VIL t1 t2 VIL CE Transfer of display and control data Internal data Undefined Defined t1 : Determined by the value of C and R t2 : 10µs(minimum) 12 Preliminary HL15203 11. Power Down Mode Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common outputs will also go low, and the oscillator on the OSC pin will stop ( it will be started by a key press). This reduces power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. Note that the SEG1 to SEG4 outputs can be used as general purpose output ports according to the state of the P0 and P1 control data bits, even in sleep mode. 13 Preliminary HL15203 12. Oscillator Port OSC Pin Diagram R OSC Internal clock SLEEP C Oscillator circuit consists of internal R and C. Using Capacitor No Capacitor OSC OSC Open C HL15203 has internal resistor and capacitor, so it can be oscillation without external capacitor. If you want to adjust the clock period then you can adjust it using external capacitor. 14 Preliminary HL15203 13. Electrical Characteristics Absolute Maximum Rating at Ta=25¡ É , Vss = 0V Parameter Maximum supply voltage Input voltage Output voltage Output current Allowable power dissipation Operating temperature Storage temperature Symbol VDD max Vin1 Vin2 Vout Iout1 Iout2 Pd max Topr Tstg Condition VDD CE,SCK,SI,INH OSC OSC SEG1 to SEG52 COM1 to COM3 Ta = 85¡ É Rating -0.3 to +6.5 -0.3 to +6.5 -0.3 to VDD+0.3 -0.3 to VDD+0.3 300 3 200 -40 to +85 -55 to +125 unit V V V V uA mA mW ¡ É ¡ É Recommend operating ranges at Ta= -40¡ Éto +85¡ É , Vss = 0V Parameter Supply voltage Input voltage Input high level voltage Input low level voltage Recommended external capacitance Guaranteed oscillation range Data setup time Data hold time CE wait time CE setup time CE hold time High level clock pulse width Low level clock pulse width Rise time Fall time INH switching time Symbol VDD VCL1 VCL2 VIH VIL Condition VDD VCL1 VCL2 CE,SCK,SI,INH CE,SCK,SI,INH COSC OSC fOSC tds tdh tcp tcs tch t0h tol tr tf t2 min 4.5 typ 2/3VDD 1/3VDD 4.0 0 max 6.0 6.0 6.0 6.0 0.7 TBD OSC SCK,SI SCK,SI CE,SCK CE,SCK CE,SCK SCK SCK CE,SCK,SI CE,SCK,SI INH,CE 15 19 100 100 100 100 100 100 100 38 100 100 10 unit V V V V V pF 76 KHz ns ns ns ns ns ns ns ns ns µs Preliminary HL15203 Electrical Characteristics for the Allowable Operating Ranges Parameter Input high level current Input low level current Oscillator frequency Hysteresis width Output high level voltage Output low level voltage Symbol IIH IIL fOSC VH VOH1 VOH2 VOL1 VOL2 VMID1 VMID2 Intermediate level voltage* VMID3 VMID4 VMID5 Supply Current IDD1 IDD2 IDD3 IDD2 IDD3 Condition CE,SCK,SI,INH : V1 = 6.0V CE,SCK,SI INH: V1 = 0V OSC : C = TBD CE,SCK,SI,INH,VDD=5V SEG1 to SEG52 : IO = -20 µA COM1 to COM3 : IO = -100 µA min typ max 5.0 -5.0 38 0.3 VDD -1.0 VDD -1.0 SEG1 to SEG52 : IO = 20 µA 1.0 1.0 COM1 to COM3 : IO = 100 µA 1/2 bias, COM1 to COM3: Io = ¡ ¾100µA 1/3 bias, COM1 to COM3: Io = ¡ ¾100µA 1/2 bias, COM1 to COM3: Io = ¡ ¾100µA 1/3 bias ,SEG1 to SEG52 : Io = ¡ ¾20µA 1/3 bias ,SEG1 to SEG52 : Io = ¡ ¾20µA Power saving mode fOSC = 38 kHz,1/2bias,VDD = 5V fOSC = 38 kHz,1/3bias,VDD = 5V fOSC = 38 kHz,1/2bias,VDD = 6V fOSC = 38 kHz,1/3bias,VDD = 6V 1/2 VDD ±1.0 2/3VDD ± 1.0 1/3VDD ± 1.0 2/3VDD ± 1.0 1/3VDD ± 1.0 unit µA µA kHz V V V V V V V V V V 400 300 650 580 5 800 600 1300 1200 µA µA µA µA µA Note : *2. Except the bias voltage generation divider resistor that are built into VCL1 and VCL2 16 Preliminary HL15203 Timing diagram of SIO CE t0l t0h SCK tr SI tf VIH VIL tds tdh VIH VIL CE VIH SCK VIL tcp tch tcs SI 17 Preliminary HL15203 14. Application 1/3 bias ( for use with small panels ) VDD COM1 COM2 COM3 INH VSS OPEN SEG1 . . . . . . VCL1 VCL2 SEG52 CE SCK SI From the microcontroller LCD panel (up to 156 segments) OSC VDD 1/3 bias ( for use with normal panels ) VDD COM1 COM2 COM3 INH VSS C ≥ 0.047uF C C SEG1 . . . . . . VCL1 VCL2 SEG52 From the microcontroller CE SCK SI 18 LCD panel (up to 156 segments) OSC VDD Preliminary HL15203 1/3 bias ( for use with large panels ) VDD COM1 COM2 COM3 INH VSS R 10 KΩ ≥ R ≥ 1 KΩ C ≥ 0.047uF SEG1 . . . . . . VCL1 R VCL2 R C C SEG52 From the microcontroller CE SCK SI 19 LCD panel (up to 156 segments) OSC VDD Preliminary