SN74ALS29833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SDAS119D – FEBRUARY 1987 – REVISED JANUARY 1995 • • • • • DW OR NT PACKAGE (TOP VIEW) Functionally Similar to AMD’s AM29833 High-Speed Bus Transceiver With Parity Generator/Checker Parity-Error Flag With Open-Collector Outputs Register for Storing the Parity-Error Flag Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs OEA A1 A2 A3 A4 A5 A6 A7 A8 ERR CLR GND description 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 VCC B1 B2 B3 B4 B5 B6 B7 B8 PARITY OEB CLK The SN74ALS29833 is an 8-bit to 9-bit parity 11 14 transceiver designed for two-way communication 12 13 between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the parity-error (ERR) output indicates whether or not an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device so that the buses are effectively isolated. A 9-bit parity generator / checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector ERR flag. ERR is clocked into the register on the rising edge of the clock (CLK) input. The error-flag register is cleared with a low pulse on the clear (CLR) input. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. The SN74ALS29833 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUT AND I/O Ai ∑ of Hs OEB OEA CLR CLK L H X X H L H ↑ NA X X L X X H No↑ X L No↑ X H ↑ Odd H ↑ Even H L H L X X Bi† ∑ of Ls A B NA NA A B NA NA X NA NA Odd Even Odd Even Odd Even X PARITY L H ERR‡ NA H L H FUNCTION A data to B bus and generate parity B data to A bus and check parity Clear error-flag register NC X Z Z Z H H Isolation§ L NA NA A H L NA A data to B bus and generate g inverted parity NA = not applicable, NC = no change, X = don’t care † Summation of high-level inputs includes PARITY along with Bi inputs. ‡ Output states shown assume ERR was previously high. § In this mode, ERR, when clocked, shows inverted parity of the A bus. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALS29833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SDAS119D – FEBRUARY 1987 – REVISED JANUARY 1995 logic diagram (positive logic) A1 – A8 2–9 8x 8 16 – 23 8 B1 – B8 EN 8x 8 EN 14 OEB OEA 1 15 8 PARITY 8 1 MUX 1 9 2K P 1 1 G1 1D CLK CLR 13 10 ERR C1 11 R error-flag waveforms OEB H L OEA H L Even Bi + PARITY Odd tsu th H L CLK tw tw tsu H L CLR tPHL tPLH H L ERR 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALS29833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SDAS119D – FEBRUARY 1987 – REVISED JANUARY 1995 ERROR-FLAG FUNCTIONS INPUTS INTERNAL TO DEVICE OUTPUT PRESTATE OUTPUT CLR CLK POINT P ERRn–1† ERR H ↑ H H H H ↑ X L L H ↑ L X L FUNCTION Sample L X X X H Clear † ERRn–1 represents the state of ERR before any changes at CLR, CLK, or point P. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions VCC VIH Supply voltage VIL VOH Low-level input voltage IOH IOL High-level output current tw High-level input voltage MIN MAX UNIT 4.75 5.25 V 2 V 0.8 High-level output voltage, ERR Low-level output current Pulse duration CLK high 10 CLK low 10 CLR low 10 Bi and PARITY 17 CLR inactive 15 tsu Set p time before CLK↑ Setup th TA Hold time, Bi and PARITY after CLK↑ 0 Operating free-air temperature 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 5.5 V – 24 mA 48 mA ns ns ns 70 °C 3 SN74ALS29833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SDAS119D – FEBRUARY 1987 – REVISED JANUARY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VCC = 4.75 V, VOH All I/Os except e cept ERR VCC = 4 4.75 75 V IOH VOL ERR VCC = 4.75 V, VCC = 4.75 V, II IIH‡ IIL‡ VCC = 5.25 V, VCC = 5.25 V, Data VCC = 5 5.25 25 V V, Control MIN II = – 18 mA IOH = – 15 mA IOH = – 24 mA VOH = 5.5 V TYP† MAX UNIT – 1.2 V 2.4 V 2 0.1 IOL = 48 mA VI = 5.5 V 0.35 VI = 2.7 V 0.5 V 0.1 mA 20 µA – 0.2 VI = 0 0.4 4V – 0.75 IO§ VCC = 5.25 V, VO = 0 – 75 ICC VCC = 5.25 V 70 † All typical values are at VCC = 5 V, TA = 25°C. ‡ For I/O ports, the parameters IIH and IIL include the off-state output current. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. mA mA – 250 mA 100 mA switching characteristics (see Figure 1) VCC = 4.75 V to 5.25 V, TA = MIN to MAX¶ FROM (INPUT) TO (OUTPUT) TEST CONDITIONS tPLH tPHL A or B B or A CL = 50 pF tPLH tPHL A or B B or A CL = 300 pF tPLH tPHL A PARITY CL = 50 pF tPLH tPHL A PARITY CL = 300 pF tPZH tPZL OEA or OEB A or B CL = 50 pF tPZH tPZL OEA or OEB A or B CL = 300 pF tPHZ tPLZ OEA or OEB A or B CL = 5 pF tPHZ tPLZ OEA or OEB A or B CL = 50 pF 8 tPHL CLK ERR CL = 50 pF 13 ns tPLH CLR ERR CL = 50 pF 13 ns tPLH tPHL OEA PARITY CL = 50 pF tPLH tPHL OEA PARITY CL = 300 pF PARAMETER MIN 8 4 8 15 15 15 19 22 24 17 17 23 23 9 9 15 17 ¶ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MAX 19 22 25 ns ns ns ns ns ns ns ns ns ns SN74ALS29833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SDAS119D – FEBRUARY 1987 – REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION Test Point VCC S1 From Output Under Test RL = 180 Ω R1 1 kΩ CL (see Note A) VCC SWITCH POSITION TABLE All Diodes 1N916 or 1N3064 S2 TEST S1 S2 tPLH tPHL tPZH tPZL tPHZ tPLZ Closed Closed Open Closed Closed Closed Closed Closed Closed Open Closed Closed 180 Ω From Output Under Test 1.5 V Timing Input LOAD CIRCUIT 2 ERROR-FLAG OUTPUT High-Level Input 3V 1.5 V 1.5 V 0 0 tw th tsu 510 Ω CL (see Note A) LOAD CIRCUIT 1 ALL OUTPUTS EXCEPT FOR ERROR FLAG 3V Test Point 3V 3V Data Input 1.5 V 1.5 V 0 Low-Level Input 1.5 V 1.5 V 0 VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Output Control 1.5 V 1.5 V 0 tPZL tPLZ ≈ 4.5 V 3V Input 1.5 V 1.5 V 0 1.5 V tPHL tPLH 1.5 V 1.5 V VOL tPHZ VOH 1.5 V VOH Waveform 2 (see Note B) 1.5 V 1.5 V 0.5 V ≈ 1.5 V ≈0 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 0.5 V tPZH tPLH tPHL ≈ 1.5 V VOL VOH In-Phase Output Out-of-Phase Output Waveform 1 (see Note B) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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