ETC CH7009A-T

CH7009A
CHRONTEL
Chrontel CH7009 DVI / TV Output Device
Features
General Description
•
•
•
•
The CH7009 is a Display controller device which accepts a
digital graphics input signal, and encodes and transmits
data through a DVI TMDSTM link (DFP can also be
supported) or TV output (analog composite, s-video or
RGB). The device accepts data over one 12-bit wide
variable voltage data port which supports five different
data formats including RGB and YCrCb.
•
•
•
•
•
•
•
•
•
•
•
•
•
DVI Transmitter up to 165MHz
DVI low jitter PLL
DVI hot plug detection
TV output supporting up to 1024x768 graphics
resolutions
MacrovisionTM 7.X copy protection support
Programmable digital interface supports RGB and
YCrCb
TrueScaleTM rendering engine supports underscan in all
TV output resolutions
Enhanced text sharpness and adaptive flicker removal
with up to 7 lines of filtering
Support for all NTSC and PAL formats
Provides CVBS, S-Video and SCART (RGB) outputs
TV connection detect
Programmable power management
10-bit video DAC outputs
Fully programmable through I2C port
Complete Windows and DOS driver support
Low voltage interface support to graphics device
Offered in a 64-pin LQFP package
XCLK,XCLK*
D[11:0]
2
12
The DVI processor includes a low jitter PLL for generation
of the high frequency serialize clock, and all circuitry
required to encode, serialize and transmit data. The
CH7009 comes in versions able to drive a DVI display at a
pixel rate of up to 165MHz, supporting UXGA resolution
displays. No scaling of input data is performed on the data
output to the DVI device.
The TV-Out processor will perform non-interlace to
interlace conversion with scaling and flicker filters, and
encode the data into any of the NTSC or PAL video
standards. The scaling and flicker filter is adaptive and
programmable to enable superior text display. Eight
graphics resolutions are supported up to 1024 by 768 with
full vertical and horizontal underscan capability in all
modes. A high accuracy low jitter phase locked loop is
integrated to create outstanding video quality. Support is
provided for MacrovisionTM and RGB bypass mode which
enables driving a VGA CRT with the input data.
Clock
Driver
Data
Latch,
Demux
DVI (TMDS
24
3
DVI
Encode
TM
link) PLL
DVI
Serialize
2
DVI
Driver
2
2
2
VREF
3
H,V,DE
Latch
TDC0,TDC0*
TDC1,TDC1*
TDC2,TDC2*
VSWING
HPDET
24
2
H,V,DE
TLC,TLC*
IIC
Control
3
GPIO[1:0]
AS
SC
SD
RESET*
XI/FIN,XO
P-OUT / TLDET*
C/H SYNC
2
PLL3
ISET
Timing
BCO
3
24
Scaling
Scan Conv
Flicker Filt
TV
Encode
Four
10-bit
DAC's
CVBS (DAC3)
Y (DAC 1)
C (DAC 2)
CVBS (DAC0)
24
Figure 1: Functional Block Diagram
201-0000-035 Rev 1.1, 5/8/2000
*TMDS is Trademark of Silicon Image Inc.
1
CHRONTEL
CH7009A
Pin Descriptions
64 DGND
63 D[0]
62 D[1]
61 D[2]
60 D[3]
59 D[4]
58 D[5]
57 XCLK
56 XCLK*
55 D[6]
54 D[7]
53 D[8]
52 D[9]
51 D[10]
50 D[11]
49 DVDD
Package Diagram
DVDD
DE
VREF
H
V
DGND
GPIO[1] / TLDET*
GPIO[0]
HPDET
AS
DGND
DVDD
RESET*
SD
SC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Chrontel
CH7009
C / H SYNC
BCO
P-Out/TLDET*
DVDDV
AVDD
XO
XI / FIN
AGND
GND
CVBS / B
C/ R
Y/G
CVBS
ISET
GND
VDD
TGND
TLC
TLC*
TVDD
TDC2
TDC2*
TGND
TDC1
TVDD
TDC1*
TDC0
TDC0*
TGND
VSWING
AVDD
AGND
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Figure 2: 64-Pin LQFP
2
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
Table 1: Pin Description
64-Pin
# Pins Type
LQFP
2
1
In
Symbol
Description
DE
Data Enable
This pin accepts a data enable signal which is high when active
video data is input to the device, and low all other times. The
levels are 0 to DVDDV, and the VREF signal is used as the
threshold level. This input is used by the DVI links. The TVOut function uses H and V sync signals as reference to active
video.
3
1
In
VREF
Reference Voltage Input
The VREF pin inputs a reference voltage of DVDDV / 2. The
signal is derived externally through a resistor divider and
decoupling capacitor, and will be used as a reference level for
data, sync, data enable and clock inputs.
4
1
In/Out
H
Horizontal Sync Input / Output
When the SYO bit is low, this pin accepts a horizontal sync
input for use with the input data. The amplitude will be 0 to
DVDDV, and the VREF signal is used as the threshold level.
When the SYO bit is high, the device will output a horizontal
sync pulse, 64 pixels wide. The output is driven from the
DVDD. This output is only for use with the TV-Out function.
5
1
In/Out
V
Vertical Sync Input / Output
When the SYO bit is low, this pin accepts a vertical sync input
for use with the input data. The amplitude will be 0 to
DVDDV, and the VREF signal is used as the threshold level.
When the SYO bit is high, the device will output a vertical
sync pulse one line wide. The output is driven from the DVDD
supply. This output is only for use with the TV-Out function.
7
2
In/Out
GPIO[1] /
TLDET*
General Purpose Input - Output[1] /
DVI Link Detect Output (internal pull-up)
This pin provides a general purpose I/O controlled via the IIC
bus. The internal pull-up will be to the DVDD supply.
When the GPIO[1] pin is configured as an input, this pin can
be used to output the DVI link detect signal (pulls low when a
termination change has been detected on the HPDET input).
This is an open drain output. The output is released through
IIC control.
8
2
In/Out
GPIO[0]
General Purpose Input - Output[0] (internal pull-up)
This pin provides a general purpose I/O controlled via the IIC
bus. This allows an external switch to be used to select NTSC
or PAL at power-up. The internal pull-up will be to the DVDD
supply.
9
1
In
HPDET
Hot Plug Detect (internal pull-down)
This input pin determines whether the DVI link is connected to
a DVI monitor. When terminated, the monitor is required to
apply a voltage greater than 2.4 volts. Changes on the status of
this pin will be relayed to the graphics controller via the POUT/TLDET* or GPIO[1]/TLDET* pin pulling low.
10
1
In
AS
Address Select (Internal pull-up)
This pin determines the IIC address of the device
(1,1,1,0,1,AS*,AS).
13
1
In
RESET*
Reset * Input (Internal pull-up)
When this pin is low, the device is held in the power-on reset
condition. When this pin is high, reset is controlled through
the IIC register.
201-0000-035 Rev 1.1, 5/8/2000
3
CHRONTEL
CH7009A
Table 1: Pin Description
64-Pin
# Pins Type
LQFP
14
1
In/Out
Symbol
Description
SD
Serial Data Input / Output
This pin functions as the serial data pin of the IIC interface
port, and uses the DVDD supply.
15
1
In
SC
19
1
In
VSWING
Serial Clock Input
This pin functions as the clock pin of the IIC interface port,
and uses the DVDD supply.
TMDSTM Link Swing Control
This pin sets the swing level of the DVI outputs. A 2.4K ohm
resistor should be connected between this pin and TGND using
short and wide traces.
22, 21
25, 24
28, 27
30, 31
35
2
2
2
2
1
Out
Out
Out
Out
In
TDC0,
TMDSTM Data Channel 0 Outputs
TDC0*
These pins provide the DVI differential outputs for data
channel 0 (blue).
TDC1,
TMDSTM Data Channel 1 Outputs
TDC1*
These pins provide the DVI differential outputs for data
channel 1 (green).
TDC2,
TMDSTM Data Channel 2 Outputs
TDC2*
These pins provide the DVI differential outputs for data
channel 2 (red).
TLC,
TMDSTM Link Clock Outputs
TLC*
These pins provide the differential clock output for the DVI
interface corresponding to data on the TDC[0:2] outputs.
ISET
Current Set Resistor Input
This pin sets the DAC current. A 140 ohm resistor should be
connected between this pin and GND (DAC ground) using
short and wide traces.
36
1
Out
CVBS
Composite Video
This pin outputs a composite video signal capable of driving a
75 ohm doubly terminated load.
37
1
Out
Y/G
Luma / Green Output
This pin outputs a selectable video signal. The output is
designed to drive a 75 ohm doubly terminated load. The
output can be selected to be s-video luminance or green.
38
1
Out
C/R
Chroma / Red Output
This pin outputs a selectable video signal. The output is
designed to drive a 75 ohm doubly terminated load. The
output can be selected to be s-video chrominance or red.
39
1
Out
CVBS/B
Composite Video / Blue Output
This pin outputs a selectable video signal. The output is
designed to drive a 75 ohm doubly terminated load. The
output can be selected to be composite video or blue.
42
1
In
XI / FIN
Crystal Input / External Reference Input
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should
be attached between this pin and XO. However, an external
clock can drive the XI/FIN input.
43
1
In
XO
Crystal Output
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should
be attached between this pin and XI / FIN. However, if an
external CMOS clock is attached to XI/FIN, XO should be left
open.
4
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
Table 1: Pin Description
64-Pin
# Pins Type
LQFP
46
1
Out
Symbol
Description
P-OUT /
Pixel Clock Output / DVI Link Detect Output
TLDET*
When the CH7009 is operating as a VGA to TV encoder in
master clock mode, this pin provides a pixel clock signal to the
VGA controller which is used as a reference frequency. The
output is selectable between 1X or 2X of the pixel clock
frequency. The output driver is driven from the DVDDV
supply. This output has a programmable tri-state. The
capacitive loading on this pin should be kept to a minimum.
When the CH7009 is operating as a DVI transmitter, this pin
provides an open drain output which pulls low when a
termination change has been detected on the HPDET input.
The output is released through IIC control.
47
1
Out
BCO
Buffered Clock Output
This output pin provides a buffered clock output, driven by the
DVDD supply. The output clock can be selected using the BCO
register.
48
1
Out
C/H SYNC
Composite / Horizontal Sync Output
This pin can be selected to output a TV composite sync, TV
horizontal sync, or a buffered version of the VGA horizontal
sync. The output is driven from the DVDD supply.
50 – 55,
12
In / Out
D[11] - D[0] Data[11] through Data[0] Inputs
58 – 63
57, 56
2
In
XCLK,
XCLK*
1, 12, 49
6, 11, 64
45
23, 29
20, 26, 32
18, 44
16, 17, 41
33
34, 40
3
3
1
2
3
2
3
1
2
Power
Power
Power
Power
Power
Power
Power
Power
Power
201-0000-035 Rev 1.1, 5/8/2000
DVDD
DGND
DVDDV
TVDD
TGND
AVDD
AGND
VDD
GND
These pins accept the 12 data inputs from a digital video
port of a graphics controller. The levels are 0 to DVDDV,
and the VREF signal is used as the threshold level.
External Clock Inputs
These inputs form a differential clock signal input to the
CH7009 for use with the H, V, DE and D[11:0] data. If
differential clocks are not available, the XCLK* input
should be connected to VREF.
The output clocks from this pad cell are able to have their
polarities reversed under the control of the MCP bit.
Digital Supply Voltage (3.3V)
Digital Ground
I/O Supply Voltage (3.3V to 1.1V)
DVI Transmitter Supply Voltage (3.3V)
DVI Transmitter Ground
PLL Supply Voltage (3.3V)
PLL Ground
DAC Supply Voltage (3.3V)
DAC Ground
5
CHRONTEL
CH7009A
Modes of Operation
The CH7009 is capable of being operated as a single DVI output link, or as a VGA to TV encoder. The two
modes of operation cannot be used simultaneously. Descriptions of each of the operating modes, with a block
diagram of the data flow within the device is shown below.
DVI Output
In DVI Output mode, multiplexed input data, sync and clock signals are input to the CH7009 from the graphics
controllers digital output port. Data will be 2X multiplexed, and the clock inputs can be 1X or 2X times the
pixel rate. Some examples of modes supported are shown in the table below, and a block diagram of the
CH7009 is shown on the following page. For the table below, clock frequencies for given modes were taken
from VESA DISPLAY MONITOR TIMING SPECIFICATIONS if they were detailed there, not VESA
TIMING DEFINITION FOR FLAT PANEL MONITORS. The device is not dependent upon this set of timing
specifications. Any values of pixels/line, lines/frame and clock rate are acceptable, as long as the pixel rate
remains below 165MHz. In the block diagram, all blocks are shown. Those blocks which are non-active are
shown as shaded. The clock and data paths which are in use are highlighted. Although the block diagram does
not show this path as being active, the data input can be selected to be output by the DACs as a VGA type
output. For correct DVI operation, the input data format must be selected to be one of the RGB input formats.
Table 2: DVI Output
Graphics
Active
Pixel Aspect Refresh Rate
XCLK
DVI
Resolution
Aspect Ratio
Ratio
(Hz)
Frequency
Frequency
720x400
640x400
640x480
720x4801
720x5761
800x600
1024x768
1280x720
1280x1024
1600x1200
1920x1080
4:3
8:5
4:3
4:3
4:3
4:3
4:3
16:9
4:3
4:3
16:9
1.35:1.00
1:1
1:1
9:8
15:12
1:1
1:1
1:1
1:1
1:1
1:1
<85
<85
<85
59.94
50
<85
<85
<60
<85
<60
<302
(MHz)
<35.5
<31.5
<36
27
27
<57
<95
<67
<158
<165
<140
(MHz)
<355
<315
<360
270
270
<570
<950
<670
<1580
<1650
<1400
1 These
2
6
DVD compatible modes are input in a non-interlaced RGB data format
30Hz in progressive scan modes, 60Hz in interlaced modes
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
XCLK,XCLK*
2
CH7009A
Clock
Driver
DVI (TMDS
24
D[11:0]
12
Data
Latch,
Demux
DVI
Encode
TM link) PLL
DVI
Serialize
2
DVI
Driver
3
2
2
2
VREF
3
H,V,DE
Latch
TDC0,TDC0*
TDC1,TDC1*
TDC2,TDC2*
VSWING
HPDET
24
2
H,V,DE
TLC,TLC*
IIC
Control
3
GPIO[1:0]
AS
SC
SD
RESET*
XI/FIN,XO
P-OUT / TLDET*
C/H SYNC
2
PLL3
ISET
Timing
BCO
3
24
Scaling
Scan Conv
Flicker Filt
TV
Encode
Four
10-bit
DAC's
CVBS (DAC3)
Y (DAC 1)
C (DAC
2)
CVBS (DAC0)
24
Figure 3: DVI Output
201-0000-035 Rev 1.1, 5/8/2000
7
CHRONTEL
CH7009A
TV Output
In TV Output mode, multiplexed input data, sync and clock signals are input to the CH7009 from the graphics
controllers digital output port. A P-OUT clock can be output as a frequency reference to the graphics
controller, which is recommended to ensure accurate frequency generation. Horizontal and vertical sync
signals are normally sent to the CH7009 from the graphics controller, but can be output to the graphics
controller as an option. This method should not be used for pixel frequencies above 50 MHz. Data will be 2X
multiplexed, and the XCLK clock signal can be 1X or 2X times the pixel rate. The input data will be encoded
into the selected video standard, and output from the video DAC’s. The modes supported for TV output are
shown in the table below, and a block diagram of the CH7009 is shown on the following page. In the block
diagram, all blocks are shown. Those blocks which are non-active are shown as shaded. The clock and data
paths which are in use are highlighted.
Table 3: TV Output Modes
Graphics
Resolution
512x384
512x384
720x400
720x400
640x400
640x400
640x480
640x480
720x4801
720x4802
720x5761
720x5762
800x600
800x600
1024x768
1024x768
Active Aspect
Pixel Aspect
Ratio
4:3
4:3
4:3
4:3
8:5
8:5
4:3
4:3
4:3
4:3
4:3
4:3
4:3
4:3
4:3
4:3
Ratio
1:1
1:1
1.35:1.00
1.35:1.00
1:1
1:1
1:1
1:1
9:8
9:8
15:12
15:12
1:1
1:1
1:1
1:1
TV Output Stan- Scaling Ratios
dard
PAL
NTSC
PAL
NTSC
PAL
NTSC
PAL
NTSC
NTSC
NTSC
PAL
PAL
PAL
NTSC
PAL
NTSC
5/4, 1/1
5/4, 1/1
5/4, 1/1
5/4, 1/1
5/4, 1/1
5/4, 1/1, 7/8
5/4, 1/1, 5/6
1/1, 7/8, 5/6
1/1
1/1, 7/8, 5/6
1/1
1/1, 5/6, 5/7
1/1, 5/6, 5/7
3/4, 7/10, 5/8
5/7, 5/8, 5/9
5/8, 5/9, 1/2
1
These DVD modes operate with interlaced input, scan conversion and flicker filter are bypassed
2
These DVD modes operate with non-interlaced input, scan conversion is not bypassed
8
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
XCLK,XCLK*
2
CH7009A
Clock
Driver
DVI (TMDS TM link) PLL
24
D[11:0]
12
Data
Latch,
Demux
DVI
Encode
DVI
Serialize
2
DVI
Driver
3
2
2
2
VREF
3
H,V,DE
Latch
TDC0,TDC0*
TDC1,TDC1*
TDC2,TDC2*
VSWING
HPDET
24
2
H,V,DE
TLC,TLC*
IIC
Control
3
GPIO[1:0]
AS
SC
SD
RESET*
XI/FIN,XO
P-OUT / TLDET*
C/H SYNC
2
PLL3
ISET
Timing
BCO
3
24
Scaling
Scan Conv
Flicker Filt
TV
Encode
Four
10-bit
DAC's
CVBS (DAC3)
Y (DAC 1)
C (DAC
2)
CVBS (DAC0)
24
Figure 4: TV Output Modes
201-0000-035 Rev 1.1, 5/8/2000
9
CHRONTEL
CH7009A
Input Interface
Two distinct methods of transferring data to the CH7009 are described. They are:
• Multiplexed data, clock input at 1X pixel rate
• Multiplexed data, clock input at 2X pixel rate
For the multiplexed data, clock at 1X pixel rate the data applied to the CH7009 is latched with both edges of
the clock (also referred to as dual-edge transfer mode). For the multiplexed data, clock at 2X pixel rate the data
applied to the CH7009 is latched with one edge of the clock. The polarity of the pixel clock can be reversed
under IIC control.
Input Clock and Data Timing Diagram
The figure below shows the timing diagram for input data and clocks. The first XCLK/XCLK* waveform
represents the input clock for the multiplexed data, clock at 2X pixel rate method. The second XCLK/XCLK*
waveform represents the input clock for the multiplexed data, clock at 1X pixel rate method.
XCLK/
XCLK*
VOH
XCLK/
XCLK*
VOH
VOL
VOL
t1 t2
VOH
D[11:0]
VOL
VOH
DE
VOL
t1
t2
VOH
H
64 P-OUT
VOL
VOH
V
1 VGA Line
VOL
Figure 5: Interface Timing
Table 4: Interface Timing
Symbol Parameter
VOH
Output high level of interface signals
VOL
Output Low level of interface signals
D[11:0], H, V & DE to XCLK = XCLK* Delay (setup
t11
Min
Max
DVDDV - 0.2
DVDDV + 0.2
Unit
V
-0.2
0.2
V
TBD
nS
TBD
nS
time)
XCLK = XCLK* to D[11:0], H, V & DE Delay (hold time)
t21
DVDDV Digital I/O Supply Voltage
1
10
1.1 – 5%
3.3 + 5%
V
D[11:0], H, V DE times measured when input equals Vref+100mV on rising edges, Vref-100mV on falling edges.
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
Input Clock and Data Formats
The 12 data inputs support 5 different multiplexed data formats, each of which can be used with a 1X clock
latching data on both clock edges, or a 2X clock latching data with a single edge. The data received by the
CH7009 can be used to drive the DVI output, the VGA to TV encoder, or directly drive the DAC’s. The
multiplexed input data formats are (IDF[2:0]):
IDF
0
1
2
3
4
Description
12-bit multiplexed RGB input (24-bit color), (multiplex scheme 1)
12-bit multiplexed RGB2 input (24-bit color), (multiplex scheme 2)
8-bit multiplexed RGB input (16-bit color, 565)
8-bit multiplexed RGB input (15-bit color, 555)
8-bit multiplexed YCrCb input (24-bit color), (Y, Cr and Cb are multiplexed)
For multiplexed input data formats, either both transitions of the XCLK/XCLK* clock pair, or each rising or
falling edge of the clock pair (depending upon MCP bit, rising refers to a rising edge on the XCLK signal, a
falling edge on the XCLK* signal) will latch data from the graphics chip. The multiplexed input data formats
are shown in the figures below. The Pixel Data bus represents a 12-bit or 8-bit multiplexed data stream, which
contains either RGB or YCrCb formatted data. The input data rate is 2X the pixel rate, and each pair of Pn
values (eg; P0a and P0b) will contain a complete pixel encoded as shown in the tables below. It is assumed
that the first clock cycle following the leading edge of the incoming horizontal sync signal contains the first
word (Pxa) of a pixel, if an active pixel was present immediately following the horizontal sync. This does not
mean that active data should immediately follow the horizontal sync, however. When the input is a YCrCb
data stream the color-difference data will be transmitted at half the data rate of the luminance data, with the
sequence being set as Cb, Y, Cr, Y, where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference
samples and the following Y1 byte refers to the next luminance sample, per CCIR-656 standards (the clock
frequency is dependent upon the current mode, and is not 27MHz as specified in CCIR-656). All non-active
pixels should be 0 in RGB formats, and 16 for Y and 128 for CrCb in YCrCb formats.
201-0000-035 Rev 1.1, 5/8/2000
11
CHRONTEL
CH7009A
HS
XCLK
(2X)
SAV
XCLK
(1X)
D[11:0]
P0a
P0b
P1a
P1b
P2a
P2b
The following data is latched for IDF = 0
P[23:16]
P0b[11:4]
P1b[11:4]
P2b[11:4]
P0b[3:0], P0a[11:8]
P1b[3:0], P1a[11:8]
P2b[3:0],
P2a[11:8]
P0a[7:0]
P1a[7:0]
P2a[7:0]
P0b[11:7], P0b[3:1]
P1b[11:7], P1b[3:1]
P2b[11:7]
P2b[3:1]
(Green Data)
P0b[6:4], P0a[11:9],
P0b[0], P0a[3]
P1b[6:4], P1a[11:9],
P1b[0], P1a[3]
P[7:0]
P0a[8:4], P0a[2:0]
P1a[8:4], P1a[2:0]
(Red Data)
P[15:8]
(Green Data)
P[7:0]
(Blue Data)
The following data is latched for IDF = 1
P[23:16]
(Red Data)
P[15:8]
(Blue Data)
P2a[8:4]
P2a[2:0]
Figure 6: Multiplexed Input Data Formats (IDF = 0, 1)
12
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
HS
XCLK
(2X)
SAV
XCLK
(1X)
D[11:0]
P0a
P0b
P1a
P1b
P2a
P2b
The following data is latched for IDF = 2
P[23:19]
P0b[11:7]
P1b[11:7]
P2b[11:7]
P1b[6:4], P1a[11:9]
P2b[6:4],
P2a[11:9]
(Red Data)
P[15:10]
P0b[6:4], P0a[11:9]
(Green Data)
P[7:3]
P0a[8:4]
P1a[8:4]
P2a[8:4]
P0b[10:6]
P1b[10:6]
P2b[10:6]
P1b[5:4], P1a[11:9]
P2b[5:4],
P2a[11:9]
(Blue Data)
The following data is latched for IDF = 3
P[23:19]
(Red Data)
P[15:11]
P0b[5:4], P0a[11:9]
(Green Data)
P[7:3]
P0a[8:4]
P1a[8:4]
P2a[8:4]
P0b[7:0]
P1b[7:0]
P2b[7:0]
P0a[7:0]
P1a[7:0]
P2a[7:0]
GND
GND
(Blue Data)
The following data is latched for IDF = 4
CRA
(internal signal)
P[23:16]
(Y Data)
P[15:8]
(CrCb Data)
P[7:0]
GND
(ignored)
Figure 7: Multiplexed Input Data Formats (IDF = 2, 3, 4)
201-0000-035 Rev 1.1, 5/8/2000
13
CHRONTEL
CH7009A
Table 5: Multiplexed Input Data Formats (IDF = 0, 1)
IDF =
Format =
Pixel #
Bus Data
0
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
P0a
G0[3]
G0[2]
G0[1]
G0[0]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
1
12-bit RGB (12-12)
P0b
P1a
R0[7]
G1[3]
R0[6]
G1[2]
R0[5]
G1[1]
R0[4]
G1[0]
R0[3]
B1[7]
R0[2]
B1[6]
R0[1]
B1[5]
R0[0]
B1[4]
G0[7]
B1[3]
G0[6]
B1[2]
G0[5]
B1[1]
G0[4]
B1[0]
P1b
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[7]
G1[6]
G1[5]
G1[4]
P0a
G0[4]
G0[3]
G0[2]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
G0[0]
B0[2]
B0[1]
B0[0]
12-bit RGB (12-12)
P0b
P1a
R0[7]
G1[4]
R0[6]
G1[3]
R0[5]
G1[2]
R0[4]
B1[7]
R0[3]
B1[6]
G0[7]
B1[5]
G0[6]
B1[4]
G0[5]
B1[3]
R0[2]
G1[0]
R0[1]
B1[2]
R0[0]
B1[1]
G0[1]
B1[0]
P1b
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
G1[7]
G1[6]
G1[5]
R1[2]
R1[1]
R1[0]
G1[1]
Table 6: Multiplexed Input Data Formats (IDF = 2, 3)
IDF =
Format =
Pixel #
Bus Data
2
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
P0a
G0[4]
G0[3]
G0[2]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
3
RGB 5-6-5
P0b
P1a
R0[7]
G1[4]
R0[6]
G1[3]
R0[5]
G1[2]
R0[4]
B1[7]
R0[3]
B1[6]
G0[7]
B1[5]
G0[6]
B1[4]
G0[5]
B1[3]
P1b
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
G1[7]
G1[6]
G1[5]
P0a
G0[5]
G0[4]
G0[3]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
RGB 5-5-5
P0b
P1a
X
G1[5]
R0[7]
G1[4]
R0[6]
G1[3]
R0[5]
B1[7]
R0[4]
B1[6]
R0[3]
B1[5]
G0[7]
B1[4]
G0[6]
B1[3]
P1b
X
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
G1[7]
G1[6]
P2b
Y2[7]
Y2[6]
Y2[5]
Y2[4]
Y2[3]
Y2[2]
Y2[1]
Y2[0]
P3b
Y3[7]
Y3[6]
Y3[5]
Y3[4]
Y3[3]
Y3[2]
Y3[1]
Y3[0]
Table 7: Multiplexed Input Data Formats (IDF = 4)
IDF =
Format =
Pixel #
Bus Data
14
4
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
P0a
Cb0[7]
Cb0[6]
Cb0[5]
Cb0[4]
Cb0[3]
Cb0[2]
Cb0[1]
Cb0[0]
P0b
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
Y0[0]
P1a
Cr0[7]
Cr0[6]
Cr0[5]
Cr0[4]
Cr0[3]
Cr0[2]
Cr0[1]
Cr0[0]
YCrCb 8-bit
P1b
P2a
Y1[7]
Cb2[7]
Y1[6]
Cb2[6]
Y1[5]
Cb2[5]
Y1[4]
Cb2[4]
Y1[3]
Cb2[3]
Y1[2]
Cb2[2]
Y1[1]
Cb2[1]
Y1[0]
Cb2[0]
P3a
Cr2[7]
Cr2[6]
Cr2[5]
Cr2[4]
Cr2[3]
Cr2[2]
Cr2[1]
Cr2[0]
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
When IDF = 4 (YCrCb mode), the data inputs can also be used to transmit sync information to the device. In
this mode, the embedded sync will follow the VIP2 convention, and the first byte of the ‘video timing
reference code’ will be assumed to occur when a Cb sample would occur, if the video stream was continuous.
This is shown below:
Table 8: Embedded Sync
IDF =
4
Format =
Pixel #
Bus Data
Dx[7]
Dx[6]
Dx[5]
Dx[4]
Dx[3]
Dx[2]
Dx[1]
Dx[0]
P0a
FF
FF
FF
FF
FF
FF
FF
FF
P0b
00
00
00
00
00
00
00
00
P1a
00
00
00
00
00
00
00
00
YCrCb 8-bit
P1b
P2a
S[7]
Cb2[7]
S[6]
Cb2[6]
S[5]
Cb2[5]
S[4]
Cb2[4]
S[3]
Cb2[3]
S[2]
Cb2[2]
S[1]
Cb2[1]
S[0]
Cb2[0]
P2b
Y2[7]
Y2[6]
Y2[5]
Y2[4]
Y2[3]
Y2[2]
Y2[1]
Y2[0]
P3a
Cr2[7]
Cr2[6]
Cr2[5]
Cr2[4]
Cr2[3]
Cr2[2]
Cr2[1]
Cr2[0]
P3b
Y3[7]
Y3[6]
Y3[5]
Y3[4]
Y3[3]
Y3[2]
Y3[1]
Y3[0]
In this mode, the S[7..0] byte contains the following data:
S[6]
=
F
=
1 during field 2, 0 during field 1
S[5]
=
V
=
1 during field blanking, 0 elsewhere
S[4]
=
H
=
1 during EAV (synchronization reference at the end of active video)
0 during SAV (synchronization reference at the start of active video)
Bits S[7] and S[3..0] are ignored
Hot Plug Detection
The CH7009 has the capability of signaling to the graphics controller when the termination of the DVI outputs
has changed. The operation of this circuit is as follows. The HPDET input pin of the CH7009 should be
connected to pin 16 of the DVI connector. When a DVI monitor is connected to the DVI connector, this pin
will be pulled high (above 2.4 volts). When a DVI monitor is not connected to the DVI connector, the internal
pull-down on the HPDET pin will pull low. The CH7009 will detect any transition at the HPDET pin. When
the HPIE (Hot Plug Interrupt Enable) bit in IIC register 1Eh is high, the CH7009 will pull low on the P-OUT /
TLDET* pin. When the HPIE2 (Hot Plug Interrupt Enable 2) bit in IIC register 20h is high, the CH7009 will
pull low on the GPIO[1] / TLDET* pin. This should signal the driver to read the DVIT bit in register 20h to
determine the state of the HPDET pin. The P-OUT / TLDET pin will continue to pull low until the driver sets
the HPIR (Hot Plug Interrupt Reset) bit in register 1Eh high. The driver should then set the HPIR bit low.
201-0000-035 Rev 1.1, 5/8/2000
15
CHRONTEL
CH7009A
Register Control
The CH7009 is controlled via an IIC control port. The IIC bus uses only the SC clock to latch data into
registers, and does not use any internally generated clocks so that the device can be written to in all power
down modes. The device retains all register states
The CH7009 contains a total of 37 registers for user control. A listing of non-Macrovision control bits is given
below with a brief description of each.
Non-Macrovision Control Registers Map
The non-Macrovision controls are listed below, divided into four sections: general controls, input / output
controls, DVI controls, and VGA to TV controls. A register map and register description follows.
GENERAL CONTROLS
ResetIB
ResetDB
PD[7:0]
VID[7:0]
DID[7:0]
TSTP[1:0]
Software IIC reset
Software datapath reset
Power down controls (DVIP, DVIL, , TVD, DACPD[1:0], Full, Partial)
Version ID register
Device ID register
Enable/select test pattern generation (color bar, ramp)
INPUT/OUTPUT CONTROLS
XCM
XCMD[7:0]
MCP
PCM
POUTP
POUTE
HPIE, HPIE2
HPIR
IDF[2:0]
IBS
DES
SYO
VSP
HSP
TERM[5:0]
BCOEN
BCO[2:0]
BCOP
GPIOL[1:0]
GOENB[1:0]
SYNCO[1:0]
DACG[1:0]
DACBP
XOSC[2:0]
16
XCLK 1X, 2X select
Delay adjust between XCLK and D[11:0]
XCLK polarity control
P-OUT 1X, 2X select
P-OUT clock polarity
P-OUT enable
Hot plug detect interrupt enable
Hot plug detect interrupt reset
Input data format
Input buffer select
Decode embedded sync (TV-Out data only)
H/V sync direction control (for TV-Out modes only)
V sync polarity control (sync polarity to DVI links is not changed)
H sync polarity control (sync polarity to DVI links is not changed)
Termination detect/check (DVI Link, DACT3, DACT2, DACT1, DACT0, SENSE)
Enable BCO Output
Select output signal for BCO pin
BCO polarity
Read or write level for GPIO pins
Direction control for GPIO pins
Enables/selects sync output for Scart and bypass modes
DAC gain control
DAC bypass
Crystal oscillator adjustments
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
DVI CONTROLS
TPPD[2:0]
TPCP[1:0]
TPVT[5:0]
TPVCO[10:0]
TPLPF[3:0]
DVID[3:0]
DVII
CTL[3:0]
DVI PLL phase detector trim
DVI PLL charge pump trim
DVI PLL VDD trim
DVI PLL VCO trim
DVI PLL low pass filter
DVI transmitter drive strength
DVI output invert
DVI control inputs
TV-OUT CONTROLS
IR[2:0]
VOS[1:0]
SR[2:0]
CFF[1:0]
YFFT[1:0]
YFFNT[1:0]
CVBWB
CBW
YSV[1:0]
YCV[1:0]
TE[2:0]
CFRB
M/S*
SAV [8:0]
BLCK[7:0]
HP[8:0]
VP[8:0]
VOF
CE[2:0]
PLLTVM[8:0]
PLLTVN[9:0]
FSCI[32:0]
CIVEN
CIVC[1:0]
CIV[25:0]
CIVPN
MEM[2:0]
VBID
PLLCPI
PLLCAP
Input data resolution (when used for TV-Out)
TV-Out video standard
TV-Out scaling ratio
Chroma flicker filter setting
Luma text enhancement flicker filter setting
Luma flicker filter setting (Non-text)
CVBS DAC receives black&white (S-Video luminance) signal
Chroma video bandwidth
S-Video luma bandwidth
Composite video luma bandwidth
Text enhancement (sharpness)
Chroma sub-carrier free run (bar) control
TV-Out PLL reference input control
Horizontal start of active video (delay from leading edge of H sync to active video)
TV-Out Black level control
TV-Out horizontal position control
TV-Out vertical position control
TV-Out video format (s-video & composite, RGB)
TV-Out contrast enhancement
TV-Out PLL M divider
TV-Out PLL N divider
Sub-carrier generation increment value (when ACIV=0)
Calculated sub-carrier enable (was called ACIV)
Calculated sub-carrier control (hysteresis,
Calculated sub-carrier increment value read out
Select PAL-N when in a CIV mode
Memory sense amp reference adjust
Vertical blanking interval defeat
TV-Out PLL charge pump current control
TV-Out PLL capacitor control
201-0000-035 Rev 1.1, 5/8/2000
17
CHRONTEL
CH7009A
I2C Port Operation
The CH7009 contains a standard I2C control port, through which the control registers can be written and read. This
port is comprised of a two-wire serial interface, pins SD (bidirectional) and SC, which can be connected directly to
the SDB and SCB buses as shown in Figure 8.
The Serial Clock line (SC) is input only and is driven by the output buffer of the master device (also shown in
Figure 8). The CH7009 acts as a slave, and generation of clock signals on the bus is always the responsibility of the
master device. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must
have an open-drain or open-collector to perform the wired-AND function. Data on the bus can be transferred up to
400 kbit/s.
+DVDD
RP
SDB (Serial Data Bus)
SCB (Serial Clock Bus)
SD
SC
DATAN2
OUT
MASTER
SCLK
OUT
FROM
MASTER
DATAN2
OUT
DATA IN
MASTER
SCLK
IN1
BUS MASTER
DATA
IN1
DATAN2
OUT
SCLK
IN2
SLAVE
DATA
IN2
SLAVE
Figure 8: Connection of Devices to the Bus
Electrical Characteristics for Bus Devices
The electrical specifications of the bus devices’ inputs and outputs and the characteristics of the bus lines connected
to them are shown in Figure 8. A pull-up resistor (RP) must be connected to a 3.3V ± 10% supply. The CH7009 is
a device with input levels related to DVDD.
Maximum and minimum values of pull-up resistor (RP)
The value of RP depends on the following parameters:
• Supply voltage
• Bus capacitance
• Number of devices connected (input current + leakage current = Iinput)
The supply voltage limits the minimum value of resistor RP due to the specified minimum sink current of 2mA at
VOLmax = 0.4 V for the output stages:
RP >= (VDD – 0.4) / 2 (R P in kΩ)
The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum
value of RP due to the specified rise time. The equation for RP is shown below:
RP <= 103/C (where: RP is in kΩ and C, the total capacitance, is in pF)
The maximum HIGH level input current of each input/output connection has a specified maximum value of 10 µA.
Due to the desired noise margin of 0.2VDD for the HIGH level, this input current limits the maximum value of RP.
The RP limit depends on VDD and is shown below:
RP <= (100 x VDD)/ Iinput (where: RP is in kΩ and Iinput is in µA)
18
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
Transfer Protocol
Both read and write cycles can be executed in “Alternating” and “Auto-increment” modes. Alternating mode
expects a register address prior to each read or write from that location (i.e., transfers alternate between address and
data). Auto-increment mode allows you to establish the initial register location, then automatically increments the
register address after each subsequent data access (i.e., transfers will be address, data...). A basic serial port transfer
protocol is shown in Figure 9 and described below.
SD
I2C
CH7009
8
Device ID
R/W*
SC
Start
Condition
9
1-8
ACK
Data1
CH7009
acknowledge
9
1-8
ACK
Data n
CH7009
acknowledge
9
ACK
CH7009
acknowledge
Stop
Condition
Figure 9: Serial Port Transfer Protocol
1. The transfer sequence is initiated when a high-to-low transition of SD occurs while SC is high; this is the
“START” condition. Transitions of address and data bits can only occur while SC is low.
2. The transfer sequence is terminated when a low-to-high transition of SD occurs while SC is high; this is the
“STOP” condition.
3. Upon receiving the first START condition, the CH7009 expects a Device Address Byte (DAB) from the
master device. The value of the device address is shown in the DAB data format below.
4. After the DAB is received, the CH7009 expects a Register Address Byte (RAB) from the master. The
format of the RAB is shown in the RAB data format below (note that B7 is not used).
Device Address Byte (DAB)
B7
B6
B5
B4
B3
B2
B1
B0
1
1
1
0
1
0
1
R/W
R/W
Read/Write Indicator
“0”:
master device will write to the CH7009 at the register location specified by the address
AR[6:0]
“1”:
master device will read from the CH7009 at the register location specified by the
address AR[6:0].
Register Address Byte (RAB)
B7
B6
B5
B4
B3
B2
B1
B0
1
AR[6]
AR[5]
AR[4]
AR[3]
AR[2]
AR[1]
AR[0]
201-0000-035 Rev 1.1, 5/8/2000
19
CHRONTEL
CH7009A
Transfer Protocols (continued)
AR[6:0]
Specifies the Address of the Register to be Accessed.
This register address is loaded into the Address Register of the CH7009. The R/W access, which
follows, is directed to the register specified by the content stored in the Address Register.
The following two sections describe the operation of the serial interface for the four combinations of R/W = 0,1 and
AutoInc and alternating operation.
CH7009 Write Cycle Protocols (R/W = 0)
Data transfer with acknowledge is required. The acknowledge-related clock pulse is generated by the mastertransmitter. The master-transmitter releases the SD line (HIGH) during the acknowledge clock pulse. The slavereceiver must pull down the SD line, during the acknowledge clock pulse, so that it remains stable LOW during the
HIGH period of the clock pulse. The CH7009 always acknowledges for writes (see Figure 10). Note that the
resultant state on SD is the wired-AND of data outputs from the transmitter and receiver.
SD Data Output
By Master-Transmitter
not acknowledge
SD Data Output
By the CH7009
acknowledge
SC from
Master
1
2
8
9
clock pulse for
acknowledgment
Start
Condition
Figure 10: Acknowledge on the Bus
Figure 11 shows two consecutive alternating write cycles. The byte of information, following the Register Address
Byte (RAB), is the data to be written into the register specified by AR[6:0]. If AutoInc = 0, then another RAB is
expected from the master device, followed by another data byte, and so on.
CH7009
acknowledge
SD
CH7009
acknowledge
CH7009
acknowledge
CH7009
acknowledge
CH7009
acknowledge
I2C
SC
Start
Condition
1-7
8
9
1-8
9
1-8
9
1-8
9
1-8
9
Device ID
R/W*
ACK
RAB
ACK
Data
ACK
RAB
ACK
Data
ACK
Stop
Condition
Note: The acknowledge is from the CH7009 (slave).
Figure 11: Alternating Write Cycles
20
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
If AutoInc = 1, then the register address pointer will be incremented automatically and subsequent data bytes will be
written into successive registers without providing an RAB between each data byte. An Auto-increment write cycle
is shown in Figure 12.
.
CH7009
acknowledge
SD
CH7009
acknowledge
CH7009
acknowledge
CH7009
acknowledge
I2C
SC
Start
Condition
1-7
8
9
1-8
9
1-8
9
1-8
9
Device ID
R/W*
ACK
RAB n
ACK
Data n
ACK
Data n+1
ACK
Stop
Condition
Note: The acknowledge is from the CH7009 (slave).
Figure 12: Auto-Increment Write Cycle
During the auto-increment mode transfers, the register address pointer continues to increment for each write cycle
until AR[6:0] = 4F. The next byte of information represents a new auto-sequencing “Starting address”, which is the
address of the register to receive the next byte. The auto-sequencing then resumes based on this new “Starting
address”. The auto-increment sequence can be terminated any time by either a “STOP” or “RESTART” condition.
The write operation can be terminated with a “STOP” condition.
CH7009 Read Cycle Protocols (R/W = 1)
If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating
an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter CH7009 releases the data
line to allow the master to generate the STOP condition or the RESTART condition.
To read the content of the registers, the master device starts by issuing a “START” condition (or a “RESTART”
condition). The first byte of data, after the START condition, is a DAB with R/W = 0. The second byte is the RAB
with AR[6:0], containing the address of the register that the master device intends to read from in AR[6:0]. The
master device should then issue a “RESTART” condition (“RESTART” = “START”, without a previous “STOP”
condition). The first byte of data, after this RESTART condition, is another DAB with R/W=1, indicating the
master’s intention to read data hereafter. The master then reads the next byte of data (the content of the register
specified in the RAB). For alternating modes, another RESTART condition, followed by another DAB with R/W =
0 and RAB, is expected from the master device. The master device then issues another RESTART, followed by
another DAB. After that, the master may read another data byte, and so on. In summary, a RESTART condition,
followed by a DAB, must be produced by the master before each of the RAB, and before each of the data read
events. Two consecutive alternating read cycles are shown in Figure 13.
201-0000-035 Rev 1.1, 5/8/2000
21
CHRONTEL
CH7009A
Transfer Protocols (continued)
.
CH7009
acknowledge
CH7009
acknowledge
CH7009
acknowledge
Master
does not
acknowledge
SD
I2C
1-7
SC
Start
Condition
I2C
9
1-8
9
ACK
RAB 1
ACK
8
Device ID R/W*
10
Restart
Condition
1-7
9
1-8
9
ACK
Data 1
ACK
8
Device ID R/W*
10
Restart
Condition
Master does
not acknowledge
CH7009
acknowledge
CH7009
acknowledge
CH7009
acknowledge
I2C
8
9
1-8
9
R/W*
ACK
RAB 2
ACK
1-7
Device ID
I2C
10
1-7
Restart Device ID
Condition
8
9
1-8
9
R/W*
ACK
Data 2
ACK
Stop
Condition
Figure 13: Alternating Read Cycle
For auto-increment reads the address register will be incremented automatically and subsequent data bytes can be
read from successive registers, without providing a second RAB.
CH7009
acknowledge
CH7009
acknowledge
CH7009
acknowledge
Master
acknowledge
Master does
not acknowledge
just before Stop
condition
SD
I2C
SC
1-7
8
Start Device ID R/W*
Condition
9
1-8
9
ACK
RAB n
ACK
10
1-7
8
Restart Device ID R/W*
Condition
9
1-8
9
1-8
9
ACK
Data n
ACK
Data
n+1
ACK
Stop
Condition
Figure 14: Auto-increment Read Cycle
When the auto-increment mode is enabled, the Address Register will continue incrementing for each read cycle.
When the content of the Address Register reaches 4Fh, it will wrap around and start from 00h again. The auto
increment sequence can be terminated by either a “STOP” or “RESTART” condition. The read operation can be
terminated with a “STOP” condition. Figure 14 shows an auto-increment read cycle terminated by a STOP or
RESTART condition.
22
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
Table 9: IIC Register Map w/o Macrovision
Register
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
31h
32h
33h
35h
36h
37h
48h
49h
4Ah
4Bh
Bit 7
IR2
VBID
Bit 6
IR1
VOF0
CFRB
Bit 5
IR0
CFF1
CVBWB
SAV8
SAV5
HP5
VP5
BL5
Bit 4
VOS1
CFF0
CBW
HP8
SAV4
HP4
VP4
BL4
Bit 3
VOS0
YFFT1
YSV1
VP8
SAV3
HP3
VP3
BL3
MEM0
M5
N5
FSCI29
FSCI21
FSCI13
FSCI5
CIV25
CIV21
CIV13
CIV5
N9
M4
N4
FSCI28
FSCI20
FSCI12
FSCI4
CIV24
CIV20
CIV12
CIV4
GPIOL1
SYO
DVIT
GPIOL0
VSP
DACT3
SYNCO1
BCOEN
TPPD0
TPVCO4
DVII
TPVT4
TPLPF0
N8
M3
N3
FSCI27
FSCI19
FSCI11
FSCI3
CIVC1
CIV19
CIV11
CIV3
M/S*
XCMD3
HPIR
HSP
DACT2
SYNCO0
BCOP
CTL3
TPVCO3
Bit 2
SR2
YFFT0
YSV0
TE2
SAV2
HP2
VP2
BL2
CE2
M8
M2
N2
FSCI26
FSCI18
FSCI10
FSCI2
CIVC0
CIV18
CIV10
CIV2
MCP
XCMD2
HPIE
IDF2
DACT1
DACG1
BCO2
CTL2
TPVCO2
SAV7
HP7
VP7
BL7
SAV6
HP6
VP6
BL6
MEM2
M7
N7
FSCI31
FSCI23
FSCI15
FSCI7
MEM1
M6
N6
FSCI30
FSCI22
FSCI14
FSCI6
CIV23
CIV15
CIV7
CIV22
CIV14
CIV6
GOENB1
IBS
HPIE2
XOSC1
SHF2
TPPD3
TPVCO7
DVID2
GOENB0
DES
XOSC2
XOSC0
SHF1
TPPD2
TPVCO6
DVID1
TPLPF3
TPVCO10
TPLPF2
TPVCO9
SHF0
TPPD1
TPVCO5
DVID0
TPVT5
TPLPF1
TPVCO8
DVIP
VID7
DID7
DVIL
VID6
DID6
TV
VID5
DID5
TPVT3
ResetDB
DACPD2
VID3
DID3
ResetIB
DACPD3
VID4
DID4
TPVT2
Bit 1
SR1
YFFNT1
YCV1
TE1
SAV1
HP1
VP1
BL1
CE1
PLLCPI
M1
N1
FSCI25
FSCI17
FSCI9
FSCI1
PALN
CIV17
CIV9
CIV1
PCM
XCMD1
POUTE
IDF1
DACT0
DACG0
BCO1
CTL1
TPVCO1
TPCP1
TPVT1
Bit 0
SR0
YFFNT0
YCV0
TE0
SAV0
HP0
VP0
BL0
CE0
PLLCAP
M0
N0
FSCI24
FSCI16
FSCI8
FSCI0
CIVEN
CIV16
CIV8
CIV0
XCM
XCMD0
POUTP
IDF0
SENSE
DACBP
BCO0
CTL0
TPVCO0
TPCP0
TPVT0
RSA
DACPD1
VID2
DID2
TSTP1
DACPD0
VID1
DID1
TSTP0
FPD
VID0
DID0
All register bits not defined in the register map are reserved bits, and should be left at the default value.
201-0000-035 Rev 1.1, 5/8/2000
23
CHRONTEL
CH7009A
Non-Macrovision Control Registers Description
Display Mode Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
Symbol:
Address:
Bits:
7
IR2
R/W
0
6
IR1
R/W
1
5
IR0
R/W
1
4
VOS1
R/W
0
3
VOS0
R/W
1
2
SR2
R/W
0
DM
00h
8
1
SR1
R/W
1
0
SR0
R/W
0
Register DM provides programmable control of the CH7009 VGA to TV display mode, including input resolution
(IR[2:0]), video output standard (VOS[1:0]), and scaling ratio (SR[2:0]). The mode of operation is determined according
to Table 10 below. For entries in which the output standard is shown as PAL, PAL-B,D,G,H,I,N,NC can be supported
through proper selection of the chroma sub-carrier. For entries in which the output standard is shown as NTSC, NTSC-M,
J and PAL-M can be supported through proper selection of VOS[1:0] and chroma sub-carrier.
Table 10: Display Mode
Mode
IR[2:0]
VOS
SR[2:0]
[1:0]
Input Data
Total Pixels/Line
Output
Format
x Total
Standard
Lines/Frame
[TV
(Active
24
000
000
000
000
001
001
001
001
010
010
010
010
010
011
011
011
011
011
011
100
100
100
101
101
101
110
110
110
110
110
110
111
111
111
111
111
111
101
100
00
00
01
01
00
00
01
01
00
00
01
01
01
00
00
00
01
01
01
01
01
01
00
00
00
00
00
00
01
01
01
00
00
00
01
01
01
00
01
000
001
000
001
000
001
000
001
000
001
000
001
010
000
001
011
001
010
011
001
010
011
001
011
100
001
011
100
110
111
101
100
101
110
101
110
111
000
000
512x384
512x384
512x384
512x384
720x400
720x400
720x400
720x400
640x400
640x400
640x400
640x400
640x400
640x480
640x480
640x480
640x480
640x480
640x480
720x480
720x480
720x480
720x576
720x576
720x576
800x600
800x600
800x600
800x600
800x600
800x600
1024x768
1024x768
1024x768
1024x768
1024x768
1024x768
720x576
720x480
Percent
Pixel Clock
Overscan
(MHz)
-17
-33
0
-20
-13
-30
+4
-16
-13
-30
+4
-17
-27
+4
-17
-30
0
-13
-18
0
-13
-18
0
-18
-30
+4
-14
-27
-6
-14
-22
-4
-16
-25
0
-10
-20
0
0
21.000000
26.250000
20.139860
24.671329
28.125000
36.000000
23.790210
29.454545
25.000000
31.500000
21.146854
26.181819
30.209791
21.000000
26.250000
31.500000
24.671329
28.195805
30.209790
27.755245
31.720280
33.986015
27.562500
33.750000
39.375000
29.500000
36.000000
42.000000
43.636364
47.832169
52.363637
61.250000
70.000000
78.750000
58.405595
65.706295
73.510491
13.500000
13.500000
Standard]
Video)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Scaling
840x500
840x625
800x420
784x525
1125x500
1152x625
945x420
936x525
1000x500
1008x625
840x420
832x525
840x600
840x500
840x625
840x750
784x525
784x600
800x630
882x525
882x600
900x630
882x625
900x750
900x875
944x625
960x750
960x875
1040x700
1064x750
1040x840
1400x875
1400x1000
1400x1125
1160x840
1160x945
1168x1050
864x625
858x525
PAL
PAL
NTSC
NTSC
PAL
PAL
NTSC
NTSC
PAL
PAL
NTSC
NTSC
NTSC
PAL
PAL
PAL
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
PAL
PAL
PAL
PAL
PAL
PAL
NTSC
NTSC
NTSC
PAL
PAL
PAL
NTSC
NTSC
NTSC
PAL
NTSC
5/4
1/1
5/4
1/1
5/4
1/1
5/4
1/1
5/4
1/1
5/4
1/1
7/8
5/4
1/1
5/6
1/1
7/8
5/6
1/1
7/8
5/6
1/1
5/6
5/7
1/1
5/6
5/7
3/4
7/10
5/8
5/7
5/8
5/9
5/8
5/9
1/2
1/1
1/1
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
Table 11: Video Output Standard Selection
VOS[1:0]
Output Format
00
PAL
01
NTSC
10
PAL-M
Flicker Filter Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
6
VOF
R/W
0
5
CFF1
R/W
1
4
CFF0
R/W
0
3
YFFT1
R/W
0
11
NTSC-J
Symbol:
FF
Address:
01h
Bits:
8
2
1
YFFT0 YFFNT1
R/W
R/W
1
1
0
YFFNT0
R/W
1
Bits 1-0 of register FF control the filter used in the scaling and flicker reduction block applied to the non-text
portion of the luminance signal as shown in Table 12 below.
Bits 3-2 of register FF control the filter used in the scaling and flicker reduction block applied to the text
portion of the luminance signal as shown in Table 12 below.
Bits 5-4 of register FF control the filter used in the scaling and flicker reduction block applied to the
chrominance signal as shown in Table 13 below. A setting of ‘11’ applies a dot crawl reduction filter which
can reduce the ‘hanging dots’ effect of an NTSC composite video signal when displayed on a TV with a comb
filter.
Table 12: Luma Flicker Filter Control
Scaling Ratio
5/4
1/1, 7/8, 5/6, 3/4, 5/7, 7/10
5/8
5/9
1/2
YFFT and YFFNT Flicker Filter Settings (lines)
00
01
10
11
2
3
3
3
2
3
4
5
2
3
4
6
3
4
5
6
3
5
5
7
Table 13: Chroma Flicker Filter Control
Scaling Ratio
5/4
1/1, 7/8, 5/6, 3/4, 5/7, 7/10
5/8
5/9
1/2
CFF Flicker Filter Settings (lines)
00
01
10
11
2
3
3
3
2
3
4
5
2
3
4
5
3
4
5
6
3
5
5
7
Bit 6 of register FF controls the video output format. A value of ‘0’ generates composite and S-Video outputs. A
value of ‘1’ generates RGB outputs.
201-0000-035 Rev 1.1, 5/8/2000
25
CHRONTEL
CH7009A
Video Bandwidth Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
VBID
R/W
0
6
5
CFRB CVBWB
R/W
R/W
0
0
4
CBW
R/W
1
3
YSV1
R/W
1
Symbol:
VBW
Address:
02h
Bits:
8
2
YSV0
R/W
1
1
YCV1
R/W
1
0
YCV0
R/W
0
Bits 1-0 of register VBW control the filter used to limit the bandwidth of the luma signal in the CVBS output signal.
A table of –3dB bandwidth values is given below.
Bits 3-2 of register VBW control the filter used to limit the bandwidth of the luma signal in the S-Video output
signal. A table of –3dB bandwidth values is given below.
Bit 4 of register VBW controls the filter used to limit the bandwidth of the chroma signal in the CVBS and S-Video
output signals. A table of –3dB bandwidth values is given in Table 14 below.
Bit 5 of register VBW controls the signal output on the CVBS pin. When this bit is low, the S-Video luminance
signal is output at both the S-Video luminance pin and the CVBS pin. This enables the output of a black and white
image on the composite output, thereby eliminating the degrading effects of the color signal (such as dot crawl and
false colors), which is useful for viewing text with high accuracy. This also allows the output of either S-Video or
CVBS using just two DAC’s. This is useful in situations where connector space is at a premium.
Table 14: Video Bandwidth
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
26
CBW
0
0.620
0.775
0.529
0.648
0.831
1.060
0.703
0.870
0.738
0.930
0.624
0.773
0.892
0.620
0.775
0.930
0.648
0.740
0.793
0.729
0.833
0.892
0.724
0.886
1.030
0.774
0.945
YSV[1:0] and YCV[1:0]
1
0.856
1.070
0.730
0.894
1.150
1.470
0.970
1.200
1.020
1.280
0.862
1.070
1.230
0.856
1.070
1.280
0.894
1.020
1.100
1.010
1.150
1.230
0.999
1.220
1.430
1.070
1.310
00
2.300
2.880
1.960
2.410
3.080
3.950
2.610
3.230
2.740
3.460
2.320
2.870
3.310
2.300
2.880
3.460
2.410
2.750
2.950
2.710
3.090
3.310
2.690
3.290
3.840
2.880
3.510
01
2.690
3.360
2.290
2.810
3.600
4.610
3.040
3.770
3.200
4.030
2.710
3.350
3.870
2.690
3.360
4.030
2.810
3.210
3.440
3.160
3.610
3.870
3.140
3.840
4.480
3.360
4.100
10
11
3.540
5.880
4.430
7.350
3.020
5.010
3.700
6.140
4.750
7.870
6.080
10.100
4.010
6.660
4.970
8.240
4.220
7.000
5.320
8.820
3.570
5.920
4.420
7.330
5.100
8.450
3.540
5.880
4.430
7.350
5.320
8.820
3.700
6.140
4.230
7.010
4.530
7.510
4.160
6.900
4.760
7.890
5.100
8.450
4.130
6.860
5.060
8.400
5.910
9.790
4.430
7.340
5.400
8.960
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
Table 14: Video Bandwidth
27
28
29
30
31
32
33
34
35
36
37
38
1.100
0.859
0.942
1.030
0.804
0.919
1.030
0.767
0.862
0.965
0.709
0.466
1.520
1.190
1.300
1.420
1.110
1.270
1.430
1.060
1.190
1.330
0.979
0.643
4.100
3.190
3.500
3.830
2.990
3.410
3.840
2.850
3.200
3.580
2.630
1.730
4.780
3.720
4.080
4.470
3.480
3.980
4.480
3.320
3.740
4.180
3.070
2.020
6.300
4.910
5.380
5.890
4.590
5.250
5.910
4.380
4.930
5.510
4.050
2.660
10.400
8.140
8.920
9.770
7.620
8.710
9.790
7.260
8.170
9.140
6.720
4.410
Bit 6 of register VBW controls whether the chroma sub-carrier free-runs, or is locked to the video signal. A ‘1’
causes the sub-carrier to lock to the TV vertical rate, and should be used when the CIVEN bit (register 10h) is
set to ‘0’. A ‘0’ causes the sub-carrier to free-run, and should be used when the CIVEN bit is set to ‘1’.
Bit 7 of register VBW controls the vertical blanking interval defeat function. A ‘1’ in this register location
forces the flicker filter to minimum filtering during the vertical blanking interval. A ‘0’ in this location causes
the flicker filter to remain at the same setting inside and outside of the vertical blanking interval.
Text Enhancement Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
6
5
SAV8
R/W
0
4
HP8
R/W
0
3
VP8
R/W
0
Symbol:
TE
Address:
03h
Bits:
6
2
TE2
R/W
1
1
TE1
R/W
0
0
TE0
R/W
1
Bits 2-0 of register TE control the text enhancement circuitry within the CH7009. A value of ‘000’ minimizes the
enhancement feature, while a value of ‘111’ maximizes the enhancement.
Bits 5-3 of register TE contain the MSB values for the start of active video, horizontal position and vertical position
controls. They are described in detail in the SAV, HP and VP register descriptions.
201-0000-035 Rev 1.1, 5/8/2000
27
CHRONTEL
CH7009A
Start of Active Video Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
SAV7
R/W
0
6
SAV6
R/W
1
5
SAV5
R/W
0
4
SAV4
R/W
1
3
SAV3
R/W
0
Symbol:
SAV
Address:
04h
Bits:
8
2
SAV2
R/W
0
1
SAV1
R/W
0
0
SAV0
R/W
0
Register SAV controls the delay, in pixel increments, from leading edge of horizontal sync to start of active video.
The entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus the MSB value contained in the Text
Enhancement register, bit SAV8. This is decoded as a whole number of pixels, which can be set anywhere between
0 and 511 pixels. Therefore, in any 2X clock mode the number of 2X clocks from the leading edge of sync to the
first active data must be a multiple of two clocks.
Horizontal Position Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
HP7
R/W
0
6
HP6
R/W
1
5
HP5
R/W
0
4
HP4
R/W
1
3
HP3
R/W
0
Symbol:
HP
Address:
05h
Bits:
8
2
HP2
R/W
0
1
HP1
R/W
0
0
HP0
R/W
0
Register HP is used to shift the displayed TV image in a horizontal direction ( left or right) to achieve a horizontally
centered image on screen. The entire bit field, HP[8:0], is comprised of this register HP[7:0] plus the MSB value
contained in the Text Enhancement register, bit HP8. Increasing values move the displayed image position right, and
decreasing values move the image position left.
Vertical Position Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
VP7
R/W
0
6
VP6
R/W
0
5
VP5
R/W
0
4
VP4
R/W
0
3
VP3
R/W
0
Symbol:
VP
Address:
06h
Bits:
8
2
VP2
R/W
0
1
VP1
R/W
0
0
VP0
R/W
0
Register VP is used to shift the displayed TV image in a vertical direction ( up or down) to achieve a vertically
centered image on screen. The entire bit field, VP[8:0], is comprised of this register HP[7:0] plus the MSB value
contained in the Text Enhancement register, bit VP8. The value represents the TV line number (relative to the VGA
vertical sync) used to initiate the generation and insertion of the TV vertical interval (i.e. the first sequence of
equalizing pulses). Increasing values delay the output of the TV vertical sync, causing the image position to move
up on the TV screen. Decreasing values, therefore, move the image position DOWN. Each increment moves the
image position by one TV lines (approximately 2 input lines). The maximum value that should be programmed
into the VP[8:0] value is the number of TV lines per field minus one half (262 or 312). When panning the image up,
the number should be increased until (TVLPF-1/2) is reached, the next step should be to reset the register to zero.
When panning the image down the screen, decrement the VP[8:0] value until the value zero is reached. The next
step should set the register to TVLPF-1/2, and then decrement for further changes.
28
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
Black Level Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
BL7
R/W
1
6
BL6
R/W
0
5
BL5
R/W
0
4
BL4
R/W
0
3
BL3
R/W
0
Symbol:
BL
Address:
07h
Bits:
8
2
BL2
R/W
0
1
BL1
R/W
1
0
BL0
R/W
1
Register BL controls the black level. The luminance data is added to this black level, which must be set between 51
and 208. When the input data format is zero through three the default values are 131 for NTSC and PAL-M, 110 for
PAL and 102 for NTSC-J. When the input data format is four the default values are 112 for NTSC and PAL-M, 94
for PAL and 88 for NTSC-J.
Contrast Enhancement Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
6
5
4
3
Symbol:
CE
Address:
08h
Bits:
3
2
CE2
R/W
0
1
CE1
R/W
1
0
CE0
R/W
1
Bits 2-0 of register CE control contrast enhancement feature of the CH7009, according to the figure below. A
setting of ‘0’ results in reduced contrast, a setting of ‘1’ leaves the image contrast unchanged, and values beyond ‘1’
result in increased contrast.
512
444
376
308
<i >
Yout n
240
256
172
104
36
32
32
36
104
172
240
308
376
444
512
Yin
n
Figure 15: Contrast Enhancement diagram
201-0000-035 Rev 1.1, 5/8/2000
29
CHRONTEL
CH7009A
TV PLL Control Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
MEM2
R/W
1
6
MEM1
R/W
0
5
IBI
R/W
0
4
N9
R/W
0
3
N8
R/W
0
Symbol:
TPC
Address:
09h
Bits:
5
2
M8
R/W
0
1
PLLCPI
R/W
0
0
PLLCAP
R/W
0
Bit 0 of register TPC controls the TV PLL loop filter capacitor. A recommended listing of PLLCAP setting versus
mode is listed in Table 15 below.
Table 15: PLLCAP setting vs Display Mode
Mode
PLLCAP
Mode
PLLCAP
Value
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Value
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
0
0
1
1
1
0
1
1
1
0
1
1
1
1
0
0
0
1
1
Bit 1 of register TPC should be left at the default value.
Bits 4-2 of register TPC contain the MSB values for the TV PLL divider ratio’s. These controls are described in
detail in the PLLM and PLLN register descriptions.
Bit 5 of register TPC controls the input latch bias current. A value of TBD is recommended.
Bits 7-6 of register TPC control the memory sense amp reference level. The default value is recommended.
30
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
TV PLL M Value Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
M7
R/W
0
6
M6
R/W
0
5
M5
R/W
1
4
M4
R/W
1
3
M3
R/W
1
Symbol:
PLLM
Address:
0Ah
Bits:
8
2
M2
R/W
1
1
M1
R/W
1
0
M0
R/W
1
Register PLLM controls the division factor applied to the 14.31818MHz frequency reference clock before it is input
to the TV PLL phase detector when the CH7009 is operating in master clock mode. The entire bit field, M[8:0], is
comprised of this register M[7:0] plus the MSB value contained in the TV PLL Control register, bit M8. In slave
clock mode, an external pixel clock is used instead of the 14.31818MHz frequency reference, and the division factor
is determined by the XCM value in register 1Dh. A table of values versus display mode is given following the
PLLN register description
TV PLL N Value Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
N7
R/W
0
6
N6
R/W
1
5
N5
R/W
1
4
N4
R/W
1
3
N3
R/W
1
Symbol:
PLLN
Address:
0Bh
Bits:
8
2
N2
R/W
1
1
N1
R/W
1
0
N0
R/W
0
Register PLLN controls the division factor applied to the VCO output before being applied to the PLL phase
detector, when the CH7009 is operating in master clock mode. The entire bit field, N[9:0], is comprised of this
register N[7:0] plus the MSB values contained in the TV PLL Control register, bits N9 and N8. In slave clock
mode, the value of ‘N’ is internally set to 1. The pixel clock generated in master clock modes is calculated
according to the equation Fpixel = Fref * [(N+2) / (M+2)]. When using a 14.31818MHz frequency reference, the
required M and N values for each mode are shown in Table 16 below:
Table 16: TV PLL M and N values vs Display Mode
Mode
VGA Resolution,
TV Standard,
Scaling Ratio
0
512x384, PAL, 5:4
1
512x384, PAL, 1:1
2
512x384, NTSC, 5:4
3
512x384, NTSC, 1:1
4
720x400, PAL, 5:4
5
720x400, PAL, 1:1
6
720x400, NTSC, 5:4
7
720x400, NTSC, 1:1
8
640x400, PAL, 5:4
9
640x400, PAL, 1:1
10
640x400, NTSC, 5:4
11
640x400, NTSC, 1:1
12
640x400, NTSC, 7:8
13
640x480, PAL, 5:4
14
640x480, PAL, 1:1
15
640x480, PAL, 5:6
16
640x480, NTSC, 1:1
17
640x480, NTSC, 7:8
18
640x480, NTSC, 5:6
19
720x480, NTSC, 1:1
201-0000-035 Rev 1.1, 5/8/2000
N
M
10-
9-bits
Mode
TV Standard,
Scaling Ratio
bits
20
9
126
110
53
86
106
70
108
9
94
62
190
20
9
9
110
126
190
124
VGA Resolution,
13
4
89
63
26
33
63
33
61
3
63
33
89
13
4
3
63
63
89
63
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
720x480, NTSC, 7:8
720x480, NTSC, 5:6
720x480, PAL, 1:1
720x480, PAL, 5:6
720x480, PAL, 5:7
800x600, PAL, 1:1
800x600, PAL, 5:6
800x600, PAL, 5:7
800x600, NTSC, 3:4
800x600, NTSC, 7:10
800x600, NTSC, 5/8
1024x768, PAL, 5:7
1024x768, PAL, 5:8
1024x768, PAL, 5:9
1024x768, NTSC, 5:8
1024x768, NTSC, 5:9
1024x768, NTSC, 1:2
720x576, PAL, 1:1
720x480, NTSC, 1:1
N
M
10-
9-bits
bits
142
214
75
31
9
647
86
42
62
302
126
75
42
20
565
333
917
31
31
63
89
38
12
2
313
33
13
19
89
33
16
7
2
137
71
177
33
33
31
CHRONTEL
CH7009A
Sub-carrier Value Register
Symbol:
FSCI
Address:
0Ch –
0Fh
Bits:
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
FSCI#
R/W
6
FSCI#
R/W
5
FSCI#
R/W
4
FSCI#
R/W
3
FSCI#
R/W
2
FSCI#
R/W
8 each
1
FSCI#
R/W
0
FSCI#
R/W
Registers FSCI contain a 32-bit value which is used as an increment value for the ROM address generation circuitry when
CIVEN=0. The bit locations are specified as follows:
Register
0Ch
0Dh
0Eh
0Fh
Contents
FSCI[31:24]
FSCI[23:16]
FSCI[15:8]
FSCI[7:0]
When the CH7009 is used in the master clock mode, the tables below should be used to set the FSCI registers.
When using these values, the CIVEN bit in register 10h should be set to ‘0’, and the CFRB bit in register 02h should
be set to ‘1’.
Table 17: FSCI Values (525-Line TV-Out Modes)
Mode
NTSC
NTSC
PAL-M
2
3
6
7
10
11
12
16
17
18
19
20
21
28
29
30
34
35
36
38
“Normal Dot Crawl”
763,363,328
623,153,737
574,429,782
463,962,517
646,233,505
521,957,831
452,363,454
623,153,737
545,259,520
508,908,885
553,914,433
484,675,129
452,363,454
469,762,048
428,554,851
391,468,373
526,457,468
467,962,193
418,281,276
569,408,543
“No Dot Crawl”
763,366,524
623,156,346
574,432,187
463,964,459
646,236,211
521,960,019
452,365,347
623,156,346
545,261,803
508,911,016
553,916,752
484,677,158
452,365,347
469,764,015
428,556,645
391,470,012
526,459,671
467,964,152
418,283,027
569,410,927
“Normal Dot Crawl”
762,524,467
622,468,953
573,798,541
463,452,668
645,523,358
521,384,251
451,866,351
622,468,953
544,660,334
508,349,645
553,305,736
484,142,519
451,866,351
469,245,826
428,083,911
391,038,188
525,878,943
467,447,949
417,821,626
568,782,819
32
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
Table 18: FSCI Values (625-Line TV-Out Modes)
Mode
PAL
PAL-N
0
1
4
5
8
9
13
14
15
22
23
24
25
26
27
31
32
33
37
“Normal Dot Crawl”
806,021,060
644,816,848
601,829,058
470,178,951
677,057,690
537,347,373
806,021,060
644,816,848
537,347,373
690,875,194
564,214,742
483,612,636
645,499,916
528,951,320
453,386,846
621,787,675
544,064,215
483,612,636
705,268,427
“Normal Dot Crawl”
651,209,077
520,967,262
486,236,111
379,871,962
547,015,625
434,139,385
651,209,077
520,967,262
434,139,385
558,179,209
455,846,354
390,725,446
521,519,134
427,355,957
366,305,106
502,361,288
439,566,127
390,725,446
569,807,942
CIV Control Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
6
5
CIV25
R/W
0
4
CIV24
R/W
0
3
CIVC1
R/W
0
Symbol:
CIVC
Address:
10h
Bits:
6
2
CIVC0
R/W
0
1
PALN
R/W
0
0
CIVEN
R/W
1
Bit 0 of register CIVC controls whether the FSCI value is used to set the sub-carrier frequency, or the automatically
calculated (CIV) value. When the CIVEN value is 1, the number calculated and present at the CIV registers will
automatically be used as the increment value for sub-carrier generation. Whenever this bit is set to 1, the CFRB bit
should be set to 0. It is recommended to use the FSCI registers, and not the CIVEN mode for Macrovision
applications
Bit 1 of register CIVC forces the CIV algorithm to generate the PAL-N (Argentina) sub-carrier frequency when it is
set to ‘1’. When this bit is set to ‘0’, the VOS[1:0] value is used by the CIV algorithm to determine which subcarrier frequency to generate.
Bits 3-2 of register CIVC control the hysteresis circuit which is used to calculate the CIV value. The default value
should be used.
Bits 5-4 of register CIVC contain the MSB values for the calculated increment value (CIV) readout. This is
described in detail in the CIV register description.
201-0000-035 Rev 1.1, 5/8/2000
33
CHRONTEL
CH7009A
Calculated Increment Value Register
Symbol:
CIV
Address:
11h –
13h
Bits:
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
CIV#
R/W
0
6
CIV#
R/W
0
5
CIV#
R/W
0
4
CIV#
R/W
0
3
CIV#
R/W
0
2
CIV#
R/W
0
8 each
1
CIV#
R/W
0
0
CIV#
R/W
0
Registers CIV contain the value that was calculated by the CH7009 as the sub-carrier increment value. The entire
bit field, CIV[25:0], is comprised of these three registers plus the MSB values contained in the CIV Control register,
bits CIV25 and CIV24. This value is used when the CIVEN bit is set to ‘1’. The bit locations are specified below.
Register Contents
10hCIV[25:24]
11hCIV[23:16]
12hCIV[15:8]
13hCIV[7:0]
Clock Mode Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
6
5
4
3
M/S*
R/W
0
Symbol:
CM
Address:
1Ch
Bits:
4
2
MCP
R/W
0
1
PCM
R/W
0
0
XCM
R/W
0
Bit 0 of register CM signifies the XCLK frequency. A value of ‘0’ is used when the XCLK is at the pixel frequency
(duel edge clocking mode) and a value of ‘1’ is used when the XCLK is twice the pixel frequency (single edge
clocking mode).
Bit 1 of register CM controls the P-OUT clock frequency. A value of ‘0’ generates a clock output at the pixel
frequency, while a value of ‘1’ generates a clock at twice the pixel frequency.
Bit 2 of register CM controls the phase of the XCLK clock input to the CH7009. A value of ‘1’ inverts the XCLK
signal at the input of the device. This control is used to select which edge of the XCLK signal to use for latching
input data.
Bit 3 of register CM controls whether the device operates in master or slave clock mode. In master mode (M/S* =
‘1’), the 14.31818MHz clock is used as a frequency reference in the TV PLL, and the M and N values are used to
determine the TV PLL’s operating frequency. In slave mode (M/S* = ‘0’) the XCLK input is used as a reference to
the TV PLL. The M and N TV PLL divider values are forced to one.
34
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
Input Clock Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
Symbol:
IC
Address:
1Dh
Bits:
8
7
6
5
4
3
2
1
Reserved Reserved Reserved Reserved XCMD3 XCMD2 XCMD1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
1
0
0
0
XCMD0
R/W
0
Bits 3-0 of register IC controls the delay applied to the XCLK signal before latching input data.
GPIO Control Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
6
5
4
GOENB1 GOENB0 GPIOL1 GPIOL0
R/W
R/W
R/W
R/W
1
1
0
0
3
HPIR
R/W
0
Symbol:
GPIO
Address:
1Eh
Bits:
8
2
HPIE
R/W
0
1
POUTE
R/W
0
0
POUTP
R/W
0
Bit 0 of register GPIO controls the polarity of the P-OUT signal. A value of ‘0’ does not invert the clock at the
output pad.
Bit 1 of register GPIO enables the P-OUT signal. A value of ‘1’ drives the P-OUT clock signal out of the
P-OUT / TLDET* pin. A value of ‘0’ disables the P-OUT signal.
Bit 2 of register GPIO enables the hot plug interrupt detection signal to be output from the P-OUT pin. A value of
‘1’ allows the hot plug detect circuit to pull the P-OUT / TLDET* pin low when a change of state has taken place on
the hot plug detect pin. A value of ‘0’ disables the interrupt signal. The two control bits HPIE and POUTE should
not be enabled (set to ‘1’) at the same time.
Bit 3 of register GPIO resets the hot plug detection circuitry. A value of ‘1’ causes the CH7009 to release the
P-OUT / TLDET* pin. When a hot plug interrupt is asserted by the CH7009 (P-OUT / TLDET) the CH7009 driver
should read register 20h to determine the state of the DVI termination. After having read this register, the HPIR bit
should be set high to reset the circuitry, and then set low again.
Bits 5-4 of register GPIO control the GPIO pins. When the corresponding GOENB bits are low, these register
values are driven out of the corresponding GPIO pins. When the corresponding GOENB bits are high, these register
values can be read to determine the level forced into the corresponding GPIO pins.
Bits 7-6 of register GPIO control the direction of the GPIO pins. A value of ‘1’ sets the corresponding GPIO pin to
an input, and a value of ‘0’ sets the corresponding pin to an output.
201-0000-035 Rev 1.1, 5/8/2000
35
CHRONTEL
CH7009A
Input Data Format Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
IBS
R/W
0
6
DES
R/W
0
5
SYO
R/W
0
4
VSP
R/W
0
3
HSP
R/W
0
Symbol:
IDF
Address:
1Fh
Bits:
8
2
IDF2
R/W
0
1
IDF1
R/W
0
0
IDF0
R/W
0
Bits 2-0 of register IDF select the input data format. See Input Interface on page 10 for a listing of available
formats.
Bit 3 of register IDF controls the horizontal sync polarity. A value of ‘0’ defines the horizontal sync to be active
low, and a value of ‘1’ defines the horizontal sync to be active high.
Bit 4 of register IDF controls the vertical sync polarity. A value of ‘0’ defines the vertical sync to be active low, and
a value of ‘1’ defines the vertical sync to be active high.
Bit 5 of register IDF controls the sync direction. A value of ‘0’ defines sync to be input to the CH7009, and a value
of ‘1’ defines sync to be output from the CH7009. The CH7009 can only output sync signals when operating as a
VGA to TV encoder, not when operating as a DVI transmitter.
Bit 6 of register IDF signifies when the CH7009 is to decode embedded sync signals present in the input data stream
instead of using the H and V pins. This feature is only available for input data format four. A value of ‘0’ selects the
H and V pins to be used as the sync inputs, and a value of ‘1’ selects the embedded sync signal.
Bit 7 of register IDF selects the input buffer used for the data, sync and clock input pins.
Connection Detect Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
6
HPIE2 Reserved
R/W
R/W
0
0
5
DVIT
R
0
4
DACT3
R
0
3
DACT2
R
0
Symbol:
CD
Address:
20h
Bits:
6
2
DACT1
R
0
1
DACT0
R
0
0
SENSE
R/W
0
The Connection Detect Register provides a means to sense the connection of a TV to the four DAC outputs, and to
determine the status of the DVI hot plug detect pin. The status bits, DACT[3:0] correspond to the termination of the
four DAC outputs. However, the values contained in these STATUS BITS ARE NOT VALID until a sensing
procedure is performed. Use of this register requires a sequence of events to enable the sensing of outputs, then
reading out the applicable status bits. The detection sequence works as follows:
1) Set the power management register to enable all DAC’s.
2) Set the SENSE bit to a 1. This forces a constant output from the DAC’s. Note that during SENSE = 1, these 4
analog outputs are at steady state and no TV synchronization pulses are asserted.
3) Reset the SENSE bit to 0. This triggers a comparison between the voltage present on these analog outputs and
the reference value. During this step, each of the four status bits corresponding to individual DAC outputs will be
set if they are NOT CONNECTED.
4) Read the status bits. The status bits, DACT[3:0] now contain valid information which can be read to determine
which outputs are connected to a TV. Again, a “0” indicates a valid connection, a “1” indicates an unconnected
output.
36
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
Bit 5 of register CD can be read at any time to determine the level of the hot plug detect pin. When the hot plug
detect pin changes state, and the DVI output is selected, the P-OUT / TLDET* output pin will be pulled low
signifying a change in the DVI termination. At this point, the HPIR bit in register 1Eh should be set high, then low
to reset the hot plug detect circuit.
Bit 6 of register CD contains the MSB value for the crystal oscillator adjustment. This control is described in detail
in the DC register description (register 21h).
Bit 7 of register CD enables the hot plug interrupt detection signal output from the GPIO[1] pin. A value of ‘1’
allows the hot plug detect circuit to pull the GPIO[1] / TLDET* pin low when a change of state has taken place on
the hot plug detect pin. A value of ‘0’ disables the interrupt signal. The GOENB1 control bit in register 1Eh should
be set to ‘1’ when HPIE2 is set to ‘1’.
DAC Control Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
XOSC1
R/W
0
6
XOSC0
R/W
0
5
4
3
SYNCO1 SYNCO0
R/W
R/W
0
0
Symbol:
DC
Address:
21h
Bits:
6
2
DACG1
R/W
0
1
DACG0
R/W
0
0
DACBP
R/W
0
Bit 0 of register DC selects the DAC bypass mode. A value of ‘1’ outputs the incoming data directly at the
DAC[2:0] outputs.
Bits 2-1 of register DC control the DAC gain. DACG0 should be set low for NTSC and PAL-M video standards,
and high for PAL and NTSC-J video standards. DACG1 should be low when the input data format is RGB (IDF =
0-3), and high when the input data format is YCrCb (IDF = 4).
Bits 4-3 of register DC select the signal to be output from the C/H Sync pin according to Table 19 below.
Table 19: Composite / Horizontal Sync Output
SYNCO[1:0]
00
01
10
11
C/H Sync Output
No Output
VGA Horizontal Sync
TV Composite Sync
TV Horizontal Sync
Bits 7-6 of register DC controls the crystal oscillator. The default value is recommended.
201-0000-035 Rev 1.1, 5/8/2000
37
CHRONTEL
CH7009A
Buffered Clock Output Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
SHF2
R/W
0
6
SHF1
R/W
0
5
SHF0
R/W
0
4
BCOEN
R/W
0
3
BCOP
R/W
0
Symbol:
BCO
Address:
22h
Bits:
8
2
BCO2
R/W
0
1
BCO1
R/W
0
0
BCO0
R/W
0
Bits 2-0 of register BCO select the signal output at the BCO pin, according to Table 20 below:
Table 20: BCO Output Signal
BCO[2:0]
000
001
010
011
Buffered Clock Output
The 14MHz crystal
(for test use only)
VCO divided by K3
Field ID
BCO[2:0]
100
101
110
111
Buffered Clock Output
(for test use only)
(for test use only)
VGA Vertical Sync
TV Vertical Sync
Bit 3 of register BCO selects the polarity of the BCO output. A value of ‘1’ does not invert the signal at the output
pad.
Bit 4 of register BCO enables the BCO output. When BCOEN is high, the BCO pin will output the selected signal.
When BCOEN is low, the BCO pin will be held in tri-state mode.
Bits 7-5 of register BCO select the K3 divider, according to Table 21 below.
Table 21: K3 Selection
SHF[2:0]
000
001
010
011
100
101
110
111
K3
2.5
3.0
3.5
4.0
4.5
5.0
6.0
7.0
DVI Control Input Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
TPPD3
R/W
1
6
TPPD 2
R/W
0
5
TPPD 1
R/W
0
4
TPPD 0
R/W
0
3
CTL3
R/W
0
Symbol:
TCTL
Address:
31h
Bits:
8
2
CTL2
R/W
0
1
CTL1
R/W
0
0
CTL0
R/W
0
Bits 3-0 of register TCTL set the DVI control inputs applied to the green and red channels during sync intervals. It
is recommended to leave these controls at the default value.
Bits 7-4 of register TCTL control the DVI PLL phase detector. The default value is recommended.
38
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
DVI PLL VCO Control Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
Symbol:
TVCO
Address:
32h
Bits:
8
7
6
5
4
3
2
1
TPVCO7 TPVCO6 TPVCO5 TPVCO4 TPVCO3 TPVCO2 TPVCO1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
0
0
0
0
0
TPVCO0
R/W
0
Register TVCO controls the state of the DVI PLL VCO, and should be set according to the following tables (TBD).
DVI PLL Charge Pump Control Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
DVID2
R/W
1
6
DVID1
R/W
1
5
DVID0
R/W
1
Symbol:
TPCP
Address:
33h
Bits:
5
4
3
2
DVII Reserved Reserved
R/W
R/W
R/W
0
0
1
1
TPCP1
R/W
0
0
TPCP0
R/W
0
Bits 1-0 of register TPCP control the DVI PLL charge pump. The default value is recommended.
Bits 3-2 of register TPCP are reserved bits, and should be left at the default value.
Bit 4 of register TPCP inverts the DVI outputs. A value of 1 inverts the outputs. A value of 0 is recommended.
Bits 7-5 of register TPCP control the DVI transmitter output drive level. The default value is recommended for DVI
applications.
DVI PLL Supply Control Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
6
Reserved Reserved
R/W
R/W
0
0
5
TPVT5
R/W
1
4
TPVT4
R/W
1
3
TPVT3
R/W
0
Symbol:
TPVT
Address:
35h
Bits:
5
2
TPVT2
R/W
0
1
TPVT1
R/W
0
0
TPVT0
R/W
0
Bits 5-0 of register TPVT control the DVI PLL supply voltage. The default value is recommended.
Bits 7-6 of register TPVT are reserved bits, and should be left at the default value.
201-0000-035 Rev 1.1, 5/8/2000
39
CHRONTEL
CH7009A
DVI PLL Filter Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
TPLPF3
R/W
0
6
TPLPF2
R/W
0
5
TPLPF1
R/W
0
Symbol:
TPF
Address:
36h
Bits:
8
4
3
2
1
TPLPF0 Reserved Reserved Reserved
R/W
R/W
R/W
R/W
0
0
0
0
0
Reserved
R/W
0
Bits 3-0 of register TPT are reserved bits, and should be left at the default value.
Bits 7-4 of register TPT control the DVI PLL low pass filter. The default value is recommended.
DVI PLL VCO Control Overflow Register
BIT:
7
SYMBOL: TPVCO10
TYPE:
R/W
DEFAULT:
0
Symbol:
TVCOO
Address:
37h
Bits:
8
6
5
4
3
2
1
TPVCO9 TPVCO8 Reserved Reserved Reserved Reserved
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Reserved
R/W
0
Bits 4-0 of register TCT are reserved bits, and should be left at the default value.
Bits 7-5 of register TCT contain the MSB values for the DVI PLL VCO control. This control is described in detail
in the TVCO register description.
Test Pattern Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
6
5
4
3
ResetIB ResetDB
R/W
R/W
1
1
Symbol:
TSTP
Address:
48h
Bits:
5
2
RSA
R/W
0
1
TSTP1
R/W
0
0
TSTP0
R/W
0
Bits 1-0 of register TSTP control the test pattern generation block. This test pattern can be used for both the DVI
output and the TV Output. The pattern generated is determined by Table 22 below.
Table 22: Test Pattern Control
TSTP[1:0]
00
01
1X
40
Buffered Clock Output
No test pattern – Input data is used
Color Bars
Horizontal Luminance Ramp
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
Bit 2 of register TSTP is a test control, and should be left at the default value.
Bit 3 of register TSTP controls the datapath reset signal. A value of ‘0’ holds the datapath in a reset condition,
while a value of ‘1’, places the datapath in normal mode. The datapath is also reset at power on by an internally
generated power on reset signal.
Bit 4 of register TSTP controls the IIC reset signal. A value of ‘0’ holds the IIC registers in a reset condition, while
a value of ‘1’, places the IIC registers in normal mode. The IIC registers are also reset at power on by an internally
generated power on reset signal.
Power Management Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
DVIP
R/W
0
6
DVIL
R/W
0
Symbol:
PM
Address:
49h
Bits:
8
5
4
3
2
1
TV DACPD3 DACPD2 DACPD1 DACPD0
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
FPD
R/W
1
Register PM controls which circuitry within the CH7009 is operating, according to Table 23 below.
Table 23: Power Management
Circuit Block
DVI PLL
DVI Encode, Serialize and
Is Operational When
DVIP = 1 & FPD = 0
DVIL = 1 & FPD = 0
Transmitter
VGA to TV Encoder
DAC 3
DAC 2
DAC 1
DAC 0
TV PLL, P-OUT and BCO pins
TV = 1 & FPD = 0
DACPD3 = 0 & FPD = 0
DACPD2 = 0 & FPD = 0
DACPD1 = 0 & FPD = 0
DACPD0 = 0 & FPD = 0
FPD = 0
Version ID Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
VID7
R
MV
6
VID6
R
0
5
VID5
R
0
4
VID4
R
0
3
VID3
R
0
Symbol:
VID
Address:
4Ah
Bits:
8
2
VID2
R
0
1
VID1
R
0
0
VID0
R
0
Register VID is a read only register containing the version ID number of the CH7009. The MV default is ‘1’ when
the CH7009 is bonded out with Macrovision enabled, and ‘0’ when the CH7009 is bonded out with Macrovision
disabled.
201-0000-035 Rev 1.1, 5/8/2000
41
CHRONTEL
CH7009A
Device ID Register
BIT:
SYMBOL:
TYPE:
DEFAULT:
7
DID7
R
0
6
DID6
R
0
5
DID5
R
0
4
DID4
R
1
3
DID3
R
0
Symbol:
DID
Address:
4Bh
Bits:
8
2
DID2
R
1
1
DID1
R
1
0
DID0
R
1
Register DID is a read only register containing the device ID number of the CH7009.
42
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
Electrical Specifications
Table 24. Absolute Maximum Ratings
Symbol
Description
DVDD, AVDD, TVDD, VDD relative to GND
1
Input voltage of all digital pins
TSC
Min
Typ
Max
Units
- 0.5
5.0
V
GND - 0.5
VDD + 0.5
V
Indefinite
Analog output short circuit duration
Sec
TAMB
Ambient operating temperature
- 55
85
°C
TSTOR
Storage temperature
- 65
150
°C
TJ
Junction temperature
150
°C
Vapor phase soldering (one minute)
220
°C
TVPS
Notes:
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the
device. These are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated under the normal operating condition of this specification is not recommended.
Exposure to absolute maximum rating conditions for extended periods my affect reliability.
2. The device is fabricated using high-performance CMOS technology. It should be handled as an ESD
sensitive device. Voltage on any signal pin that exceeds the power supply voltages by more than ± 0.5V can
induce destructive latch.
Table 25. Recommended Operating Conditions
Symbol
VDD
Description
Min
Typ
Max
Units
DAC power supply voltage
3.1
3.3
3.6
V
AVDD
Analog supply voltage
3.1
3.3
3.6
V
DVDD
Digital supply voltage
3.1
3.3
3.6
V
Digital supply voltage (P-OUT pin)
1.1
1.8
3.6
V
TVDD,
DVDDV
RL
Output load to DAC outputs
Ω
37.5
Table 26. Electrical Characteristics (Operating Conditions: TA = 0oC - 70oC, VDD = 5V ± 5%)
Video D/A resolution
Full scale output current
10
10
10
33.89
mA
10
Video level error
Bits
%
VDD & AVDD current (simultaneous S-Video & 2
composite outputs)
150
mA
DVDD, TVDD (3.3V) current
TBD
mA
4
mA
DVDD2 (1.8V) current (15pF load)
201-0000-035 Rev 1.1, 5/8/2000
43
CHRONTEL
CH7009A
P-OUTP-OUT
Table 27. Digital Inputs / Outputs
Symbol
Description
Max
Unit
0.4
V
2.7
DVDD + 0.5
V
SD Input
Low Voltage
GND-0.5
1.4
V
VDATAIH
D[0-11] Input
High Voltage
Vref-0.25
DVDD+0.5
V
VDATAIL
D[0-11] Input
Low Voltage
GND-0.5
Vref+0.25
V
VP-OUTOH
P-OUT Output
High Voltage
IOL = - 400 µA
VP-OUTOL
P-OUT Output
Low Voltage
IOL = 3.2 mA
VSDOL
SD Output
Low Voltage
VIICIH
SD Input
High Voltage
VIICIL
Test Condition
Min
Typ
IOL = 2.0 mA
DVDDV-0.2
V
0.2
V
Note:
VIIC -refers to I2C pins SD and SC.
VDATA - refers to all digital pixel and clock inputs.
VSD - refers to I2C pin SD as an output.
VP-OUT - refers to pixel data output Time - Graphics.
44
201-0000-035 Rev 1.1, 5/8/2000
CHRONTEL
CH7009A
Mechanical Package Information
201-0000-035 Rev 1.1, 5/8/2000
45
CHRONTEL
CH7009A
ORDERING INFORMATION
Part number
CH7009A-T
Package type
Number of pins
Voltage supply
LQFP
64
3.3V
Chrontel
2210 O’Toole Avenue
San Jose, CA 95131-1326
Tel: (408) 383-9328
Fax: (408) 383-9338
www.chrontel.com
E-mail: sales@chrontel.com
1998 Chrontel, Inc. All Rights Reserved.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE
SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably
expect to result in personal injury or death. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not
responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no
liability for errors contained in this document. Printed in the U.S.A.
201-0000-035 Rev 1.1, 5/8/2000
46