INTEGRAL IN74HC125A

TECHNICAL DATA
IN74HC125A
Quad 3-State Noninverting Buffers
High-Performance Silicon-Gate CMOS
The IN74HC125A is identical in pinout to the LS/ALS125. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LS/ALSTTL outputs.
The IN74HC125A noninverting buffers are designed to be used with 3state memory address drivers, clock drivers, and other bus-oriented
systems. The devices have four separate output enables that are active-low.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC125AN Plastic
IN74HC125AD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
PIN 14 =VCC
PIN 7 = GND
Output
A
OE
Y
H
L
H
L
L
L
X
H
Z
X = don’t care
Z = high impedance
118
IN74HC125A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
IOUT
DC Output Current, per Pin
±35
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
Min
Max
Unit
2.0
6.0
V
0
VCC
V
-55
+125
°C
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
119
IN74HC125A
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC
V
25 °C
to
-55°C
≤85
°C
≤125
°C
Unit
VOUT= VCC-0.1 V
IOUT≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
Maximum Low Level Input Voltage
VOUT=0.1 V
IOUT ≤ 20 µA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
Minimum High-Level
Output Voltage
VIN=VIH
IOUT ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VIN=VIL
IOUT ≤ 6.0 mA
IOUT ≤ 7.8 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
Symbol
Parameter
VIH
Minimum High-Level
Input Voltage
VIL
VOH
Test Conditions
VIN=VIH
IOUT ≤ 6.0 mA
IOUT ≤ 7.8 mA
VOL
120
Guaranteed Limit
Maximum Low-Level
Output Voltage
VIN=VIL
IOUT ≤ 20 µA
V
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0
±1.0
µA
IOZ
Maximum ThreeState Leakage
Current
Output in High-Impedance
State
VIN=VIL or VIH
VIN=VCC or GND
6.0
±0.5
±5.0
±10
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA
6.0
4.0
40
160
µA
IN74HC125A
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
VCC
Symbol
Parameter
V
25 °C
to
-55°C
≤85°C
≤125°C
Unit
tPLH, tPHL
Maximum Propagation Delay, Input A to
Output Y (Figures 1 and 3)
2.0
4.5
6.0
90
18
15
115
23
20
135
27
23
ns
tPLZ, tPHZ
Maximum Propagation Delay, Output Enable toY
(Figures 2 and 4)
2.0
4.5
6.0
120
24
20
150
30
26
180
36
31
ns
tPZL, tPZH
Maximum Propagation Delay, Output Enable toY
(Figures 2 and 4)
2.0
4.5
6.0
90
18
15
115
23
20
135
27
23
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
Maximum Input Capacitance
-
10
10
10
pF
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
-
15
15
15
pF
CIN
COUT
Power Dissipation Capacitance (Per Buffer)
CPD
Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
Figure 1. Switching Waveforms
Typical @25°C,VCC=5.0 V
45
pF
Figure 2. Switching Waveforms
121
IN74HC125A
Figure 3. Test Circuit
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
122