MICRON MT28S4M16LC

4 MEG x 16
SYNCFLASH MEMORY
SYNCFLASH®
MEMORY
MT28S4M16LC
1 Meg x 16 x 4 banks
FEATURES
PIN ASSIGNMENT (Top View)
• 100 MHz SDRAM-compatible read timing
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access
• Programmable burst lengths: 1, 2, 4, 8, or full page
(READ)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
– Additional VHH hardware protect mode (RP#)
• Four-bank architecture supports true concurrent
operations with zero latency:
Read from any bank while performing a
PROGRAM or ERASE operation to any other
bank
• Deep power-down mode: 300µA maximum
• Cross-compatible Flash memory command set
• Industry-standard, SDRAM-compatible pinouts
– Pins 36 and 40 are no connects for SDRAM
OPTIONS
54-Pin TSOP II
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
VCC
DQML
WE#
CAS#
RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
VCC
MARKING
• Configuration
4 Meg x 16 (1 Meg x 16 x 4 banks)
VSS
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VCCQ
DQ8
VSS
RP#
DQMH
CLK
CKE
VCCP
A11
A9
A8
A7
A6
A5
A4
VSS
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
4M16
NOTE: The # symbol indicates signal is active LOW.
• Read Timing (Cycle Time)
10ns (100 MHz)
12ns (83 MHz)
• Package
54-pin OCPL1 TSOP II (400 mil)
-10
-12
KEY TIMING PARAMETERS
TG
SPEED
GRADE
• Operating Temperature Range
Commercial Temperature (0ºC to +70ºC) None
-10
-10
-12
-12
NOTE: 1. Off-center parting line
Part Number Example:
MT28S4M16LCTG-10
CLOCK
ACCESS TIME
FREQUENCY CL = 2* CL = 3*
100 MHz
66 MHz
83 MHz
66 MHz
–
9ns
–
10ns
SETUP
TIME
HOLD
TIME
3ns
3ns
3ns
3ns
2ns
2ns
2ns
2ns
7ns
–
9ns
–
*CL = CAS (READ) latency
GENERAL DESCRIPTION
This SyncFlash® data sheet is divided into two major sections. The SDRAM Interface Functional
Description details compatibility with the SDRAM
memory, and the Flash Memory Functional Description specifies the symmetrical-sectored flash architecture functional commands.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
The MT28S4M16LC is a nonvolatile, electrically sector-erasable (Flash), programmable memory containing 67,108,864 bits organized as 4,194,304 words (16
bits). SyncFlash memory is ideal for 3.3V-only platforms that require both hardware and software protection modes. Additional hardware protection modes are
1
©2001, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
4 MEG x 16
SYNCFLASH MEMORY
GENERAL DESCRIPTION (continued)
also available when VHH is applied to the RP# pin. Programming or erasing the device is done with a 3.3V
VCCP voltage, while all other operations are performed
with a 3.3V VCC. The device is fabricated with Micron’s
advanced CMOS floating-gate process.
The MT28S4M16LC is organized into 16 independently erasable blocks. To ensure that critical firmware
is protected from accidental erasure or overwrite, the
MT28S4M16LC features sixteen 256K-word hardwareand software-lockable blocks.
The MT28S4M16LC four-bank architecture supports
true concurrent operations. A read access to any bank
can occur simultaneously with a background PROGRAM or ERASE operation to any other bank.
The SyncFlash memory has a synchronous interface (all signals are registered on the positive edge of
the clock signal, CLK). Read accesses to the memory are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ
command. The address bits registered coincident with
the ACTIVE command are used to select the bank and
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
row to be accessed. The address bits registered coincident with the READ command are used to select the
starting column location for the burst access.
The SyncFlash memory provides for programmable
read burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option.
The 4 Meg x 16 SyncFlash memory uses an internal
pipelined architecture to achieve high-speed
operation.
The 4 Meg x 16 SyncFlash memory is designed to
operate in 3.3V, low-power memory systems. A deep
power-down mode is provided, along with a powersaving standby mode. All inputs and outputs are
LVTTL-compatible.
SyncFlash memory offers substantial advances in
Flash operating performance, including the ability to
synchronously burst data at a high data rate with automatic column-address generation and the capability
to randomly change column addresses on each clock
cycle during a burst access.
Please refer to Micron’s Web site (www.micron.com/
flash) for the latest data sheet.
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
4 MEG x 16
SYNCFLASH MEMORY
TABLE OF CONTENTS
Functional Block Diagram – 4 Meg x 16 ...............
Pin Descriptions ......................................................
Output (READ) Operations ..............................
Memory Array .............................................
Status Register ..............................................
Device Configuration Registers ...................
Input Operations ..............................................
Memory Array .............................................
Command Execution ........................................
Status Register ..............................................
Device Configuration ..................................
Program Sequence .......................................
Erase Sequence .............................................
Program and Erase NVMode Register .........
Block Protect/Unprotect Sequence ..............
Device Protect Sequence ..............................
Reset/Deep Power-Down Mode .......................
Error Handling ..................................................
PROGRAM/ERASE Cycle Endurance ................
Absolute Maximum Ratings ..................................
DC Electrical Characteristics
and Operating Conditions ...................................
ICC Specifications and Conditions ..........................
Capacitance ............................................................
4
5
SDRAM Interface Functional Description ..........
7
Initialization ......................................................
7
Register Definition ............................................
7
Mode Register ...............................................
7
Burst Length ............................................
7
Burst Type ...............................................
7
CAS Latency ............................................
9
Operating Mode ......................................
9
Write Burst Mode ....................................
9
Commands ........................................................ 10
Truth Table 1 (Commands and DQM Operation) ....... 10
Truth Table 2 (Commands Sequences) ....................... 11
Command Inhibit ........................................ 13
No Operation (NOP) .................................... 13
Load Mode Register ...................................... 13
Active ............................................................ 13
Read .............................................................. 13
Write ............................................................. 13
Active Terminate .......................................... 13
Burst Terminate ............................................ 13
Load Command Register ............................. 13
Operation .......................................................... 14
Bank/Row Activation .................................. 14
Reads ............................................................ 15
Writes ........................................................... 20
Active Terminate .......................................... 20
Power-Down ................................................ 20
Clock Suspend ............................................. 20
Burst Read/Single Write ............................... 21
Truth Table 3 (CKE) .................................................. 21
Truth Table 4 (Current State, Same Bank) .................. 22
Truth Table 5 (Current State, Different Bank) ............. 23
Flash Memory Functional Description ...............
Command Interface ....................................
Memory Architecture ...................................
Protected Blocks ...........................................
Command Execution Logic (CEL) ...............
Internal State Machine (ISM) ......................
ISM Status Register ......................................
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
25
25
25
25
26
26
26
27
27
27
27
27
27
28
28
28
28
35
35
36
36
Electrical Characteristics and Recommended
Operating Conditions (Timing Table) ............. 37
AC Functional Characteristics ............................. 38
Notes ...................................................................... 39
Timing Waveforms
Initialize and Load Mode Register .....................
Clock Suspend Mode .........................................
Reads
Read ..............................................................
Alternating Bank Read Accesses ...................
Read – Full-Page Burst .................................
Read – DQM Operation ..............................
Program
Program/Erase
(Bank a followed by READ to bank b) ..
Program/Erase
(Bank a followed by READ to bank a) ..
24
24
24
24
25
25
25
3
40
41
42
43
44
45
46
47
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
FUNCTIONAL BLOCK DIAGRAM
4 Meg x 16
VCCP
RP#
CKE
STATE MACHINE
CLK
WE#
CAS#
RAS#
STATUS REG.
COMMAND
EXECUTION
LOGIC
COMMAND
DECODE
CS#
16
High Voltage
Switch/Pump
BANK 3
BANK 2
BANK 1
ID REG.
NVMODE
REGISTER
MODE REGISTER
ROWADDRESS
MUX
12
12
12
BANK 0
ROWADDRESS
4,096
LATCH
&
DECODER
BANK 0
MEMORY
ARRAY
(4,096 x 256 x 16)
2
DQML,
DQMH
SENSE AMPLIFIERS
4
16
4,096
14
ADDRESS
REGISTER
2
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
BANK
CONTROL
LOGIC
16
16
256
(x16)
COLUMN
DECODER
8
COLUMNADDRESS
COUNTER/
LATCH
DATA
OUTPUT
REGISTER
8
DQ0–DQ15
DATA
INPUT
REGISTER
4 MEG x 16
SYNCFLASH MEMORY
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
A0–A11,
BA0, BA1
2
4 MEG x 16
SYNCFLASH MEMORY
PIN DESCRIPTIONS
54-PIN TSOP
NUMBERS
SYMBOL
TYPE
38
CLK
Input
Clock: CLK is driven by the system clock. All SyncFlash memory input
signals are sampled on the positive edge of CLK. CLK also increments
the internal burst counter and controls the output registers.
37
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK
signal. Deactivating the clock provides STANDBY operation or CLOCK
SUSPEND operation (burst/access in progress). CKE is synchronous
except after the device enters power-down modes, where CKE
becomes asynchronous until after exiting the same mode. The input
buffers, including CLK, are disabled during power-down modes,
providing low standby power. CKE may be tied HIGH in systems where
power-down modes (other than RP# deep power-down) are not
required.
19
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external bank selection on systems
with multiple banks. CS# is considered part of the command code.
18, 17, 16
RAS#,
CAS#,
WE#
Input
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
15, 39
DQML,
DQMH
Input
Input/Output Mask: DQM is an input mask signal for write accesses
and an output enable signal for read accesses. Input data is masked
when DQM is sampled HIGH during a WRITE cycle. The output buffers
are placed in a High-Z state (after a two-clock latency) when DQM is
sampled HIGH during a READ cycle. DQML corresponds to DQ0–DQ7
and DQMH corresponds to DQ8–DQ15. DQML and DQMH are
considered same state when referenced as DQM.
23-26, 29-34,
22, 35
A0–A11
Input
40
RP#
Input
Address Inputs: A0–A11 are sampled during the ACTIVE command
(row-address A0–A11) and READ/WRITE command (column-address
A0–A7) to select one location in the respective bank. The address
inputs provide the Op-Code during LOAD MODE REGISTER command
and the operation code during a LOAD COMMAND REGISTER
command.
Initialize/Power-Down: Upon initial device power-up, a 100µs delay
after RP# has transitioned from LOW to HIGH is required for internal
device initialization, prior to issuing an executable command. RP#
clears the status register, sets the internal state machine (ISM) to the
array read mode, and places the device in the deep power-down
mode when LOW. All inputs, including CS#, are “Don’t Care” and all
outputs are High-Z. When RP# = VHH, all protection modes are ignored
during PROGRAM and ERASE. Also allows the device protect bit to be
set to “1” (protected) and allows the block protect bits at locations 0
and 15 to be set to “0” (unprotected) when brought to VHH. RP# must
be held HIGH during all other modes of operation.
DESCRIPTION
(continued on next page)
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
4 MEG x 16
SYNCFLASH MEMORY
PIN DESCRIPTIONS (continued)
54-PIN TSOP
NUMBERS
SYMBOL
TYPE
DESCRIPTION
20, 21
BA0,
BA1
Input
Bank Address Input(s): BA0, BA1 define to which bank the command
is being applied. See Truth Tables 1 and 2.
2, 4, 5, 7, 8, 10,
11,13, 42, 44, 45,
47, 48, 50, 51, 53
DQ0DQ15
I/O
3, 9, 43, 49
VCCQ
Supply
DQ Power: Provide isolated power to DQs for improved noise
immunity.
6, 12, 46, 52
VSS Q
Supply
DQ Ground: Provide isolated ground to DQs for improved noise
immunity.
1, 14, 27
VCC
Supply
Power Supply: 3.3V ±0.3V.
28, 41, 54
VSS
Supply
Ground.
36
VCCP
Supply
Program/Erase Supply Voltage: VCCP must be tied externally to VCC. The
VCCP pin sources current during device initialization, PROGRAM and
ERASE operations.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
Data I/O: Data bus.
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
4 MEG x 16
SYNCFLASH MEMORY
SDRAM INTERFACE
FUNCTIONAL DESCRIPTION
ister; the mode register settings automatically load the
mode register during initialization. Details on erase
nvmode register and program nvmode register command sequences are found in the Command Execution section of the Flash Memory Functional Description.
Mode register bits M0–M2 specify the burst length,
M3 specifies the burst type (sequential or interleaved),
M4–M6 specify the CAS latency, M7 and M8 specify the
operating mode, M9 specifies the write burst mode in
an SDRAM (M9 = 1 by default), and M10 and M11 are
reserved for future use.
The mode register must be loaded when all banks
are idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating
either of these requirements will result in unspecified
operation.
BURST LENGTH
Read accesses to the SyncFlash memory are burst
oriented, with the burst length being programmable,
as shown in Figure 1. The burst length determines the
maximum number of column locations that can be accessed for a given READ command. Burst lengths of 1,
2, 4, or 8 locations are available for both sequential and
interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ command is issued, a block of columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1–A7 when the burst length is set to two, by A2–A7
when the burst length is set to four, and by A3–A7 when
the burst length is set to eight. The remaining (least
significant) address bit(s) are used to select the starting location within the block. Full-page bursts wrap
within the page if the boundary is reached.
Initialization
SyncFlash memory must be powered up and initialized in a predefined manner. Operational procedures
other than those specified may result in undefined
operation. After power is applied to VCC, VCCQ, and VCCP
(simultaneously), and the clock is stable, RP# must be
brought from LOW to HIGH. A 100µs delay is required
after RP# transitions HIGH in order to complete internal device initialization.
The SyncFlash memory is now in the array read mode
and ready for mode register programming or an executable command. After initial programming of the
nvmode register, the contents are automatically loaded
into the mode register during initialization and the
device will power up in the programmed state.
Register Definition
MODE REGISTER
The mode register is used to define the specific mode
of operation of the SyncFlash memory. This definition
includes the selection of a burst length, a burst type, a
CAS latency, and an operating mode, as shown in Figure 1. The mode register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is reprogrammed. The contents of
the mode register may be copied into the nvmode reg-
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
BURST TYPE
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type, and the
starting column address, as shown in Table 1.
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
SDRAM
In general, the 64Mb SyncFlash memory (1 Meg x 16
x 4 banks) is configured as a quad-bank, nonvolatile
SDRAM that operates at 3.3V and includes a synchronous interface (all signals are registered on the positive
edge of the clock signal, CLK). Each of the x16’s
16,777,216-bit banks is organized as 4,096 rows by 256
columns by 16 bits.
Read accesses to the SyncFlash memory are burst
oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row
to be accessed (BA0 and BA1 select the bank, A0–A11
select the row). The address bits registered coincident
with the READ command are used to select the starting
column location for the burst access (BA0 and BA1 select the bank, A0–A7 select the column).
Prior to normal operation, the SyncFlash memory
must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation.
4 MEG x 16
SYNCFLASH MEMORY
A11 A10
11
A9
9
10
Reserved* WB
A8
8
A6
A7
6
7
A5
5
A3
A4
4
Op Mode CAS Latency
3
1
2
BT
A1
A2
A0
0
Table 1
Burst Definition
Address Bus
Burst
Length
Mode Register (Mx)
Burst Length
2
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
M3
Burst Type
0
Sequential
1
Interleaved
M6 M5 M4
M9
4
8
CAS Latency
0
0
0
Reserved
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined
Standard Operation
-
-
-
Full
Page
256
Reserved
1
Single Location Access
All other states reserved
Figure 1
Mode Register Definition
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
n = A0–A7
Cn, Cn+1, Cn+2
Cn+3, Cn+4...
(location 0-255)
…Cn-1,
Cn...
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
NOTE: 1. For a burst length of two, A1–A7 select the blockof-two burst; A0 selects the starting column
within the block.
2. For a burst length of four, A2–A7 select the blockof-four burst; A0–A1 select the starting column
within the block.
3. For a burst length of eight, A3–A7 select the
block-of-eight burst; A0–A2 select the starting
column within the block.
4. For a full-page burst, the full row is selected and
A0–A7 select the starting column.
5. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
6. For a burst length of one, A0–A7 select the unique
column to be accessed, and mode register bit M3
is ignored.
Write Burst Mode
0
A0
0
1
A1 A0
0
0
0
1
1
0
1
1
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
SDRAM
*Program
M11, M10 = 0, 0
to ensure compatibility
with future devices.
StartingColumn
Order of Accesses Within a Burst
Address
Type=Sequential
Type=Interleaved
4 MEG x 16
SYNCFLASH MEMORY
CAS LATENCY
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency can be set to one, two, or three clocks.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available by
T1
T2
READ
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
OPERATING MODE
The normal operating mode is selected by setting
M7 and M8 to zero; the other combinations of values for
M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to READ
bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
CAS Latency = 1
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
WRITE BURST MODE
WRITE bursts are not supported with the
MT28S4M16LC. By default, M9 is set to “1” and write
accesses are single-location (nonburst) accesses.
CAS Latency = 2
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
COMMAND
tLZ
Table 2
CAS Latency
tOH
DOUT
DQ
ALLOWABLE OPERATING
FREQUENCY (MHz)
tAC
CAS Latency = 3
SPEED
UNDEFINED
-10
≤33
≤66
≤100
-12
≤33
≤66
≤83
Figure 2
CAS Latency
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
CAS
CAS
CAS
LATENCY = 1 LATENCY = 2 LATENCY = 3
DON’T CARE
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
SDRAM
T0
clock edge n + m. The DQs will start driving as a result of
the clock edge one cycle earlier (n + m - 1) and, provided
that the relevant access times are met, the data will be
valid by clock edge n + m. For example, assuming that
the clock cycle time is such that all relevant access times
are met, if a READ command is registered at T0, and the
latency is programmed to two clocks, the DQs will start
driving after T1 and the data will be valid by T2, as
shown in Figure 2. Table 2 below indicates the operating frequencies at which each CAS latency setting can
be used.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
4 MEG x 16
SYNCFLASH MEMORY
COMMANDS
Truth Table 1 provides a quick reference of available commands for SDRAM-compatible operation. This
is followed by a written description of each command.
Additional truth tables appear later.
SDRAM
TRUTH TABLE 1
SDRAM-COMPATIBLE INTERFACE COMMANDS AND DQM OPERATION
(Notes: 1)
NAME (FUNCTION)
CS# RAS# CAS# WE# DQM
ADDR
DQs NOTES
COMMAND INHIBIT (NOP)
H
X
X
X
X
X
X
NO OPERATION (NOP)
L
H
H
H
X
X
X
ACTIVE (Select bank and activate row)
L
L
H
H
X
Bank/Row
X
2
READ (Select bank, column and start READ burst)
L
H
L
H
X
Bank/Col
X
3
WRITE (Select bank, column and start WRITE)
L
H
L
L
X
Bank/Col
Valid
3, 4
BURST TERMINATE
L
H
H
L
X
X
Active
ACTIVE TERMINATE
L
L
H
L
X
X
X
5
LOAD COMMAND REGISTER
L
L
L
H
X
ComCode
X
6, 7
LOAD MODE REGISTER
L
L
L
L
X
OpCode
X
8
Write Enable/Output Enable
–
–
–
–
L
–
Active
9
Write Inhibit/Output High-Z
–
–
–
–
H
–
High-Z
9
NOTE: 1.
2.
3.
4.
5.
6.
7.
8.
9.
CKE is HIGH for all commands shown.
A0–A11 provide row address, and BA0 and BA1 determine which bank is made active.
A0–A7 provide column address, and BA0 and BA1 determine which bank is being read from or written to.
A program setup command sequence (see Truth Table 2) must be completed prior to executing a WRITE.
ACTIVE TERMINATE is functionally equivalent to the SDRAM PRECHARGE command, however PRECHARGE (deactivate row
in bank or banks) is not required for SyncFlash memory. A10 LOW: BA0 and BA1 determine the bank being active
terminated. A10 HIGH: All banks active terminated and BA0 and BA1 are “Don’t Care.”
A0–A7 define the ComCode, and A8–A11 are “Don’t Care” for this operation. See Truth Table 2.
LOAD COMMAND REGISTER (LCR) replaces the SDRAM AUTO REFRESH or SELF REFRESH command, which is not required
for SyncFlash memory. LCR is the first cycle for Flash memory command sequences. See Truth Table 2.
A0–A11 define the OpCode written to the mode register. The mode register can be dynamically loaded each cycle,
provided tMRD is satisfied. The contents of the nvmode register are automatically loaded into the mode register during
device initialization.
Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
10
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©2001, Micron Technology, Inc.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
COMMANDS
Truth Table 2 provides a quick reference of available commands
for flash memory interface operation. A written description of each
command is found in the Flash Memory Functional Description section.
TRUTH TABLE 2
FLASH MEMORY COMMAND SEQUENCES
(Notes: 1, 2, 3, 4, 5; see notes on the next page.)
FIRST CYCLE
OPERATION
CMD
BANK
ADDR6 ADDR
SECOND CYCLE
DQ
RP#
CMD7
BANK
ADDR ADDR
THIRD CYCLE
DQ
RP#
CMD
BANK
ADDR ADDR
DQ8
RP#
NOTES
READ DEVICE CONFIGURATION
LCR
90h
Bank
X
H
ACTIVE
Row
Bank
X
H
READ
CA
Bank
X
H
9, 10
READ STATUS REGISTER
LCR
70h
X
X
H
ACTIVE
X
X
X
H
READ
X
X
X
H
CLEAR STATUS REGISTER
LCR
50h
X
X
H
ERASE SETUP/CONFIRM
LCR
20h
Bank
X
H
ACTIVE
Row
Bank
X
H
WRITE
X
Bank
D0h
H/VHH 11, 12, 13
PROGRAM SETUP/PROGRAM
LCR
40h
Bank
X
H
ACTIVE
Row
Bank
X
H
WRITE
Col
Bank
DIN
H/VHH 11, 12, 13
PROTECT BLOCK/CONFIRM
LCR
60h
Bank
X
H
ACTIVE
Row
Bank
X
H
WRITE
X
Bank
01h
H/VHH
11, 12,
13, 14
11
PROTECT DEVICE/CONFIRM
LCR
60h
Bank
X
H
ACTIVE
X
Bank
X
H
WRITE
X
Bank
F1h
VHH
11, 12
UNPROTECT BLOCKS/CONFIRM
LCR
60h
Bank
X
H
ACTIVE
X
Bank
X
H
WRITE
X
Bank
D0h
H/VHH
11, 12,
13, 15
ERASE NVMODE REGISTER
LCR
30h
Bank
X
H
ACTIVE
X
Bank
X
H
WRITE
X
Bank
C0h
H
11, 12
PROGRAM NVMODE REGISTER
LCR
A0h
Bank
X
H
ACTIVE
X
Bank
X
H
WRITE
X
Bank
X
H
11, 12
4 MEG x 16
SYNCFLASH MEMORY
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
SDRAM
4 MEG x 16
SYNCFLASH MEMORY
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
12
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©2001, Micron Technology, Inc.
SDRAM
NOTE: 1. CMD = Command: Decoded from CS#, RAS#, CAS#, and WE# inputs.
2. NOP/COMMAND INHIBIT commands may be issued throughout any operation command sequence.
3. After a PROGRAM or ERASE operation is registered to the ISM and prior to completion of the ISM operation, a READ to
any location in the bank under ISM control will output the contents of the row activated prior to the LCR/active/write
sequence (see Note 7).
4. In order to meet the tRCD specification, the appropriate number of NOP/COMMAND INHIBIT commands must be issued
between ACTIVE and READ/WRITE commands.
5. The ERASE, PROGRAM, PROTECT, UNPROTECT operations are self-timed. The status register may be polled to monitor
these operations.
6. A8–A11 are “Don’t Care.”
7. A row will not be opened when ACTIVE is preceded by LCR. ACTIVE is considered a NOP.
8. Data Inputs: DQ8–DQ15 are “Don’t Care.”
Data Outputs: All unused bits are driven LOW.
9. The block address is required during ACTIVE and READ cycles for the block protect bit location. The first row in a block
should be specified, acceptable values include 000h, 400h, 800h, and C00h. Bank address is “Don’t Care” for manufacturer compatibility ID, device ID, and device protect bit location.
10. CA = Configuration Address:
000h – Manufacturer compatibility ID (2Ch)
001h – Device ID (D3h)
x02h – Block protect bit, where x = 0, 4, 8, or Ch
003h – Device protect bit
11. The proper command sequence (LCR/active/write) is needed to initiate an ERASE, PROGRAM, PROTECT, UNPROTECT
operation.
12. The bank address must match for the three command cycles (LCR/ACTIVE/WRITE) to initiate an ERASE, PROGRAM,
PROTECT, UNPROTECT operation.
13. If the device protect bit is set, then an ERASE, PROGRAM, PROTECT, UNPROTECT operation can still be initiated by
bringing RP# to VHH prior to the WRITE command cycle and holding it at VHH until the operation is completed.
14. The A10, A11 row address and BA0, BA1 bank address select the block to be protected; A0–A9 are “Don’t Care.”
15. If the device protect bit is not set, RP# = VIH unprotects all sixteen 256K-word erasable blocks, except for blocks 0 and
15. When RP# = VHH, all sixteen 256K-word erasable blocks (including block 0 and 15) will be unprotected, and the
device protect bit will be ignored. If the device protect bit is set and RP# = VIH, the block protect bits cannot be
modified.
4 MEG x 16
SYNCFLASH MEMORY
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to
perform a NOP to a SyncFlash memory that is selected
(CS# is LOW). This prevents unwanted commands from
being registered during idle or wait states. Operations
already in progress are not affected.
LOAD MODE REGISTER
The mode register is loaded via inputs A0–A11 and
BA0 and BA1. See mode register heading in Register
Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a
subsequent executable command cannot be issued
until tMRD is met. The data in the nvmode register is
automatically loaded into the mode register upon
power-up initialization and is the default mode setting
unless dynamically changed with the LOAD MODE
REGISTER command.
ACTIVE TERMINATE
ACTIVE TERMINATE, which replaces the SDRAM
PRECHARGE command, is not required for SyncFlash
memory, but is functionally equivalent to the SDRAM
PRECHARGE command. ACTIVE TERMINATE can be
issued to terminate a BURST READ in progress and
may or may not be bank specific.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most
recently registered READ command prior to the BURST
TERMINATE command will be truncated as shown in
the Operation section of this data sheet. BURST TERMINATE is not bank specific.
ACTIVE
The ACTIVE command is used to open (or activate)
a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0–A11 selects the row.
This row remains active for accesses until the next ACTIVE command, power-down or RESET.
LOAD COMMAND REGISTER (LCR)
The LOAD COMMAND REGISTER (LCR) command
is used to initiate flash memory control commands to
the command execution logic (CEL). The CEL receives
and interprets commands to the device. These commands control the operation of the ISM and the read
path (i.e., memory array, ID register, or status register).
However, there are restrictions on what commands are
allowed in this condition. See the Command Execution
section of Flash Memory Functional Description for
more details.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0–A7 selects the starting column location. Read
data appears on the DQs subject to the logic level on
the DQM input two clocks earlier. If a given DQM signal
was registered HIGH, the corresponding DQs will be
High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
13
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©2001, Micron Technology, Inc.
SDRAM
WRITE
The WRITE command is used to initiate a singlelocation write access. A WRITE command must be preceded by LRC/ACTIVE. The value on the BA0, BA1 inputs selects the bank, and the address provided on
inputs A0–A7 selects the column location.
Input data appearing on the DQs is written to the
memory array, subject to the DQM input logic level
appearing coincident with the data. If a given DQM
signal is registered LOW, the corresponding data will
be written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs will be ignored,
and a WRITE will not be executed to that word/column
location. A WRITE command with DQM HIGH is considered a NOP.
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new
commands from being executed by the SyncFlash
memory, regardless of whether the CLK signal is enabled. The SyncFlash memory is effectively deselected.
Operations already in progress are not affected.
4 MEG x 16
SYNCFLASH MEMORY
Operation
CLK
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to a bank within the SyncFlash memory, a row in
that bank must be “opened.” (Note: A row will not be
activated for LCR/active/read or LCR/active write command sequences, see the Flash Memory Architecture
section for additional information). This is accomplished via the ACTIVE command, which selects both
the bank and the row to be activated.
After opening a row (issuing an ACTIVE command),
a READ or WRITE command may be issued to that row,
subject to the tRCD specification. tRCD (MIN) should
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock edge
after the ACTIVE command on which a READ or WRITE
command can be entered. For example, a tRCD specification of 30ns with a 90 MHz clock (11.11ns period)
results in 2.7 clocks rounded to 3. This is reflected in
Figure 4, which covers any case where 2 < tRCD (MIN)/
tCK ≤ 3 . (The same procedure is used to convert other
specification limits from time units to clock cycles).
A subsequent ACTIVE command to a different row
in the same bank can be issued without having to close
a previous active row, provided the minimum time interval between successive ACTIVE commands to the
same bank is defined by tRC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row access overhead. The minimum time interval between successive
ACTIVE commands to different banks is defined by
tRRD.
HIGH
CS#
SDRAM
T0
CKE
RAS#
CAS#
WE#
ROW
ADDRESS
A0–A10
BANK
ADDRESS
BA0, BA1
Figure 3
Activating a Specific Row in a
Specific Bank
T1
T2
T3
NOP
NOP
T4
CLK
COMMAND
ACTIVE
READ or WRITE
tRCD
DON’T CARE
Example: Meeting
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
tRCD
Figure 4
(MIN) When 2 < tRCD (MIN)/tCK £ 3
14
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©2001, Micron Technology, Inc.
4 MEG x 16
SYNCFLASH MEMORY
The new READ command should be issued x cycles
before the clock edge at which the last desired data
element is valid, where x equals the CAS latency minus
one. This is shown in Figure 7 for CAS latencies of one,
two, and three; data element n + 3 is either the last of a
burst of four, or the last desired of a longer burst. The
SyncFlash memory uses a pipelined architecture and
therefore does not require the 2n rule associated with a
prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed, random read accesses within a page
can be performed as shown in Figure 8, or each subsequent READ may be performed to a different bank.
Data from any READ burst may be truncated with a
T0
T1
T2
READ
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CAS Latency = 1
CLK
CKE
HIGH
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
CS#
tLZ
tOH
DOUT
DQ
tAC
RAS#
CAS Latency = 2
CAS#
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
WE#
COMMAND
tLZ
COLUMN
ADDRESS
A0–A7
tOH
DOUT
DQ
tAC
BANK
ADDRESS
BA0, BA1
CAS Latency = 3
DON’T CARE
Figure 5
READ Command
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
UNDEFINED
Figure 6
CAS Latency
15
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©2001, Micron Technology, Inc.
SDRAM
READs
READ bursts are initiated with a READ command,
as shown in Figure 5.
The starting column and bank addresses are provided with the READ command.
During READ bursts, the valid data-out element
from the starting column address will be available following the CAS latency after the READ command. Each
subsequent data-out element will be valid by the next
positive clock edge. Figure 6 shows general timing for
one, two, and three CAS latency settings.
Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A
full-page burst will continue until terminated. (At the
end of the page, it will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixedlength READ burst may be immediately followed by
data from a subsequent READ command. In either
case, a continuous flow of data can be maintained. The
first data element from the new burst follows either the
last element of a completed burst, or the last desired
data element of a longer burst that is being truncated.
4 MEG x 16
SYNCFLASH MEMORY
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
NOP
NOP
NOP
READ
NOP
X = 0 cycles
BANK,
COL n
SDRAM
ADDRESS
BANK,
COL b
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
DOUT
b
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
READ
NOP
NOP
X = 1 cycle
BANK,
COL b
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
DOUT
b
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
READ
NOP
NOP
NOP
X = 2 cycles
BANK,
COL b
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
DON’T CARE
Figure 7
Consecutive READ Bursts
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
16
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©2001, Micron Technology, Inc.
4 MEG x 16
SYNCFLASH MEMORY
T0
T1
T2
T3
T4
CLK
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
DOUT
x
DOUT
a
SDRAM
COMMAND
DOUT
m
CAS Latency = 1
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
NOP
DOUT
x
DOUT
a
DOUT
m
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
NOP
DOUT
a
DOUT
n
DQ
NOP
DOUT
x
NOP
DOUT
m
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
DON’T CARE
Figure 8
Random Read Accesses Within a Page
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
17
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©2001, Micron Technology, Inc.
4 MEG x 16
SYNCFLASH MEMORY
T0
T1
T2
T3
T4
CLK
DQM, H
COMMAND
READ
LCR
ACTIVE
ADDRESS
BANK,
COL n
40h
BANK
ROW
NOP
WRITE
BANK,
COL b
tCK
tHZ
DOUT n
DQ
DIN b
tDS
NOTE:
A CAS latency of three is used for illustration. The
READ command may be to any bank, and the WRITE
command may be to any bank. If a CAS latency of one is
used, then DQM is not required.
DON’T CARE
Figure 9
READ to WRITE
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
18
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©2001, Micron Technology, Inc.
SDRAM
High-Z) regardless of the state of the DQM signal. The
DQM signal must be de-asserted prior to the WRITE
command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 9 shows the case where the clock frequency allows
for bus contention to be avoided without adding a NOP
cycle.
A fixed-length or full-page READ burst can be truncated with ACTIVE TERMINATE (may or may not be
bank specific) or BURST TERMINATE (not bank specific). The ACTIVE TERMINATE or BURST TERMINATE
command should be issued x cycles before the clock
edge at which the last desired data element is valid,
where x equals the CAS latency minus one. This is
shown in Figure 10 for each possible CAS latency; data
element n + 3 is the last desired data element of a burst
of four or the last desired of a longer burst.
subsequent WRITE command (WRITE commands
must be preceded by LCR/ACTIVE), and data from a
fixed-length READ burst may be immediately followed
by data from a subsequent WRITE command (subject
to bus turnaround limitations). The WRITE may be
initiated on the clock edge immediately following the
last (or last desired) data element from the READ burst,
provided that I/O contention can be avoided. In a given
system design, there may be the possibility that the
device driving the input data would go Low-Z before
the SyncFlash memory DQs go High-Z. In this case, at
least a single-cycle delay should occur between the last
read data and the WRITE command.
The DQM input is used to avoid I/O contention as
shown in Figure 9. The DQM signal must be asserted
(HIGH) at least two clocks prior to the WRITE command
(DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain
4 MEG x 16
SYNCFLASH MEMORY
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
X = 0 cycles
SDRAM
ADDRESS
BANK,
COL n
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
DOUT
n+3
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
X = 1 cycle
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
DOUT
n+3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
NOP
X = 2 cycles
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
CAS Latency = 3
NOTE: DQM is LOW.
DON’T CARE
Figure 10
Terminating a READ Burst
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
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©2001, Micron Technology, Inc.
4 MEG x 16
SYNCFLASH MEMORY
WRITEs
A single-location WRITE is initiated with a WRITE
command (preceded by LCR/ACTIVE, see Truth Table
2), as shown in Figure 11. The starting column and
bank addresses are provided with the WRITE command. Once a WRITE command is registered, a READ
command can be executed as defined by Truth Tables
4 and 5. An example is shown in Figure 12.
During a WRITE, the valid data-in element will be
registered coincident with the WRITE command. Additional details on write sequence operations are found
in the Command Execution section.
COMMAND
WRITE
READ
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL b
DbOUT
A CAS latency of two is used for illustration.
The WRITE command may be to any bank and the
READ command may be to any bank. DQM is
LOW. For more details, refer to Truth Tables 4
and 5.
Figure 12
WRITE to READ
BURST READ/SINGLE WRITE
The burst read/single write mode is the default
mode for the MT28S4M16LC; the write burst mode bit
(M9) in the mode register is set to a logic 1. All WRITE
commands result in the access of a single column location (burst of one). READ commands access columns
according to the programmed burst length and sequence.
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT, when no
accesses are in progress. Entering power-down deactivates the input and output buffers (excluding CKE)
after ISM operations (including WRITE operations) are
completed, for power savings while in standby.
The power-down state is exited by registering a NOP
or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting tCKS).
See the Reset/Deep Power-Down description in the
Flash Memory Functional Description for maximum
power savings mode.
RAS#
CAS#
WE#
COLUMN
ADDRESS
CLOCK SUSPEND
The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic.
BANK
ADDRESS
Figure 11
WRITE Command
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SDRAM
DIN
n
DON’T CARE
CS#
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
T3
NOTE:
HIGH
BA0, BA1
T2
DQ
CLK
A0–A7
T1
CLK
ACTIVE TERMINATE
The ACTIVE TERMINATE command is functionally
equivalent to the SDRAM PRECHARGE command. Unlike SDRAM, SyncFlash does not require a PRECHARGE
command to deactivate the open row in a particular
bank or the open rows in all banks. Asserting input A10
HIGH during an ACTIVE TERMINATE command will
terminate a BURST READ in any bank. When A10 is
LOW during an ACTIVE TERMINATE command, BA0
and BA1 will determine which bank will undergo a terminate operation. ACTIVE TERMINATE is considered
a NOP for banks not addresssed by A10, BA0, BA1.
CKE
T0
4 MEG x 16
SYNCFLASH MEMORY
For each positive clock edge on which CKE is
sampled LOW, the next internal positive clock edge is
suspended. Any command or data present on the input pins at the time of a suspended internal clock edge
is ignored, any data present on the DQ pins remains
driven, and burst counters are not incremented, as
long as the clock is suspended (see example in Figure
14).
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will resume on the subsequent positive clock edge.
T0
T4
T5
T6
INTERNAL
CLOCK
COMMAND
READ
ADDRESS
BANK,
COL n
DQ
NOP
NOP
DOUT
n
NOP
NOP
DOUT
n+1
DOUT
n+2
NOP
DOUT
n+3
t CKS
DON’T CARE
((
))
COMMAND
((
))
((
))
NOP
NOP
tRCD
tRAS
All banks idle
Input buffers gated off
Enter power-down mode.
Figure 14
Clock Suspend During READ Burst
ACTIVE
Exit power-down mode.
tRC
Figure 13
Power-Down
TRUTH TABLE 3 – CKE
(Notes: 1-4)
CKEn-1 CKEn
L
L
L
H
H
L
H
H
CURRENT STATE
COMMAND n
ACTION n
NOTES
Clock Standby
X
Maintain Clock Standby
Clock Suspend
X
Maintain Clock Suspend
Clock Standby
COMMAND INHIBIT or NOP
Exit Clock Standby
5
Clock Suspend
X
Exit Clock Suspend
6
No Burst in Progress
COMMAND INHIBIT or NOP
Clock Standby
VALID
Clock Suspend
Reading
See Truth Table 4
NOTE: 1.
2.
3.
4.
5.
“CKEn” is the logic state of CKE at clock edge n; “CKEn-1” was the state of CKE at the previous clock edge.
“Current State” is the state of the SyncFlash memory immediately prior to clock edge n.
“Commandn” is the command registered at clock edge n and “Actionn” is a result of Commandn.
All states and sequences not shown are illegal or reserved.
Exiting POWER-DOWN at clock edge n will put the device in the idle state in time for clock edge n + 1 (provided that
tCKS is met).
6. After exiting CLOCK SUSPEND at clock edge n, the device will resume operation and recognize the next command at
clock edge n + 1.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
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©2001, Micron Technology, Inc.
SDRAM
CKE
T3
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
DM is LOW.
((
))
((
))
tCKS
T2
CKE
Coming out of a power-down sequence (active),
tCKS (CKE setup time) must be greater than or equal to 3ns.
CLK
T1
CLK
4 MEG x 16
SYNCFLASH MEMORY
TRUTH TABLE 4 – CURRENT STATE BANK n; COMMAND TO BANK n
(Notes: 1-6)
CURRENT STATE CS# RAS# CAS# WE#
Any
Row Active
Read
Write
NOTES
X
X
X
COMMAND INHIBIT (NOP/continue previous operation)
L
H
H
H
NO OPERATION (NOP/continue previous operation)
L
L
H
H
ACTIVE (Select and activate row)
L
L
L
H
LOAD COMMAND REGISTER
L
L
L
L
LOAD MODE REGISTER
7
L
L
H
L
ACTIVE TERMINATE
8
L
H
L
H
READ (Select column and start READ burst)
L
H
L
L
WRITE (Select column and start WRITE)
L
L
H
L
ACTIVE TERMINATE
L
L
L
H
LOAD COMMAND REGISTER
L
H
L
H
READ (Select column and start new READ burst)
L
L
H
L
ACTIVE TERMINATE
8
L
H
H
L
BURST TERMINATE
9
L
L
L
H
LOAD COMMAND REGISTER
L
H
L
H
READ (Select column and start new READ burst)
L
L
L
H
LOAD COMMAND REGISTER
8
10
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 3).
2. This table is bank specific, except where noted; i.e., the current state is for a specific bank and the commands shown
are those allowed to be issued to that bank, when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank is not in read or write mode.
Row Active: A row in the bank has been activated and tRCD has been met. No data bursts/accesses and no
register accesses are in progress.
Read: A READ burst has been initiated and has not yet terminated or been terminated.
Write: A WRITE operation has been initiated to the SyncFlash ISM and has not yet completed.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP
commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states.
Allowable commands to the other bank are determined by its current state and Truth Table 4, and according to Truth
Table 5.
Active Terminate: Starts with registration of an ACTIVE TERMINATE command and ends on the next clock cycle. The
bank will then be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the
bank will be in the row active state.
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must
be applied on each positive clock edge during these states.
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD
has been met. Once tMRD is met, the SyncFlash memory will be in the all banks idle state.
Initialize Mode: Starts with RP# transitioning from LOW to HIGH and ends after 100µs delay.
6. All states and sequences not shown are illegal or reserved.
7. Not bank specific; requires that all banks are idle.
8. May or may not be bank specific.
9. Not bank specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.
10. A READ operation to the bank under ISM control will output the contents of the row activated prior to the LCR/active/
write sequence (see Truth Table 2).
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
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©2001, Micron Technology, Inc.
SDRAM
Idle
COMMAND/ACTION
H
4 MEG x 16
SYNCFLASH MEMORY
TRUTH TABLE 5 – CURRENT STATE BANK n; COMMAND TO BANK m
(Notes: 1-6)
CURRENT STATE CS# RAS# CAS# WE#
Any
NOTES
X
X
X
COMMAND INHIBIT (NOP/continue previous operation)
L
H
H
H
NO OPERATION (NOP/continue previous operation)
X
X
X
X
Any Command Otherwise Allowed to Bank m
L
L
H
H
ACTIVE (Select and activate row)
Row Activating,
L
H
L
H
READ (Select column and start READ burst)
Active, or
L
H
L
L
WRITE (Select column and start WRITE)
Active
L
L
H
L
ACTIVE TERMINATE
Terminate
L
L
L
H
LOAD COMMAND REGISTER
L
L
H
H
ACTIVE (Select and activate row)
L
H
L
H
READ (Select column and start new READ burst)
L
L
H
L
ACTIVE TERMINATE
L
L
L
H
LOAD COMMAND REGISTER
L
L
H
H
ACTIVE (Select and activate row)
L
H
L
H
READ (Select column and start READ burst)
L
L
H
L
ACTIVE TERMINATE
L
H
H
L
BURST TERMINATE
L
L
L
H
LOAD COMMAND REGISTER
Read
Write
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 3).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the
commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given
command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank is not in initialize, read, write mode.
Row Active: A row in the bank has been activated and tRCD has been met. No data bursts/accesses and no
register accesses are in progress.
Read: A READ burst has been initiated and has not yet terminated or been terminated.
Write: A WRITE operation has been initiated to the SyncFlash ISM and has not yet completed.
4. LOAD MODE REGISTER command may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
6. All states and sequences not shown are illegal or reserved.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
SDRAM
Idle
COMMAND/ACTION
H
4 MEG x 16
SYNCFLASH MEMORY
FLASH MEMORY
FUNCTIONAL DESCRIPTION
•
•
•
•
•
•
•
•
Command Interface
Memory Architecture
Output (READ) Operations
Input Operations
Command Execution
RESET/Power-Down Mode
Error Handling
PROGRAM/ERASE Cycle Endurance
COMMAND INTERFACE
All Flash operations are executed with LCR (LOAD
COMMAND REGISTER), LCR/ACTIVE/READ, or LCR/
ACTIVE/WRITE commands and command sequences
as defined in Truth Tables 1 and 2. See the SDRAM
Interface Functional Description for information on
reading the memory array.
Address pins A0–A7 are used to input 8-bit commands during the LCR command cycle. This command
will identify which flash operation is initiated.
Certain LCR/active/write command sequences require an 8-bit confirmation code on the WRITE cycle.
The confirmation code is input on DQ0–DQ7.
All input commands are latched on the positive clock
edge.
PROTECTED BLOCKS
The 64Mb SyncFlash memory is organized into 16
erasable memory blocks. Each block may be software
protected by issuing the appropriate LCR/active/write
sequence for a BLOCK PROTECT operation.
The blocks at locations 0 and 15 have additional
protection to prevent inadvertent PROGRAM or ERASE
operations in 3.3V-only platforms. Once a PROTECT
BLOCK operation has been executed to these blocks,
an UNPROTECT ALL BLOCKS operation will unlock all
blocks except the blocks at locations 0 and 15 unless
RP# = VHH. This provides additional security for critical
code during in-system firmware updates should an
unintentional power disruption or system reset occur.
MEMORY ARCHITECTURE
The 64Mb SyncFlash is a four-bank architecture with
four erasable “blocks” per bank. By erasing blocks
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
24
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©2001, Micron Technology, Inc.
FLASH
rather than the entire array, the total device endurance is enhanced, as is system flexibility. Only the
ERASE and BLOCK PROTECT functions are block oriented. The four banks have simultaneous read-whilewrite functionality. An ISM PROGRAM or ERASE operation to any bank can occur simultaneously with a READ
to any other bank.
The SyncFlash memory has a single background
operation ISM to control power-up initialization,
ERASE, PROGRAM, and PROTECT operations. ISM
operations are initiated with an LCR/ACTIVE/WRITE
command sequence. Only one ISM operation can occur
at any time; however, certain other commands, including READ operations, can be performed while an ISM
operation is taking place. A new LCR/active/write command sequence will not be permitted until the current
ISM operation is complete. An operational command
controlled by the ISM is defined as either a bank-level
operation or a device-level operation.
PROGRAM and ERASE are bank-level ISM operations. After an ISM bank-level operation has been initiated, a READ may be issued to any bank; however, a
READ to the bank under ISM control will output the
contents of the row activated prior to the LCR/active/
write command sequence.
ERASE NVMODE REGISTER, PROGRAM NVMODE
REGISTER, BLOCK PROTECT, DEVICE PROTECT, and
UNPROTECT ALL BLOCKS are device-level ISM operations. Once an ISM device-level operation has been
initiated, a READ to any bank will output the contents
of the array.
A read status register command sequence may be
issued to determine completion of the ISM operation.
When SR7 = 1, the ISM operation is complete and a new
ISM operation may be initiated.
The SyncFlash memory incorporates a number of
features that make it ideally suited for code storage
and execute-in-place applications on an SDRAM bus.
The memory array is segmented into individual erase
blocks. Each block may be erased without affecting
data stored in other blocks. These memory blocks are
read, programmed, and erased by issuing commands
to the command execution logic (CEL). The CEL controls the operation of the internal state machine (ISM),
which completely controls all ERASE NVMODE REGISTER, PROGRAM NVMODE REGISTER, PROGRAM,
BLOCK ERASE, BLOCK PROTECT, DEVICE PROTECT,
UNPROTECT ALL BLOCKS, and VERIFY operations.
The ISM protects each memory location from
overerasure and optimizes each memory location for
maximum data retention. In addition, the ISM greatly
simplifies the control necessary for programming the
device in-system or in an external programmer.
The Flash Memory Functional Description provides
detailed information on the operation of the SyncFlash
memory and is organized into these sections:
4 MEG x 16
SYNCFLASH MEMORY
COMMAND EXECUTION LOGIC (CEL)
SyncFlash operations are executed by issuing the
appropriate commands to the CEL. The CEL receives
and interprets commands to the device. These commands control the operation of the ISM and the read
path (i.e., memory array, device configuration, or status register). Commands may be issued to the CEL
while the ISM is active. However, there are restrictions
on what commands are allowed in this condition. See
the Command Execution section for more details.
A second level of block protection is possible
by completing a hardware DEVICE PROTECT operation. DEVICE PROTECT prevents block protect bit
modification.
The protection status of any block may be checked
by reading the protect bits with a read device configuration command sequence.
ADDRESS RANGE
n
lu
m
FFF
C00
BFF
800
7FF
400
3FF
000
FFF
C00
BFF
800
7FF
400
3FF
000
FFF
C00
BFF
800
7FF
400
3FF
000
FFF
C00
BFF
800
7FF
400
3FF
000
Co
w
Ro
Ba
nk
Bank 3
Bank 2
Bank 1
Bank 0
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
256K-Word Block
15
256K-Word Block
14
256K-Word Block
13
256K-Word Block
12
256K-Word Block
11
256K-Word Block
10
256K-Word Block
9
256K-Word Block
8
256K-Word Block
7
256K-Word Block
6
256K-Word Block
5
256K-Word Block
4
256K-Word Block
3
256K-Word Block
2
256K-Word Block
1
256K-Word Block
0
ISM STATUS REGISTER
The 16-bit ISM status register allows an external
processor to monitor the status of the ISM during device initialization, ERASE NVMODE REGISTER, PROGRAM NVMODE REGISTER, PROGRAM, ERASE,
BLOCK PROTECT, DEVICE PROTECT or UNPROTECT
ALL BLOCKS, and any related errors. ISM operations
and related errors can be monitored by reading status
register bits on DQ0–DQ8.
All of the defined bits are set by the ISM, but only
the ISM status bits (SR0, SR1, SR2, SR7) are cleared by
the ISM. The erase/unprotect block, program/protect
block, and device protection bits must be cleared by
the host system using the CLEAR STATUS REGISTER
command. This allows the user to choose when to poll
and clear the status register. For example, the host
system may perform multiple PROGRAM operations
before checking the status register instead of checking
after each individual PROGRAM.
A V CC power sequence error is cleared by reinitializing the device.
Asserting the RP# signal or powering down the device will also clear the status register.
Word-Wide (x16)
Unlock Blocks
(RP# = VHH)
Unlock Blocks
(RP# = VIH)
NOTE: See Block Lock and Unlock Flowchart Sequences for
additional information
Figure 15
Memory Address Map
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
FLASH
INTERNAL STATE MACHINE (ISM)
Power-up initialization, erase, program, and protect timings are simplified by using an ISM to control all
programming algorithms in the memory array. The ISM
ensures protection against overerasure and optimizes
programming margin to each cell.
During PROGRAM operations, the ISM automatically increments and monitors PROGRAM attempts,
verifies programming margin on each memory cell, and
updates the ISM status register. When BLOCK ERASE is
performed, the ISM automatically overwrites the entire addressed block (eliminates overerasure), increments and monitors ERASE attempts, and sets bits in
the ISM status register.
4 MEG x 16
SYNCFLASH MEMORY
OUTPUT (READ) OPERATIONS
an input operation is LCR where inputs A0–A7 determine the input command being executed to the CEL.
An input operation will not disrupt data in a previously
opened page.
The DQ pins are used either to input data to the
array or to input a command to the command execution logic (CEL) during the WRITE cycle.
More information describing how to program, erase,
protect, or unprotect the device is provided in the Command Execution section.
MEMORY ARRAY
Programming or erasing the memory array sets the
desired bits to logic 0s but cannot change a given bit to
a logic 1 from a logic 0. Setting any bit to a logic 1 requires that the entire block be erased. Programming a
protected block requires that the RP# pin be brought to
VHH. A0–A11 provide the address to be programmed,
while the data to be programmed in the array is input
on the DQ pins. The data and addresses are latched on
the rising edge of the clock. Details on how to input
data to the array is covered in the Command Execution
section.
MEMORY ARRAY
A READ command to any bank will output the contents of the memory array. While a PROGRAM or ERASE
ISM operation is in progress, a READ to any location in
the bank under ISM control will output the contents of
the row activated prior to the LCR/active/write command sequence; a READ to any other bank will output
the contents of the array. All commands and their operations are covered in the SDRAM Interface Functional
Description section.
COMMAND EXECUTION
Commands are issued to bring the device into different operational modes. Each mode has specific operations that can be performed while in that mode. All
modes require that an LCR/active/read or LCR/active/
write sequence be issued, except CLEAR STATUS REGISTER which is a single LCR command. Inputs A0–A7
during the LCR command determine the command
being executed. The following section describes the
properties of each mode, and Truth Tables 1 and 2 list
all commands and command sequences required to
perform the desired operation. Read-while-write functionality allows a background operation program or
erase to any bank while simultanously reading any
other bank.
The LCR/active/write command sequences in Truth
Table 2 must be completed on consecutive clock cycles.
However, in order to reduce bus contention issues, an
unlimited number of NOPs or COMMAND INHIBITs
can be issued throughout the LCR/active/write command sequence. For additional protection, these command sequences must have the same bank address for
the three command cycles.
If the bank address changes during the LCR/active/write command sequence or if the command sequences are not consecutive (other than NOPs and
COMMAND INHIBITs), the program and erase status
bits (SR4 and SR5) will be set and the desired operation
will be aborted.
STATUS REGISTER
Reading the status register requires an LCR/active/
read command sequence. The status register contents
are latched on the next positive clock edge subject to
CAS latencies. The burst length of the status register
data-out is defined by the mode register.
All commands and their operations are covered in
the Command Execution section.
DEVICE CONFIGURATION REGISTERS
Reading the device ID, manufacturer compatibility
ID, device protection status, and block protect status
requires the same input sequencing as when reading
the status register except that specific addresses must
be issued.
All commands and their operations are covered in
the Command Execution section.
INPUT OPERATIONS
An LCR/active/write command sequence is required to program the array, or to perform an ERASE,
PROTECT, or UNPROTECT operation. The first cycle of
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
26
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©2001, Micron Technology, Inc.
FLASH
SyncFlash memory features three different types of
READs. Depending on the mode, a READ operation
will produce data from the memory array, status register, or one of the device configuration registers.
SyncFlash memory is in the array read mode unless a
status register or device register read is initiated or in
progress.
A READ to the device configuration register or the
status register must be preceded by LCR/ACTIVE. The
burst length of data-out is defined by the mode register settings. Reading the device configuration register
or status register will not disrupt data in a previously
opened (or “activated”) page. When the burst is complete, a subsequent READ will read the array. However, several differences exist and are described in the
following section. Moving between modes to perform a
specific READ will be covered in the Command Execution section.
4 MEG x 16
SYNCFLASH MEMORY
STATUS REGISTER
Reading the status register requires an LCR/active/
read command sequence. The status register contents
are latched on the next positive clock edge subject to
CAS latencies for a burst length defined by the mode
register.
DEVICE CONFIGURATION
To read the device ID, manufacturer compatibility
ID, device protect bit, and each of the block protect
bits, the appropriate LCR/active/read command sequence for READ DEVICE CONFIGURATION must be
issued. Specific configuration addresses must be issued to read the desired information. The manufacturer compatibility ID is read at 000h; the device ID is
read at 001h. The manufacturer compatibility ID and
device ID are output on DQ0–DQ7. The device protect
bit is read at 003h; and each of the block protect bits is
read on the third address location within each block
(x02h). The device and block protect bits are output on
DQ0.
The device configuration register contents are output subject to CAS latencies for a burst length defined
by the mode register.
PROGRAM SEQUENCE
Three commands on consecutive clock edges are
required to input data to the array (NOPs and COMMAND INHIBITS are permitted between cycles). In
the first cycle, LOAD COMMAND REGISTER is issued
with PROGRAM SETUP (40h) on A0–A7, and the bank
address is issued on BA0, BA1. The next command is
ACTIVE, which identifies the row address and confirms the bank address. The third cycle is WRITE, during which the column address, the bank address, and
data are issued. The ISM status bit will be set on the
following clock edge (subject to CAS latencies).
While the ISM is programming the array, the ISM
status bit (SR7) will be at “0.” When the ISM status bit
(SR7) is set to a logic 1, programming is complete, and
the bank will be in the array read mode and ready for a
new ISM operation.
Programming hardware-protected blocks requires
that the RP# pin be set to VHH prior to the third cycle
(WRITE), and RP# must be held at VHH until the ISM
PROGRAM operation is complete. The program and
erase status bits (SR4 and SR5) will be set and the operation aborted if the LCR/active/write command sequence is not completed on consecutive cycles or the
bank address changes for any of the three cycles. After
the ISM has initiated programming, it cannot be
aborted except by a RESET or by powering down the
device. Doing either while programming the array will
corrupt the data being written.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
PROGRAM AND ERASE NVMODE REGISTER
The contents of the mode register may be copied
into the nvmode register with a PROGRAM NVMODE
REGISTER command. Prior to programming the
nvmode register, an erase nvmode register command
sequence must be completed to set all bits in the
nvmode register to logic 1. The command sequence
necessary to execute an ERASE NVMODE REGISTER
and PROGRAM NVMODE REGISTER is similar to that
of a PROGRAM. See Truth Table 2 for more information
on the LCR/ACTIVE/WRITE commands necessary to
complete ERASE NVMODE REGISTER and PROGRAM
NVMODE REGISTER.
BLOCK PROTECT/UNPROTECT SEQUENCE
Executing a block protect sequence will enable the
first level of software/hardware protection for a given
block. The command sequence necessary to execute a
BLOCK PROTECT is similar to that of a PROGRAM. To
provide added security against accidental block protection, three consecutive command cycles are required to initiate a BLOCK PROTECT. In the first cycle,
LOAD COMMAND REGISTER is issued with PROTECT
SETUP (60h) on A0–A7, and the bank address of the
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
FLASH
ERASE SEQUENCE
Executing an erase sequence will set all bits within a
block to logic 1. The command sequence necessary to
execute an ERASE is similar to that of a PROGRAM. To
provide added security against accidental block erasure, three consecutive command sequences on consecutive clock edges are required to initiate an ERASE
of a block. In the first cycle, LOAD COMMAND REGISTER is issued with ERASE SETUP (20h) on A0–A7, and
the bank address of the block to be erased is issued on
BA0, BA1. The next command is ACTIVE, where A10,
A11, BA0, and BA1 provide the address of the block to
be erased. The third cycle is WRITE, during which
ERASE CONFRIM (D0h) is issued on DQ0–DQ7 and the
bank address is reissued. The ISM status bit will be set
on the following clock edge (subject to CAS latencies).
After ERASE CONFIRM (D0h) is issued, the ISM will
start erasing the addressed block. When the ERASE
operation is complete, the bank will be in the array read
mode and ready for an executable command. Erasing
hardware-protected blocks also requires that the RP#
pin be set to VHH prior to the third cycle (WRITE), and
RP# must be held at VHH until the erase operation is
complete (SR7 = 1). If the LCR/active/write command
sequence is not completed on consecutive cycles (NOPs
and COMMAND INHIBITs are permitted between
cycles), or the bank address changes for one or more of
the command cycles, the program and erase status bits
(SR4 and SR5) will be set.
4 MEG x 16
SYNCFLASH MEMORY
block to be protected is issued on BA0, BA1. The next
command is ACTIVE, which identifies a row in the block
to be protected and confirms the bank address. The
third cycle is WRITE, during which BLOCK PROTECT
CONFIRM (01h) is issued on DQ0–DQ7, and the bank
address is reissued. The ISM status bit will be set on the
following clock edge (subject to CAS latencies) indicating the PROTECT operation is in progress.
If the LCR/ACTIVE/WRITE is not completed on consecutive cycles (NOPs and COMMAND INHIBITs are
permitted between cycles), or the bank address
changes, the write and erase status bits (SR4 and SR5)
will be set and the operation will be aborted. When the
ISM status bit (SR7) is set to a logic 1, the PROTECT
opertation is complete.
Once a block protect bit has been set to a “1” (protected), it can only be reset to a “0” if the UNPROTECT
ALL BLOCKS command is executed. The unprotect all
blocks command sequence is similar to the block protect sequence; however, in the third cycle, a WRITE is
issued with UNPROTECT ALL BLOCKS CONFIRM (D0h)
and addresses are “Don’t Care.” For additional information, refer to Truth Table 2.
The blocks at locations 0 and 15 have additional
security. Once the block protect bits at locations 0 and
15 have been set to a “1” (protected), each bit can only
be reset to a “0” if RP# is brought to VHH prior to the third
cycle (WRITE) of the UNPROTECT operation, and held
at VHH until the operation is complete (SR7 = 1).
If the device protect bit is set, RP# must be brought
to VHH prior to the third cycle and held at VHH until the
BLOCK PROTECT or UNPROTECT ALL BLOCKS operation is complete.
To check a block’s protect status, a read device configuration command sequence may be issued.
Once the device protect bit is set, it can only be reset
to a “0” by issuing a BLOCK UNPROTECT command
with RP# at VHH during the operation. With the device
protect bit set to a “1,” BLOCK PROTECT or BLOCK
UNPROTECT is prevented unless RP# is at VHH during
either operation. The device protect bit does not affect
PROGRAM or ERASE operations.
RESET/DEEP POWER-DOWN MODE
ERROR HANDLING
After the ISM status bit (SR7) has been set, the device protect (SR3), write/protect block (SR4) and erase/
unprotect (SR5) status bits may be checked. If one or a
combination of SR3, SR4, SR5 status bits has been set,
an error has occurred. SR8 is set when an inadvertent
power failure occurs during device initialization. The
device should be reinitialized to ensure proper device
operation. The ISM cannot reset SR3, SR4, SR5 or SR8.
To clear these bits, CLEAR STATUS REGISTER (50h)
must be given. Table 5 lists the combination of errors.
DEVICE PROTECT SEQUENCE
Executing a device protect sequence will set the
device protect bit to a “1” and prevent block protect bit
modification. The command sequence necessary to
execute a DEVICE PROTECT is similar to that of a PROGRAM. Three consecutive command cycles are required to initiate a DEVICE PROTECT. In the first cycle,
LOAD COMMAND REGISTER is issued with PROTECT
SETUP (60h) on A0–A7, and a bank address is issued on
BA0, BA1. The bank address is “Don’t Care,” but the
same bank address must be used for all three cycles.
The next command is ACTIVE. The third cycle is WRITE,
during which DEVICE PROTECT (F1h) is issued on
DQ0–DQ7. RP# must be brought to VHH prior to registration of the WRITE command. The ISM status bit will
be set on the following clock edge (subject to CAS latencies). RP# must be held at VHH until the PROTECT operation is complete (SR7 = 1).
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
PROGRAM/ERASE CYCLE ENDURANCE
SyncFlash memory is designed and fabricated to
meet advanced code and data storage requirements.
Operation outside specification limits may reduce the
number of PROGRAM and ERASE cycles that may be
performed on the device. Each block is designed and
processed for a minimum of 100,000-PROGRAM/
ERASE-cycle endurance.
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
FLASH
To allow for maximum power conservation, the device features a very low current, deep power-down
mode.
To enter this mode, the RP# pin (reset/power-down)
is taken to VSS ±0.2V. To prevent an inadvertent RESET,
RP# must be held at VSS for 50ns prior to the device
entering the reset mode. With RP# held at VSS, the device will enter the deep power-down mode. After the
device enters the deep power-down mode, a transition
from LOW to HIGH on RP# will result in a device powerup initialization sequence as outlined in the Device
Initialization section. Transitioning RP# from LOW to
HIGH after entering the reset mode but prior to entering deep power-down mode (i.e., less than 100ns) will
require a 1µs delay prior to issuing an executable command.
When the device enters the deep power-down
mode, all buffers excluding the RP# buffer are disabled
and the current draw is a maximum of 100µA at 3.6V
VCC. The input to RP# must remain at VSS during deep
power-down. Entering the RESET mode clears the Status Register.
4 MEG x 16
SYNCFLASH MEMORY
Table 3
Status Register Bit Definition1
R
VPS
ISMS
R
ES
WS
DPS
BISMS
DBS
15-9
8
7
6
5
4
3
2-1
0
STATUS
BIT #
STATUS REGISTER BIT
SR15SR9
DESCRIPTION
Reserved for future use.
SR8
VCC POWER SEQUENCE STATUS (VPS)
1 = Power-up incomplete error
0 = Power-up complete
VPS is set if there has been a power disruption that may
result in undefined device operation. A VPS error is
only cleared by re-initializing the device.
SR7
ISM STATUS (ISMS)
1 = Ready
0 = Busy
The ISMS bit displays the active status of the state machine
when performing PROGRAM or BLOCK ERASE. The
controlling logic polls this bit to determine when the erase
and program status bits are valid.
SR6
RESERVED
Reserved for future use.
SR5
ERASE/UNPROTECT BLOCK STATUS (ES) ES is set to “1” after the maximum number of ERASE cycles
1 = BLOCK ERASE or BLOCK
is executed by the ISM without a successful verify. This bit
UNPROTECT error
is also set to “1” if a BLOCK UNPROTECT operation is
0 = Successful BLOCK ERASE or
unsuccessful. ES is only cleared by a CLEAR STATUS
UNPROTECT
REGISTER command or by a RESET.
SR4
PROGRAM/PROTECT BLOCK STATUS (WS) WS is set to “1” after the maximum number of PROGRAM
1 = PROGRAM or BLOCK PROTECT error cycles is executed by the ISM without a successful verify.
0 = Successful BLOCK ERASE or
This bit is also set to “1” if a BLOCK or DEVICE PROTECT
UNPROTECT
operation is unsuccessful. WS is only cleared by a CLEAR
STATUS REGISTER command or by a RESET.
SR3
DEVICE PROTECT STATUS (DPS)
1 = Device protected, invalid operation
attempted
0 = Device unprotected or RP#
condition met
DPS is set to “1” if an invalid PROGRAM, ERASE, PROTECT
BLOCK, PROTECT DEVICE, or UNPROTECT ALL BLOCKS is
met. After one of these commands is issued, the condition
of RP#, the block protect bit, and the device protect bit is
compared to determine if the desired operation is allowed.
Must be cleared by CLEAR STATUS REGISTER or by a
RESET.
SR2
SR1
BANK ISM STATUS (BISMS)
BANKA1 ISM STATUS
BANKA0 ISM STATUS
When SR0 = 0, the bank under ISM control can be
decoded from SR1, SR2: [0,0] Bank0; [1,0] Bank1; [0,1]
Bank2; [1,1] Bank3. SR1, SR2 is valid when SR7 = 0. When
SR7 = 1, SR1, SR2 is reset to “0.”
SR0
DEVICE/BANK ISM STATUS (DBS)
1 = Device-level ISM operation
0 = Bank-level ISM operation
DBS is set to “1” if the ISM operation is a device-level
operation. A valid READ to any bank can immediately
follow the registration of an ISM PROGRAM operation.
When DBS is set to “0,” the ISM operation is a bank-level
operation. A READ to the bank under ISM control will
output the contents of the row activated prior to the LCR/
ACTIVE/WRITE command sequence. SR1 and SR2 can be
decoded to determine which bank is under ISM control.
SR0 is used in conjuction with SR7, and is valid when
SR7 = 0. When SR7 = 1, SR0 is reset to “0.”
NOTE: 1. SR3-SR5 must be cleared with CLEAR STATUS REGISTER prior to initiating an ISM WRITE operation for the status bits to
be valid.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
FLASH
RESERVED
4 MEG x 16
SYNCFLASH MEMORY
Table 4
Device Configuration
DEVICE
CONFIGURATION
CONFIGURATION
ADDRESS
DATA
Manufacturer Compatibility ID
000h
2Ch
Manufacturer compatibility ID read
Device ID
001h
D3h
Device ID read
Block Protect Bit
x02h
x02h
DQ0 = 1
DQ0 = 0
Block protected
Block unprotected
Device Protect Bit
003h
003h
DQ0 = 1
DQ0 = 0
Block protect modification prevented
Block protect modification enabled
CONDITION
NOTES
1
1
2, 3
3
STATUS BITS
ERROR DESCRIPTION5
SR5
SR4
SR3
0
0
0
No errors
0
1
0
PROGRAM, BLOCK PROTECT or DEVICE PROTECT error
0
1
1
Invalid BLOCK PROTECT or DEVICE PROTECT, RP# not valid (VHH)
0
1
1
Invalid BLOCK or DEVICE PROTECT, RP# not valid
1
0
0
ERASE or ALL BLOCK UNPROTECT error
1
0
1
Invalid ALL BLOCK UNPROTECT, RP# not valid (VHH)
1
1
0
Command sequencing error
NOTE: 1. DQ8–DQ15 are “Don’t Care.”
2. Address to read block protect bit is always the third location within each block.
x = 0, 4, 8, C; BA0, BA1 required.
3. DQ1–DQ7 are reserved, DQ8–DQ15 are “Don’t Care.”
4. SR3–SR5 must be cleared using CLEAR STATUS REGISTER.
5. Assumes that SR4 and SR5 reflect noncumulative results.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
30
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©2001, Micron Technology, Inc.
FLASH
Table 5
Status Register Error Decode4
4 MEG x 16
SYNCFLASH MEMORY
SELF-TIMED PROGRAM SEQUENCE1
COMPLETE PROGRAM STATUS-CHECK
SEQUENCE
Start
Start (PROGRAM completed)
LOAD COMMAND
REGISTER 40h
SR4, 5 = 1?
YES
Command Sequence Error 4
NO
SR3 = 1?
ACTIVE Row Address
YES
Invalid PROGRAM Error 4
NO
SR4 = 1?
YES
PROGRAM Error 4
NO
Status Register
Polling
SR7 = 1?
PROGRAM Successful
NO
YES
Complete Status 2
Check (optional)
PROGRAM Complete3
NOTE: 1.
2.
3.
4.
Sequence may be repeated for multiple PROGRAMs.
Complete status check is not required.
The bank will be in array read mode.
Status register bits 3–5 must be cleared using CLEAR STATUS REGISTER.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
FLASH
WRITE
Column Address/Data
4 MEG x 16
SYNCFLASH MEMORY
SELF-TIMED BLOCK ERASE SEQUENCE1
COMPLETE BLOCK ERASE
STATUS-CHECK SEQUENCE
Start
Start (ERASE or BLOCK UNPROTECT completed)
LOAD COMMAND
REGISTER 20h
SR4, 5 = 1?
YES
Command Sequence Error 4
YES
Invalid ERASE or
UNPROTECT Error 4
YES
BLOCK ERASE or
UNPROTECT Error 4
NO
ACTIVE Row Address
Block
Protected?
SR3 = 1?
NO
NO
YES
NO
RP# = VHH
ERASE or BLOCK UNPROTECT Successful
WRITE D0h
Status Register
SR7 = 1
NO
YES
Complete Status 2
Check (optional)
ERASE Complete 3
NOTE: 1.
2.
3.
4.
Sequence may be repeated to erase multiple blocks.
Complete status check is not required.
The bank will be in the array read mode.
Status register bits 3–5 must be cleared using CLEAR STATUS REGISTER.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
32
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
FLASH
SR5 = 1?
4 MEG x 16
SYNCFLASH MEMORY
BLOCK PROTECT SEQUENCE1
COMPLETE BLOCK
STATUS-CHECK SEQUENCE
Start
Start (BLOCK or DEVICE PROTECT completed)
LOAD COMMAND
REGISTER 60h
SR4 = 1?
YES
BLOCK or DEVICE
PROTECT Error 4
YES
Command Sequence Error 4
YES
Invalid BLOCK/DEVICE
PROTECT Error 4
NO
SR4, 5 = 1?
ACTIVE Row
NO
NO
SR3 = 1?
NO
YES
BLOCK or DEVICE PROTECT Successful
RP# = VHH
WRITE 01h
Status Register
SR7 = 1
NO
YES
Complete Status 2
Check (optional)
BLOCK PROTECT Complete 3
NOTE: 1.
2.
3.
4.
Sequence may be repeated for multiple BLOCK PROTECTs.
Complete status check is not required.
The bank will be in array read mode.
Status register bits 3–5 must be cleared using CLEAR STATUS REGISTER.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
33
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©2001, Micron Technology, Inc.
FLASH
Device
Protected?
4 MEG x 16
SYNCFLASH MEMORY
DEVICE PROTECT SEQUENCE1
BLOCK UNPROTECT SEQUENCE
Start
Start
LOAD COMMAND
REGISTER 60h
LOAD COMMAND
REGISTER 60h
ACTIVE Row
ACTIVE Row
Device
Protected?
NO
YES
Block 0
or Block 15
Protected?
FLASH
YES
RP# = VHH
WRITE F1h
YES
Unprotect
Block 0 or
Block 15?
NO
NO
Status Register
RP# = VHH
SR7 = 1
NO
YES
WRITE D0h
Complete Status
Check (optional)
Status Register
DEVICE PROTECT Complete2, 3
SR7 = 1
NO
YES
Complete Status
2, 3
Check (optional)
ALL BLOCKS UNPROTECT Complete 4
NOTE: 1.
2.
3.
4.
Once the device protect bit is set, it cannot be reset.
Complete status check is not required.
For complete details, see Complete Block Status Check Sequence.
The device will remain in the array read mode; a READ may be issued to any bank after the WRITE (D0h) is registered.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
34
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
4 MEG x 16
SYNCFLASH MEMORY
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on RP# Relative to VSS .................... -1V to +10V
Voltage on VCC, VCCP or VCCQ Supply or Inputs,
Relative to VSS ....................................... -1V to +3.6V
Voltage on I/O Pins Relative to VSS .............. VCCQ ±0.3V
Operating Temperature,
TA (ambient) ........................................ 0ºC to +70ºC
Storage Temperature (plastic) ........... -55ºC to +150ºC
Power Dissipation ........................................................ 1W
Short Circuit Output Current ................................ 50mA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
PARAMETER/CONDITION
SYMBOL
MIN
MAX
VCC
3.0
3.6
V
VCCQ
3.0
3.6
V
HARDWARE PROTECTION VOLTAGE
(RP# only)
VHH
8.5
10
V
INPUT HIGH VOLTAGE:
Logic 1; All Inputs
VIH
2
VCCQ + 0.3
V
INPUT LOW VOLTAGE:
Logic 0; All Inputs
VIL
- 0.3
0.8
V
IL
-5
5
µA
IOZ
-5
5
µA
VOH
VOH
VOL
VOL
2.4
VCC SUPPLY VOLTAGE
VCCQ SUPPLY VOLTAGE
INPUT LEAKAGE CURRENT:
Any input 0V ≤ VIN ≤ VCC
(All other pins not under test = 0V)
OUPUT LEAKAGE CURRENT:
DQs are disabled; 0V ≤ VOUT ≤ VCCQ
UNITS NOTES
OUTPUT LEVELS:
Output High Voltage
Output Low Voltage
(IOUT
(IOUT
(IOUT
(IOUT
=
=
=
=
-4mA)
-100mA)
-4mA)
100mA)
0.4
V
V
V
V
NOTE: 1. All voltages referenced to VSS.
2. An initial pause of 100µs is required after power-up. (VCC, VCCP and VCCQ must be powered up simultaneously. VSS and
VSSQ must be at same potential.)
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
FLASH
(Notes: 1, 2); Commercial Temperature (0ºC ≤ TA ≤ +70ºC)
4 MEG x 16
SYNCFLASH MEMORY
ICC SPECIFICATIONS AND CONDITIONS
(Notes: 1, 2, 3); Commercial Temperature (0ºC ≤ TA ≤ +70ºC)
MAX
PARAMETER/CONDITION
-10
-12
VCC OPERATING CURRENT:
Active Mode; Burst = 2; READ; tCK = 15ns; tRC = tRC (MIN);
CAS latency = 3
ICCR1
125
120
mA
4,5,6
VCC OPERATING CURRENT:
Burst Mode; Continuous Burst;
All banks active; READ; tCK = 15ns; CAS latency = 3
ICCR2
100
95
mA
4, 5, 6
VCC STANDBY CURRENT:
Active Mode; CKE = LOW; Burst in progress
ICCS1
10
10
mA
VCC STANDBY CURRENT:
Power-Down Mode; CKE = LOW; No burst in progress
ICCS2
2
2
mA
VCC DEEP POWER-DOWN CURRENT:
RP# = VSS ±0.2V
ICCDP
300
300
µA
ICCW + IPPW
60
60
mA
IPPR1
250
125
µA
ICCE+IPPE
80
80
mA
IPPDP
1
1
µA
SYMBOL
MIN
MAX UNITS NOTES
Input Capacitance: CLK
CI1
2.5
6.5
pF
7
Input Capacitance: All other input-only pins
CI2
2.5
6.5
pF
7
Input/Output Capacitance: DQs
CIO
4.0
7.0
pF
7
PROGRAM CURRENT
VCCP OPERATING CURRENT:
Active Mode; Burst = 2; READ; tRC = tRC (MIN); CAS latency = 3
VCCP OPERATING CURRENT:
ERASE CURRENT
VCCP DEEP POWER-DOWN CURRENT:
RP# = VSS ±0.2V
UNITS NOTES
FLASH
SYMBOL
CAPACITANCE
PARAMETER
NOTE: 1. All voltages referenced to VSS.
2. An initial pause of 100µs is required after power-up. (VCC, VCCP, and VCCQ must be powered up simultaneously. VSS and
VSSQ must be at same potential.)
3. ICC specifications are tested after the device is properly initialized.
4. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the
outputs open.
5. The ICC current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is
slower as the CAS latency is reduced.
6. Address transitions average one transition every 30ns.
7. This parameter is sampled. VCC = VCCQ; f = 1 MHz, TA = +25ºC.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
4 MEG x 16
SYNCFLASH MEMORY
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 1, 2, 3, 4, 5); Commercial Temperature (0ºC ≤ TA ≤ +70ºC)
AC CHARACTERISTICS
PARAMETER
Access time from CLK (pos. edge)
Address hold time
Address setup time
CLK high level width
CLK low level width
Clock cycle time
CL = 3
CL = 2
CL = 1
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time
CL = 3
CL = 2
CL = 1
Data-out low-impedance time
Data-out hold time
ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B command
Transition time
MIN
-10
MAX
7
9
27
2
3
3.5
3.5
10
15
30
2
3
2
3
2
3
MIN
2
3
4
4
12
15
30
2
3
2
3
2
3
8
10
15
2
3
90
30
20
0.3
-12
MAX
9
10
27
1.2
9
10
15
2
3
100
30
20
1
1.2
UNITS NOTES
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
ns
6
ns
6
ns
ns
ns
ns
ns
ns
7
NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature
range is ensured.
2. An initial pause of 100µs is required after power-up. (VCC, VCCP, and VCCQ must be powered up simultaneously. VSS and
VSSQ must be at same potential.)
3. In addition to meeting the transition rate specification, the clock and CKE must transit between V IH and VIL (or between
VIL and VIH) in a monotonic manner.
4. Outputs measured at 1.5V with equivalent load:
Q
50pF
5. AC timing and ICC tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point.
6. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to V OH or VOL. The
last valid data element will meet tOH before going High-Z.
7. AC characteristics assume tT = 1ns.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
37
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
FLASH
CL = 3
CL = 2
CL = 1
SYM
tAC
tAC
tAC
tAH
tAS
tCH
tCL
tCK
tCK
tCK
tCKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ
tHZ
tHZ
tLZ
tOH
tRC
tRCD
tRRD
tT
4 MEG x 16
SYNCFLASH MEMORY
AC FUNCTIONAL CHARACTERISTICS
(Notes: 1-6); Commercial Temperature (0ºC ≤ TA ≤ +70ºC)
CL = 3
CL = 2
CL = 1
SYMBOL
tCCD
tCKED
tPED
tDQD
tDQM
tDQZ
tDWD
tDAL
tDPL
tMRD
tROH
tROH
tROH
-10
1
1
1
0
0
2
0
4
1
2
3
2
1
-12
1
1
1
0
0
2
0
4
1
2
3
2
1
UNITS
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
NOTES
7
8
8
7
7
7
7
7
7
7
7
NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature
range is ensured.
2. An initial pause of 100µs is required after power-up. (VCC, VCCP, and VCCQ must be powered up simultaneously. VSS and
VSSQ must be at same potential.)
3. AC characteristics assume tT = 1ns.
4. In addition to meeting the transition rate specification, the clock and CKE must transit between V IH and VIL (or between
VIL and VIH) in a monotonic manner.
5. Outputs measured at 1.5V with equivalent load:
Q
50pF
6. AC timing and ICC tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point.
7. Required clocks specified by JEDEC functionality and not dependent on any timing parameter.
8. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate.
ERASE AND PROGRAM TIMING
CHARACTERISTICS
Commercial Temperature (0ºC £ TA £ +70ºC)
-10/-12
PARAMETER
Word program time
Block erase time
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
MIN
MAX UNITS
5
5,000
µs
1.1
13
s
38
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
FLASH
PARAMETER
READ/WRITE command to READ/LOAD COMMAND REGISTER command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQM to data high-impedance during READs
WRITE command to input data delay
Data-in to ACTIVE command
Data-in to ACTIVE TERMINATE command
LOAD MODE REGISTER command to ACTIVE command
Data-out to High-Z from ACTIVE TERMINATE command
4 MEG x 16
SYNCFLASH MEMORY
INITIALIZE AND LOAD MODE REGISTER
T0
T1
((
))
((
))
CLK
tCKS
tCKH
Tn+1
COMMAND
((
))
((
))
DQM
((
))
((
))
Tn + 4
tCH
((
))
((
))
CKE
Tn + 3
tCL
Tn + 2
tCK
tCMH tCMS
LOAD MODE
REGISTER
ACTIVE
NOP
((
))
VCC, VCCP,
VCCQ
((
))
RP#1
tAS
((
))
((
))
ADDRESS
High-Z
DQ
tAH
OPCODE
ROW
((
))
tMRD
T = 100µs
3, 4, 5
Program Mode Register
Power-up:2
DON’T CARE
VCC, VCCP, VCCQ,
CLK stable
UNDEFINED
TIMING PARAMETERS
-10
SYMBOL*
tAH
MIN
-12
MAX
MIN
-10
MAX
UNITS
SYMBOL*
2
3
3.5
2
3
4
ns
ns
ns
tCK (1)
3.5
10
4
12
ns
ns
tCMH
tCK (3)
tCK (2)
15
15
ns
tAS
tCH
tCL
MIN
-12
MAX
MIN
MAX
UNITS
30
30
ns
2
3
2
3
ns
ns
tCMS
2
3
2
3
ns
ns
tMRD
2
2
tCK
tCKH
tCKS
*CAS latency indicated in parentheses.
NOTE: 1. RP# = VHH or VIH
2. VCC, VCCP, VCCQ = 3.3V
3. The nvmode register contents are automatically loaded into the mode register upon power-up initialization, LOAD
MODE REGISTER cycle is required to enter new mode register values.
4. JEDEC and PC100 specify three clocks.
5. If CS is HIGH at clock time, all commands applied are NOP, with CKE a “Don’t Care.”
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
4 MEG x 16
SYNCFLASH MEMORY
CLOCK SUSPEND MODE1
T0
T1
T2
tCK
CLK
T3
T4
T5
tCL
tCH
tCKS tCKH
CKE
tCKS
tCKH
tCMS
tCMH
COMMAND
READ
NOP
tCMS
NOP
NOP
NOP
NOP
tCMH
DQM
tAS
A0–A11
tAH
COLUMN m2
tAS
BA
tAH
BANK
tAC
tOH
tAC
DQ
tHZ
DOUT m
tLZ
DOUT m+1
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-10
SYMBOL*
tAC
MIN
-12
MAX
MIN
-10
MAX
UNITS
SYMBOL*
(3)
7
9
ns
tCKS
(2)
tAC (1)
tAH
9
27
10
27
tCMH
tAC
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
tCKH
MIN
-12
MAX
MIN
MAX
UNITS
3
2
3
2
ns
ns
tDH
3
2
3
2
ns
ns
3
2
2
ns
ns
ns
3
3.5
3
4
ns
ns
tDS
3.5
10
15
4
12
15
ns
ns
ns
tHZ (2)
tLZ
2
2
ns
ns
30
2
30
2
ns
ns
tOH
3
3
ns
tCMS
tHZ (3)
3
8
10
tHZ (1)
9
10
15
15
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 2, CAS latency = 3.
2. x16: A0–A7.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
40
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
4 MEG x 16
SYNCFLASH MEMORY
READ1
T0
T1
tCK
CLK
tCKS
T2
T3
T4
T5
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
tCMS tCMH
DQM
tAS
A0–A11
ROW
tAS
BA
tAH
COLUMN m2
ROW
BANK
BANK
tAH
BANK
tAC
tOH
tAC
DQ
tLZ
tRCD
DOUT m
tAC
tOH
tAC
tOH
DOUT m+1
DOUT m+2
tOH
DOUT m+3
tHZ
tRP3
CAS Latency
tRAS3
tRC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-10
SYMBOL*
tAC (3)
tAC (2)
tAC (1)
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
tCKH
MIN
-12
MAX
7
9
27
MIN
-10
MAX
9
10
27
UNITS
ns
ns
ns
SYMBOL*
tCKS
MIN
tCMH
3
2
tCMS
3
2
3
2
3
ns
ns
tHZ (3)
3.5
3.5
10
4
4
12
ns
ns
ns
tHZ (1)
15
30
15
30
ns
ns
tRC
2
2
ns
tOH
tRCD
MIN
MAX
3
2
9
10
15
UNITS
ns
ns
3
8
10
tHZ (2)
tLZ
-12
MAX
15
ns
ns
ns
2
2
ns
ns
3
90
30
3
100
30
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, CAS latency = 2.
2. x16: A0–A7.
3. tRAS and tRP are referenced to show compatibility with SDRAM timings; no values are given.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
41
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
4 MEG x 16
SYNCFLASH MEMORY
ALTERNATING BANK READ ACCESSES1
T0
T1
T2
tCK
CLK
T3
T4
T5
T6
T7
T8
READ
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
ACTIVE
NOP
tCMS tCMH
DQM
tAS
A0–A11
ROW
tAS
BA
tAH
COLUMN m2
ROW
COLUMN b2
ROW
BANK 0
BANK 1
BANK 1
BANK 0
tAH
BANK 0
tAC
tOH
tAC
DQ
tLZ
tRCD - BANK 0
DOUT m
tAC
tOH
DOUT m+1
tAC
tOH
DOUT m+2
tAC
tOH
tAC
tOH
DOUT m+3
DOUT b
tRP - BANK 0
CAS Latency - BANK 0
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRCD - BANK 1
tRRD
CAS Latency - BANK 1
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-10
SYMBOL*
tAC (3)
MIN
tAC
(2)
tAC (1)
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
-12
MAX
7
MIN
9
27
-10
MAX
9
UNITS
ns
SYMBOL*
10
27
ns
ns
tCKS
tCKH
tCMH
MIN
MAX
UNITS
2
3
2
ns
ns
ns
3
2
3
2
ns
ns
3
100
30
ns
ns
ns
20
ns
2
3
4
ns
ns
ns
tCMS
3.5
10
4
12
ns
ns
tRC
tRCD
3
90
30
15
30
15
30
ns
ns
tRRD
20
tOH
MIN
2
3
2
2
3
3.5
tLZ
-12
MAX
*CAS latency indicated in parentheses.
NOTE: 1. For this example, CAS latency = 2.
2. x16: A0–A7.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
42
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
4 MEG x 16
SYNCFLASH MEMORY
READ – FULL-PAGE BURST1
T0
T1
T2
tCL
CLK
T3
T4
T5
T6
tCKS
Tn + 1
((
))
((
))
tCK
tCH
Tn + 2
Tn + 3
Tn + 4
tCKH
((
))
((
))
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
tCMS tCMH
tAS
tAH
ROW
tAS
BA
COLUMN m2
((
))
((
))
BANK
((
))
((
))
tAH
BANK
NOP
BURST TERM
NOP
NOP
((
))
((
))
DQM
A0–A11
((
))
((
))
tAC
tAC
DOUT m
DQ
tAC
tOH
OH
DOUT m+1
tLZ
tAC ( (
tOH ) )
tAC
tOH
((
))
DOUT m+2
((
))
DOUT m-1
tAC
tOH
tOH
DOUT m
DOUT m+1
tHZ
256 (x16) locations within
the same row.
tRCD
Full page completed.
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.3
CAS Latency
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-10
SYMBOL*
tAC (3)
tAC (2)
tAC
MIN
-12
MAX
7
9
MIN
-10
MAX
9
10
UNITS
ns
ns
27
SYMBOL*
ns
3
2
3
3
2
3
ns
ns
ns
tCMH
tAS
3
3.5
3.5
3
4
4
ns
ns
ns
tHZ (3)
12
15
ns
ns
tLZ
tCK (2)
10
15
tCK (1)
30
30
ns
tRCD
tCK (3)
UNITS
tCKS
ns
ns
tCL
MAX
2
2
tCH
MIN
2
2
27
-12
MAX
tCKH
tAH
(1)
MIN
tCMS
8
10
tHZ (2)
tHZ (1)
tOH
15
9
10
ns
ns
15
2
3
2
3
ns
ns
ns
30
30
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the CAS latency = 2.
2. x16: A0–A7.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
4 MEG x 16
SYNCFLASH MEMORY
READ – DQM OPERATION1
T0
T1
tCK
CLK
tCKS
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
NOP
NOP
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
tCMS tCMH
DQM
tAS
A0–A11
COLUMN m2
ROW
tAS
BA
tAH
tAH
BANK
BANK
tAC
DQ
tOH
DOUT m
tLZ
tRCD
tAC
tOH
tAC
tHZ
tOH
DOUT m+2
DOUT m+3
tLZ
tHZ
CAS Latency
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-10
SYMBOL*
tAC (3)
MIN
tAC
(2)
tAC (1)
tAH
-12
MAX
7
MIN
UNITS
ns
10
27
SYMBOL*
MAX
UNITS
ns
tCKS
3
2
3
3
2
3
ns
ns
ns
3
3.5
3.5
3
4
4
ns
ns
ns
tHZ (3)
12
15
ns
ns
tLZ
tCK (2)
10
15
tCK (1)
30
30
ns
tRCD
tCK (3)
MIN
2
2
tCL
-12
MAX
2
2
tCH
MIN
tCKH
ns
ns
ns
tAS
9
27
-10
MAX
9
tCMH
tCMS
8
10
tHZ (2)
tHZ (1)
tOH
15
9
10
ns
ns
15
2
3
2
3
ns
ns
ns
30
30
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, CAS latency = 2.
2. x16: A0–A7.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
4 MEG x 16
SYNCFLASH MEMORY
PROGRAM/ERASE1
(BANK a FOLLOWED BY READ TO BANK b)
T0
T1
T2
T3
t CK
CLK
T4
t CL
T5
T6
T7
T8
NOP
NOP
NOP
T9
t CH
t CKS t CKH
CKE
tCMS tCMH
COMMAND
LCR
ACTIVE
NOP
WRITE
READ
NOP
NOP
t CMS t CMH
DQM
t AS
A0–A11
BA
COMCODE2
t AH
ROW
BANK a
BANK a
COLUMN3 m
COLUMN n
BANK a
BANK b
t DS
t DH
t DS
DIN4 m
DQ
t DH
DOUT n
DOUT n + 1
High-Z
t RCD
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-10
SYMBOL*
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
MIN
2
3
3.5
3.5
10
15
30
-12
MAX
MIN
2
3
4
4
12
15
30
-10
MAX
UNITS
ns
ns
ns
ns
ns
SYMBOL*
tCKH
tCKS
tCMH
2
3
2
-12
MAX
MIN
2
3
2
MAX
UNITS
ns
ns
ns
tCMS
3
3
ns
tDH
2
3
1.5
3
ns
ns
tDS
ns
ns
MIN
*CAS latency indicated in parentheses.
NOTE: 1.
2.
3.
4.
For this example, READ burst length = 2, CAS = 3.
Com-code = 40h for WRITE, 20h for ERASE (see Truth Table 2).
Column address is “Don’t Care” for ERASE operation.
DIN = D0h (erase confirm) for ERASE operation.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
45
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
PROGRAM/ERASE1
(BANK a FOLLOWED BY READ TO BANK a)
T0
tCK
CLK
T1
tCL
tCKS
tCKH
tCMS
tCMH
T2
T3
T4
T5
T6
READ
NOP
NOP
Tn
Tn + 1
Tn + 2
Tn + 3
READ3
NOP
NOP
NOP
Tn + 4
Tn + 5
tCH
CKE
COMMAND
LCR
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
NOP
READ
t CMS t CMH
DQM
tAS
A0–A11
COMCODE2
tAS
BA
BANK a
tAH
ROW
COLUMN4 m
COLUMN n
BANK a
BANK a
ROW
COLUMN
BANK a
BANK a
tAH
BANK a
tDS
t DS t DH
tDH
DIN5 m
DQ
DOUT n
SR7 = 0
DOUT
High-Z
SR7 = 1
ISM PROGRAM or ERASE
operation is complete
T = 10µs typical/word
46
DON’T CARE
UNDEFINED
TIMING PARAMETERS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
MIN
2
3
3.5
3.5
10
15
30
-12
MAX
MIN
2
3
4
4
12
15
30
-10
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
tCKH
tCKS
tCMH
tCMS
tDH
tDS
MIN
2
3
2
3
2
3
-12
MAX
MIN
2
3
2
3
2
3
MAX
UNITS
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. ACTIVE/READ or READ will output the contents of the row activated prior to the LCR/active/write command sequence. This example illustrates the
timing for activating a new row in bank a. For this example, READ burst length = 2, CAS latency = 2.
2. Com-code = 40h for PROGRAM, 20h for ERASE (see Truth Table 2).
3. LCR/ACTIVE cycles must be initiated prior to READ according to Truth Table 2 for a status register read command sequence.
4. Column address is “Don’t Care” for ERASE operation.
5. DIN = D0h (erase confirm) for ERASE operation.
4 MEG x 16
SYNCFLASH MEMORY
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
-10
SYMBOL*
tAH
tAS
4 MEG x 16
SYNCFLASH MEMORY
54-PIN TSOP TYPE II
(400 MIL)
22.30
SEE DETAIL A
22.14
.71
.80 TYP
.10 (2X)
.45
.30
2.80
11.86
11.66
PIN #1 ID
10.24
10.08
.75 (2X)
.18
.13
1.00 (2X)
.25
.20
.05
.10
1.2 MAX
.60
.40
.80
TYP
DETAIL A
NOTE: 1. All dimensions in millimeters MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
DATA SHEET DESIGNATION
This data sheet contains minimum and maximum limits specified over the complete power supply and
temperature range for production devices. Although considered final, these specifications are subject to change,
as further product development and data characterization sometimes occur.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron and SyncFlash are registered trademarks and the Micron logo, and M logo are trademarks of Micron Technology, Inc.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
47
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
4 MEG x 16
SYNCFLASH MEMORY
REVISION HISTORY
Rev. 6 ......................................................................................................................................................................... 9/01
• Added erase and program timing characteristics
• Updated the device protect sequence
• Removed the “Preliminary” designation
Rev. 5, PRELIMINARY .............................................................................................................................................. 7/01
Changed tAH, tCKH, tCMH, tDH from 1ns to 2ns
Rev. 4, ADVANCE .................................................................................................................................................... 5/01
Changed deep power-down current from 100µA to 300µA
Rev. 3, ADVANCE .................................................................................................................................................... 4/01
Changes to VCCP Operating Current
Changes to MAX Capacitance Parameters
Rev. 2, ADVANCE .................................................................................................................................................... 2/01
Changes to Absolute Maximum Ratings
Changes to ICC Specifications and Conditions
Original document, Rev. 11/00, ADVANCE ......................................................................................................... 11/00
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
48
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.