MOSEL V53C808H

MOSEL VITELIC
PRELIMINARY
V53C808H
HIGH PERFORMANCE
1M x 8 BIT EDO PAGE MODE
CMOS DYNAMIC RAM
OPTIONAL SELF REFRESH
HIGH PERFORMANCE
35
40
45
50
Max. RAS Access Time, (tRAC)
35 ns
40 ns
45 ns
50 ns
Max. Column Address Access Time, (tCAA)
18 ns
20 ns
22 ns
24 ns
Min. Extended Data Out Mode Cycle Time, (tPC)
14 ns
15 ns
17 ns
19 ns
Min. Read/Write Cycle Time, (tRC)
70 ns
75 ns
80 ns
90 ns
Features
Description
■ 1M x 8-bit organization
■ EDO Page Mode for a sustained data rate
of 72 MHz
■ RAS access time: 35, 40, 45, 50 ns
■ Low power dissipation
■ Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
■ Optional Self Refresh (V53C808SH)
■ Refresh Interval: 1024 cycles/16 ms
■ Available in 28-pin 400 mil SOJ package
■ Single +5V ± 10% Power Supply
■ TTL Interface
The V53C808H is a ultra high speed 1,048,576 x
8 bit CMOS dynamic random access memory. The
V53C808H offers a combination of features: Page
Mode with Extended Data Output for high data
bandwidth, and Low CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Page Mode
with Extended Data Output operation allows random access of up to 1024 x 8 bits within a row with
cycle times as fast as 14 ns.
The V53C808H is ideally suited for graphics, digital signal processing and high-performance computing systems.
Device Usage Chart
Operating
Temperature
Range
0°C to 70 °C
V53C808H Rev. 1.5 April 1998
Package Outline
Access Time (ns)
Power
K
T
35
40
45
50
Std.
Temperature
Mark
•
•
•
•
•
•
•
Blank
1
V53C808H
MOSEL VITELIC
Part Name
Self Refresh
Supply Voltage
Package
Speed
V53C808HKxx
No Self Refresh
5V
SOJ
35/40/45/50
V53C808HTxx
No Self Refresh
5V
TSOP
35/40/45/50
V53C808SHKxx
Optional Standard Self Refresh (16ms)
5V
SOJ
35/40/45/50
V53C808SHTxx
Optional Standard Self Refresh (16ms)
5V
TSOP
35/40/45/50
V
5
3
C
8
FAMILY
0
8
S
H
DEVICE
PKG
S (OPTIONAL STANDARD
SELF REFRESH)
SPEED
( t RAC)
SUPPLY
VOLTAGE
35
40
45
50
K (SOJ)
27
3
26
4
25
5
24
6
23
7
8
9
400 mil
28
2
22
21
20
10
19
11
18
12
17
13
16
14
15
VSS
I/O8
I/O7
I/O6
I/O5
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
808H-02
V53C808H Rev. 1.5 April 1998
(35 ns)
(40 ns)
(45 ns)
(50 ns)
808H-01
Pin Names
28-Pin Plastic SOJ
PIN CONFIGURATION
Top View
1
BLANK (0¡C to 70¡C)
BLANK (NORMAL)
H (5V)
VCC
I/O1
I/O2
I/O3
I/O4
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
TEMP.
PWR.
2
A0–A9
Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
I/O1–I/O8
Data Input, Output
VCC
+5V Supply
VSS
0V Supply
NC
No Connect
V53C808H
MOSEL VITELIC
Absolute Maximum Ratings*
Capacitance*
TA = 25°C, VCC = 5 V ± 10%, f = 1 MHz
Ambient Temperature
Under Bias ................................. –10°C to +80°C
Storage Temperature (plastic) ..... –55°C to +125°C
Voltage Relative to VSS .................–1.0 V to +7.0 V
Data Output Current ..................................... 50 mA
Power Dissipation .......................................... 1.4 W
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Symbol
Parameter
Typ.
Max.
Unit
CIN1
Address Input
3
4
pF
CIN2
RAS, CAS, WE, OE
4
5
pF
COUT
Data Input/Output
5
7
pF
* Note: Capacitance is sampled and not 100% tested
Block Diagram
1M x 8
OE
WE
CAS
RAS
RAS CLOCK
GENERATOR
CAS CLOCK
GENERATOR
WE CLOCK
GENERATOR
OE CLOCK
GENERATOR
VCC
VSS
I/O 1
DATA I/O BUS
I/O 2
COLUMN DECODERS
Y0 -Y 9
SENSE AMPLIFIERS
I/O 3
I/O
BUFFER
I/O 4
I/O 5
I/O 6
REFRESH
COUNTER
I/O 7
I/O 8
1024 x 8
A1
•
•
•
A7
A9
V53C808H Rev. 1.5 April 1998
X0 -X9
ROW
DECODERS
A0
ADDRESS BUFFERS
AND PREDECODERS
10
1024
MEMORY
ARRAY
1024 x 1024 x8
808H-04
3
V53C808H
MOSEL VITELIC
DC and Operating Characteristics
TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0 V, unless otherwise specified.
Symbol
Parameter
ILI
Input Leakage Current
(any input pin)
ILO
Output Leakage Current
(for High-Z State)
ICC1
VCC Supply Current,
Operating
ICC2
VCC Supply Current,
TTL Standby
ICC3
VCC Supply Current,
RAS-Only Refresh
ICC4
VCC Supply Current,
EDO Page Mode
Operation
Access
Time
V53C808H
Min.
Typ.
Max.
Unit
Test Conditions
Notes
–10
10
mA
VSS £ VIN £ VCC
–10
10
mA
VSS £ VOUT £ VCC
RAS, CAS at VIH
35
160
mA
tRC = tRC (min.)
40
150
45
145
50
135
2
mA
RAS, CAS at VIH
other inputs ³ VSS
35
160
mA
tRC = tRC (min.)
2
40
150
45
145
50
135
35
95
mA
Minimum cycle
1, 2
40
90
45
85
50
80
1, 2
ICC5
VCC Supply Current,
Standby, Output Enabled
2.0
mA
RAS = VIH, CAS = VIL
other inputs ³ VSS
ICC6
VCC Supply Current,
CMOS Standby
2.0
mA
RAS ³ VCC – 0.2 V,
CAS ³ VCC– 0.2 V,
All other inputs ³ VSS
ICC7
Self Refresh Current
400
mA
CBR Cycle with tRAS ³ tRASS
(Min.) and CAS = VIL;
WE = VCC–0.2V; A0–A8 and
DIN = VCC–0.2V
VCC
Supply Voltage
4.5
5.5
V
VIL
Input Low Voltage
–1
0.8
V
3
VIH
Input High Voltage
2.4
VCC + 1
V
3
VOL
Output Low Voltage
0.4
V
IOL = 2 mA
VOH
Output High Voltage
V
IOH = –2 mA
V53C808H Rev. 1.5 April 1998
5.0
2.4
4
1
V53C808H
MOSEL VITELIC
AC Characteristics
TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
35
40
45
50
#
Symbol
Parameter
1
tRAS
RAS Pulse Width
35
2
tRC
Read or Write Cycle Time
70
75
80
90
ns
3
tRP
RAS Precharge Time
25
25
25
30
ns
4
tCSH
CAS Hold Time
35
40
45
50
ns
5
tCAS
CAS Pulse Width
7
8
9
9
ns
6
tRCD
RAS to CAS Delay
16
7
tRCS
Read Command Setup Time
0
0
0
0
ns
8
tASR
Row Address Setup Time
0
0
0
0
ns
9
tRAH
Row Address Hold Time
6
7
8
9
ns
10
tASC
Column Address Setup Time
0
0
0
0
ns
11
tCAH
Column Address Hold Time
4
5
6
7
ns
12
tRSH (R)
RAS Hold Time (Read Cycle)
14
14
15
15
ns
13
tCRP
CAS to RAS Precharge Time
5
5
5
5
ns
14
tRCH
Read Command Hold Time
Referenced to CAS
0
0
0
0
ns
5
15
tRRH
Read Command Hold Time
Referenced to RAS
0
0
0
0
ns
5
16
tROH
RAS Hold Time Referenced to OE
8
8
9
10
ns
17
tOAC
Access Time from OE
12
12
13
14
ns
18
tCAC
Access Time from CAS (EDO)
12
12
13
14
ns
6, 7
19
tRAC
Access Time from RAS
35
40
45
50
ns
6, 8, 9
20
tCAA
Access Time from Column Address
18
20
22
24
ns
6, 7, 10
21
tLZ
CAS to Low-Z Output
0
ns
16
22
tHZ
Output buffer turn-off delay time
0
ns
16
23
tAR
Column Address Hold Time from RAS
28
24
tRAD
RAS to Column Address Delay Time
11
25
tRSH (W)
RAS or CAS Hold Time in Write Cycle
12
12
13
14
ns
26
tCWL
Write Command to CAS Lead Time
12
12
13
14
ns
27
tWCS
Write Command Setup Time
0
0
0
0
ns
28
tWCH
Write Command Hold Time
5
5
6
7
ns
29
tWP
Write Pulse Width
5
5
6
7
ns
30
tWCR
Write Command Hold Time from RAS
28
30
35
40
ns
31
tRWL
Write Command to RAS Lead Time
12
12
13
14
ns
V53C808H Rev. 1.5 April 1998
Min. Max. Min. Max. Min. Max. Min. Max. Unit
75K
23
40
17
75K
28
0
6
0
5
12
18
75K
32
0
6
30
17
45
0
13
19
75K
36
0
7
35
20
50
0
8
40
23
14
Notes
ns
ns
4
ns
26
ns
11
12, 13
V53C808H
MOSEL VITELIC
AC Characteristics (Cont’d)
35
40
45
50
#
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
32
tDS
Data in Setup Time
0
0
0
0
ns
14
33
tDH
Data in Hold Time
4
5
6
7
ns
14
34
tWOH
Write to OE Hold Time
5
6
7
8
ns
14
35
tOED
OE to Data Delay Time
5
6
7
8
ns
14
36
tRWC
Read-Modify-Write Cycle Time
105
110
115
130
ns
37
tRRW
Read-Modify-Write Cycle RAS
Pulse Width
70
75
80
87
ns
38
tCWD
CAS to WE Delay
28
30
32
34
ns
12
39
tRWD
RAS to WE Delay in
54
58
62
68
ns
12
40
tCRW
CAS Pulse Width (RMW)
46
48
50
52
ns
41
tAWD
Col. Address to WE Delay
35
38
41
42
ns
42
tPC
EDO Page Mode Read or Write
Cycle Time
14
15
17
19
ns
43
tCP
CAS Precharge Time
4
5
6
7
ns
44
tCAR
Column Address to RAS Setup Time
18
20
22
24
ns
45
tCAP
Access Time from Column Precharge
46
tDHR
Data in Hold Time Referenced to RAS
28
30
35
40
ns
47
tCSR
CAS Setup Time
CAS-before-RAS Refresh
10
10
10
10
ns
48
tRPC
RAS to CAS Precharge Time
0
0
0
0
ns
49
tCHR
CAS Hold Time
CAS-before-RAS Refresh
8
8
10
12
ns
50
tPCM
EDO Page Mode Read-Modify-Write
Cycle Time
58
60
65
70
ns
51
tT
Transition Time (Rise and Fall)
3
52
tREF
Refresh Interval (1024 Cycles)
16
16
53
tCOH
Output Hold After CAS Low
5
5
21
50
23
3
50
25
3
50
27
3
ns
50
ns
16
16
ms
5
5
ns
Notes
12
7
15
Optional Self Refresh
54
tRASS
RAS Pulse Width During Self Refresh
100
100
100
100
ms
18
55
tRPS
RAS Precharge Time During Self
Refresh
100
100
100
100
ns
18
56
tCHS
CAS Hold Time Width During Self
Refresh
100
100
100
100
ns
18
57
tCHD
CAS Low Time During Self
Refresh
100
100
100
100
ms
18
V53C808H Rev. 1.5 April 1998
6
V53C808H
MOSEL VITELIC
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the
output open.
2. ICC is dependent upon the number of address transitions. Specified IDD (max.) is measured with a maximum of two
transitions per address cycle in EDO Page Mode.
3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period
not to exceed 20 ns. All AC parameters are measured with VIL (min.) ³ VSS and VIH (max.) £ VDD.
4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA
(max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC.
5. Either tRRH or tRCH must be satisified for a Read Cycle to occur.
6. Measured with a load equivalent to one TTL input and 50 pF.
7. Access time is determined by the longest of tCAA, tCAC and tCAP.
8. Assumes that tRAD £ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.).
9. Assumes that tRCD £ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD
exceeds tRCD (max.).
10. Assumes that tRAD ³ tRAD (max.).
11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC.
12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
13. tWCS (min.) must be satisfied in an Early Write Cycle.
14. tDS and tDH are referenced to the latter occurrence of CAS or WE.
15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns.
16. Assumes a three-state test load (5 pF and a 500 Ohm Thevenin equivalent).
17. An initial 200 ms pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
18. Once CBR refresh or complete set of row refresh cycles must be completed upon exiting Self Refresh Mode.
V53C808H Rev. 1.5 April 1998
7
V53C808H
MOSEL VITELIC
Waveforms of Read Cycle
RAS
t RAS (1)
t AR (23)
VIH
t RC (2)
t RP (3)
VIL
t CRP (13)
CAS
t RSH (R)(12)
t CAS (5)
VIH
VIL
t RAH (9)
VIH
ROW ADDRESS
VIL
t CAH (11)
t ASC (10)
COLUMN ADDRESS
t RCH (14)
t CAR (44)
t RCS (7)
WE
t CRP (13)
t RAD (24)
t ASR (8)
ADDRESS
t CSH (4)
t RCD (6)
t RRH (15)
VIH
VIL
t ROH (16)
t HZ (22)
t CAA (20)
OE
t OAC (17)
VIH
VIL
t CAC (18)
t RAC (19)
I/O
t HZ (22)
t HZ (22)
VOH
VALID DATA-OUT
VOL
t LZ (21)
808H-05
Waveforms of Early Write Cycle
RAS
t AR (23)
V IH
t CSH (4)
t RCD (6)
t RAH (9)
V IH
V IL
ROW ADDRESS
t ASC (10)
t CWL (26)
t WCH (28)
t WP (29)
t WCS (27)
V IH
V IL
t RWL (31)
V IH
V IL
t DS (32)
I/O
t CAR (44)
t CAH (11)
COLUMN ADDRESS
t WCR (30)
OE
t CRP (13)
V IL
t RAD (24)
WE
t RSH (W)(25)
t CAS (5)
V IH
t ASR (8)
ADDRESS
t RP (3)
V IL
t CRP (13)
CAS
t RC (2)
t RAS (1)
V IH
V IL
t DHR (46)
t DH (33)
VALID DATA-IN
HIGH-Z
808H-06
Don’t Care
V53C808H Rev. 1.5 April 1998
8
Undefined
V53C808H
MOSEL VITELIC
Waveforms of OE-Controlled Write Cycle
RAS
t AR (23)
V IH
t CSH (4)
t RCD (6)
t RSH (W)(12)
t CAS (5)
V IH
t CRP (13)
V IL
t RAD (24)
t RAH (9)
t ASR (8)
ADDRESS
t RP (3)
V IL
t CRP (13)
CAS
t RC (2)
t RAS (1)
V IH
ROW ADDRESS
V IL
t CAR (44)
t CAH (11)
t ASC (10)
COLUMN ADDRESS
t CWL (26)
t RWL (31)
t WP (29)
WE
V IH
V IL
t WOH (34)
OE
V IH
V IL
t OED (35)
I/O
t DH (33)
t DS (32)
V IH
VALID DATA-IN
V IL
808H-07
Waveforms of Read-Modify-Write Cycle
RAS
t AR (23)
VIH
t CSH (4)
t RCD (6)
t RP (3)
t RSH (W)(25)
t CRW (40)
VIH
t CRP (13)
VIL
t
t RAH (9)
t ASC (10)
t ASR (8)
ADDRESS
t RWC (36)
VIL
t CRP (13)
CAS
tRRW (37)
VIH
VIL
ROW
ADDRESS
CAH (11)
COLUMN
ADDRESS
t AWD (41)
t CWD (38)
t RAD (24)
t RWL (31)
t RWD (39)
t WP (29)
t RCS (17)
WE
t CWL (26)
VIH
VIL
t CAA (20)
t OAC (17)
OE
VIH
VIL
t OED (35)
t CAC (18)
t RAC (19)
I/O
t HZ (22)
VIH VOH
VALID
DATA-OUT
VIL VOL
t DH (33)
t DS (32)
VALID
DATA-IN
t LZ (21)
808H-08
Don’t Care
V53C808H Rev. 1.5 April 1998
9
Undefined
V53C808H
MOSEL VITELIC
Waveforms of EDO Page Mode Read Cycle
RAS
V IL
t PC (42)
t CP (43)
V IH
t CSH (4)
t RAH (9)
t ASC (10)
ROW
ADDRESS
t CAH (11)
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
t CAH (11)
t RCH (14)
V IH
V IL
t CAA (20)
t CAA (20)
t CAP (45)
t OAC (17)
t RRH (15)
t OAC (17)
V IH
V IL
t RAC (19)
t CAC (18)
t LZ (21)
I/O
t CAR (44)
t ASC (10)
t CAH (11)
t RCS (7)
OE
t CRP (13)
t CAS (5)
t CAS (5)
V IL
V IL
WE
t RSH (R)(12)
t CAS (5)
V IH
t ASR (8)
ADDRESS
RP (3)
t RCD (6)
t CRP (13)
CAS
t
t RAS (1)
t AR (23)
V IH
t CAC (18)
t CAC (18)
t COH
V OH
t HZ (22)
VALID
DATA OUT
V OL
t HZ (22)
t HZ (22)
t HZ (22)
VALID
DATA OUT
VALID
DATA OUT
808H-09
t LZ
Waveforms of EDO Page Mode Write Cycle
t RP (3)
t AR (23)
RAS
t RAS (1)
V IH
V IL
t CRP (13)
t RCD (6)
CAS
t PC (42)
t CP (43)
t CAS (5)
V IH
t RSH (W)(25)
t CAS (5)
t CAS (5)
t CRP (13)
V IL
t CSH (4)
t RAH (9)
t ASC (10)
t ASR (8)
ADDRESS
V IH
ROW
ADD
V IL
t CAH (11)
t CAH (11)
COLUMN
ADDRESS
t RAD (24)
COLUMN
ADDRESS
t CWL (26)
t WCS (27)
t WCH (28)
t CAH (11)
COLUMN
ADDRESS
t CWL (26)
t WCS (27)
t WCS (27)
t CWL (26)
t WCH (28)
t RWL (31)
t WCH (28)
t WP (29)
t WP (29)
t WP (29)
WE
t CAR (44)
t ASC (10)
V IH
V IL
OE
VIH
V IL
t DH (33)
t DS (32)
I/O
V IH
V IL
VALID
DATA IN
t DH (33)
t DS (32)
VALID
DATA IN
OPEN
t DS (32)
t DH (33)
VALID
DATA IN
OPEN
808H-10
Don’t Care
V53C808H Rev. 1.5 April 1998
10
Undefined
V53C808H
MOSEL VITELIC
Waveforms of EDO Page Mode Read-Write Cycle
RAS
t RAS (1)
VIH
V
IL
t CSH (4)
t RCD (6)
t PCM (50)
IH
V
t RSH (W)(25)
t CRP (13)
t CAS (5)
t CP (43)
t CAS (5)
V
CAS
t RP (3)
t CAS (5)
t RAD (24)
IL
t RAH (9)
t ASC (10)
t ASR (8)
V
ADDRESS
IH
IL
t CAH (11)
COLUMN
ADDRESS
COLUMN
ADDRESS
t RWD (39)
t RCS (7)
t CWL (26)
t CWD (38)
t CAR (44)
t ASC (10)
t CAH (11)
ROW
ADD
V
t ASC (10)
t CAH (11)
COLUMN
ADDRESS
t CWD (38)
t CWD (38)
t RWL (31)
t CWL (26)
t CWL (26)
V
WE
IH
V
IL
t CAA (20)
t OAC (17)
t AWD (41)
t AWD (41)
t AWD (41)
t WP (29)
t WP (29)
t WP (29)
t OAC (17)
t OAC (17)
V
OE
IH
V
IL
t CAA (20)
t OED (35)
t CAC (18)
t RAC (19)
t CAP (43)
t CAP (43)
t CAA (20)
t OED (35)
t CAC (18)
t HZ (22)
t HZ (22)
t DH (33)
t DH (33)
t DS (32)
t DS (32)
I/O
V I/OH
OUT
V I/OL
OUT
IN
t OED (35)
t CAC (18)
t HZ (22)
t DH (33)
t DS (32)
OUT
IN
IN
808H-11
t LZ (21)
t LZ
t LZ
Waveforms of RAS-Only Refresh Cycle
t RC (2)
RAS
t RAS (1)
V IH
t RP (3)
V IL
t CRP (13)
CAS
V IH
V IL
t ASR (8)
ADDRESS
V IH
t RAH (9)
ROW ADD
V IL
808H-12
NOTE:
WE, OE = Don’t care
Don’t Care
V53C808H Rev. 1.5 April 1998
11
Undefined
V53C808H
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
t RAS (1)
RAS
t RP (3)
V IH
V IL
t CSR (47)
CAS
t CHR (49)
t RSH (W)(25)
t CAS (5)
t CP (43)
V IH
V IL
ADDRESS
V IH
V IL
READ CYCLE
WE
t RRH (15)
t RCH (14)
t RCS (7)
V IH
V IL
t ROH (16)
t OAC (17)
OE
V IH
V IL
t HZ (22)
t HZ (22)
t LZ (21)
I/O
V IH
DOUT
V IL
t RWL (31)
t CWL (26)
WRITE CYCLE
t WCH (28)
t WCS (27)
WE
t HZ (22)
V IH
V IL
OE
V IH
V IL
t DH (33)
t DS (32)
I/O
V IH
D IN
V IL
808H-13
Waveforms of CAS-before-RAS Refresh Cycle
t RC (2)
t RP (3)
RAS
V IL
t CP (43)
CAS
t RAS (1)
t RP (3)
V IH
t RPC (48)
t CSR (47)
t CHR (49)
V IH
V IL
t HZ (22)
I/O
V OH
V OL
808H-14
NOTE: WE, OE, A 0 –A 9 = Don’t care
Don’t Care
V53C808H Rev. 1.5 April 1998
12
Undefined
V53C808H
MOSEL VITELIC
Waveforms of Hidden Refresh Cycle (Read)
t RC (2)
RAS
V IH
t RC (2)
tRP (3)
t RAS (1)
t AR (23)
t RAS (1)
t RP (3)
V IL
t RCD (6)
t CRP (13)
CAS
t CRP (13)
V IL
V IH
t RAD (24)
t ASC (10)
t CAH (11)
COLUMN
ADDRESS
ROW
ADD
V IL
t RCS (7)
WE
t CHR (49)
V IH
t ASR (8)
t RAH (9)
ADDRESS
t RSH (R)(12)
t RRH (15)
V IH
V IL
t CAA (20)
OE
t HZ (22)
t OAC (17)
V IH
V IL
t CAC (18)
t LZ (21)
t RAC (19)
I/O
t HZ (22)
V OH
t HZ (22)
VALID DATA
V OL
808H-15
Waveforms of Hidden Refresh Cycle (Write)
t RC (2)
RAS
V IH
t RC (2)
t RAS (1)
t RP (3)
V IL
t RCD (6)
t CRP (13)
CAS
t RP (3)
t RAS (1)
t AR (23)
t RSH (12)
t CHR (49)
t CRP (13)
V IH
V IL
t RAD (24)
t ASC (10)
t ASR (8)
t RAH (9)
ADDRESS
V IH
V IL
ROW
ADD
COLUMN
ADDRESS
t WCH (28)
t WCS (27)
WE
t CAH (11)
V IH
V IL
V IH
OE
V IL
t DS (32)
I/O
V IH
V IL
t DH (33)
VALID DATA-IN
t DHR (46)
808H-16
Don’t Care
V53C808H Rev. 1.5 April 1998
13
Undefined
V53C808H
MOSEL VITELIC
Waveforms of Self Refresh Cycle (Optional)
tRP (3)
RAS
VIH
VIL
ADDRESS
I/O
WE
OE
tRPS (57)
tRPC (48)
tRPC (48)
tCP (43)
UCAS, LCAS
tRASS (54)
VIH
tCSR (47)
tCHS (56)
tCHD (57)
VIL
VIH
VIL
VOH
OPEN
VOL
VIH
VIL
VIH
VIL
808H-17
Functional Description
Read Cycle
The V53C808H is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional
dynamic RAM. The V53C808H reads and writes
data by multiplexing an 20-bit address into a 10-bit
row and a 10-bit column address. The row address
is latched by the Row Address Strobe (RAS). The
column address “flows through” an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only
when tOAC, tRAC, tCAA and tCAC are all satisifed. As
a result, the access time is dependent on the timing
relationships between these parameters. For example, the access time is limited by tCAA when tRAC,
tCAC and tOAC are all satisfied.
Write Cycle
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAScontrolled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
the high state and tOED must be satisfied.
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time tRP/tCP has elapsed.
V53C808H Rev. 1.5 April 1998
14
V53C808H
MOSEL VITELIC
Extended Data Output Page Mode
Self Refresh (Optional)
EDO Page operation permits all 1024 columns
within a selected row of the device to be randomly
accessed at a high data rate. Maintaining RAS low
while performing successive CAS cycles retains the
row address internally and eliminates the need to
reapply it for each cycle. The column address buffer
acts as a transparent or flow-through latch while
CAS is high. Thus, access begins from the
occurrence of a valid column address rather than
from the falling edge of CAS, eliminating tASC and tT
from the critical timing path. CAS latches the
address into the column address buffer. During
EDO operation, Read, Write, Read-Modify-Write or
Read-Write-Read cycles are possible at random
addresses within a row. Following the initial entry
cycle into Hyper Page Mode, access is tCAA or tCAP
controlled. If the column address is valid prior to the
rising edge of CAS, the access time is referenced to
the CAS rising edge and is specified by tCAP. If the
column address is valid after the rising CAS edge,
access is timed from the occurrence of a valid
address and is specified by tCAA. In both cases, the
falling edge of CAS latches the address and
enables the output.
EDO provides a sustained data rate of 72 MHz for
applications that require high bandwidth such as bitmapped graphics or high-speed signal processing.
The following equation can be used to calculate the
maximum data rate:
Self Refresh mode provides internal refresh control signals to the DRAM during extended periods of
inactivity. Device operation in this mode provides
additional power savings and design ease by elimination of external refresh control signals. Self Refresh mode is initialed with a CAS before RAS
(CBR) Refresh cycle, holding both RAS low (tRASS)
and CAS low (tCHD) for a specified period. Both of
these parameters are specified with minimum values to guarantee entry into Self Refresh operation.
Once the device has been placed in to Self Refresh
mode the CAS clock is no longer required to maintain Self Refresh operation.
The Self Refresh mode is terminated by returning
the RAS clock to a high level for a specified (tRPS)
minimum time. After termination of the Self Refresh
cycle normal accesses to the device may be initiated immediately, poviding that subsequest refresh
cycles utilize the CAS before RAS (CBR) mode of
operation.
Data Output Operation
The V53C808H Input/Output is controlled by OE,
CAS, WE and RAS. A RAS low transition enables
the transfer of data to and from the selected row
address in the Memory Array. A RAS high transition
disables data transfer and latches the output data if
the output is enabled. After a memory cycle is
initiated with a RAS low transition, a CAS low
transition or CAS low level enables the internal I/O
path. A CAS high transition or a CAS high level
disables the I/O path and the output driver if it is
enabled. A CAS low transition while RAS is high has
no effect on the I/O data path or on the output
drivers. The output drivers, when otherwise
enabled, can be disabled by holding OE high. The
OE signal has no effect on any data stored in the
output latches. A WE low level can also disable the
output drivers when CAS is low. During a Write
cycle, if WE goes low at a time in relationship to
CAS that would normally cause the outputs to be
active, it is necessary to use OE to disable the
output drivers prior to the WE low transition to allow
Data In Setup Time (tDS) to be satisfied.
1024
Data Rate = -------------------------------------------t RC + 1023 ´ t PC
V53C808H Rev. 1.5 April 1998
15
V53C808H
MOSEL VITELIC
Power-On
Table 1. V53C808H Data Output
After application of the VCC supply, an initial
pause of 200 ms is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the VCC current requirement of
the V53C808H is dependent on the input levels of
RAS and CAS. If RAS is low during Power-On, the
device will go into an active cycle and ICC will exhibit
current transients. It is recommended that RAS and
CAS track with VCC or be held at a valid VIH during
Power-On to avoid current surges.
V53C808H Rev. 1.5 April 1998
Operation for Various Cycle Types
16
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS-Controlled Write
Cycle (Early Write)
High-Z
WE-Controlled Write
Cycle (Late Write)
OE Controlled.
High OE = High-Z I/Os
Read-Modify-Write
Cycles
Data from Addressed
Memory Cell
EDO Read Cycle
Data from Addressed
Memory Cell
EDO Write Cycle
(Early Write)
High-Z
EDO Read-ModifyWrite Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS
Refresh Cycle
Data remains as in
previous cycle
CAS-only Cycles
High-Z
V53C808H
MOSEL VITELIC
Package Diagrams
28-Pin Plastic SOJ
Unit in inches [mm]
1
14
+0.007
0.138 –0.006
0.028
+0.102
+0.004
0.711
–0.051
–0.002
3.51
0.043 MAX
[1.09 MAX]
0.004 [0.102]
0.05 bsc
[1.27 bsc]
V53C808H Rev. 1.5 April 1998
0.015/0.020
[0.38/0.51]
0.025 MIN
[.635 MIN]
17
+0.178
–0.154
0.370 ± 0.010
[9.40 ± 0.26]
15
0.400 ± 0.005
[10.16 ± .0.13]
28
0.440 ±0.005
[11.18 ± 0.12]
0.725 ± 0.005
[18.42 ± 0.12]
MOSEL VITELIC
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V53C808H
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© Copyright 1997, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC
4/98
Printed in U.S.A.
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sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
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