THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 features D D D D D D D D Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance up to –55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† 14-Bit Resolution 1, 3, and 8 MSPS Speed Grades Differential Nonlinearity (DNL) ±0.6 LSB Typ † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. D D D D D D D D D Integral Nonlinearity (INL) ±1.5 LSB Typ Internal Reference Differential Inputs Programmable Gain Amplifier µP Compatible Parallel Interface Timing Compatible With TMS320C6000 DSP 3.3-V Single Supply Power-Down Mode Monolithic CMOS Design applications D D D D D xDSL Front Ends Communication Industrial Control Instrumentation Automotive and Selected Military IN+ AVDD AGND AGND AGND AVDD DVDD A0 A1 NC NC CS PHP PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 IN– AVDD VBG CML REF+ REF– AGND AGND DGND OV D13 D12 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 WR OE DGND DGND CLK DVDD DVDD D0 D1 D2 DVDD DGND D6 D5 D4 D3 D11 DVDD DGND D10 D9 D8 D7 DVDD 13 14 15 16 17 18 19 20 21 22 23 24 NC – No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 description The THS1401, THS1403, and THS1408 are 14-bit, 1/3/8 MSPS, single supply analog-to-digital converters with an internal reference, differential inputs, programmable input gain, and an on-chip sample and hold amplifier. Implemented with a CMOS process, the device has outstanding price/performance and power/speed ratios. The THS1401, THS1403, and THS1408 are designed for use with 3.3-V systems, and with a high-speed µP compatible parallel interface, making them the first choice for solutions based on high-performance DSPs like the TI TMS320C6000 series. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING –40°C to 125°C PQFP – PHP THS1401QPHPEP THS1401QE –40°C to 125°C PQFP – PHP THS1403QPHPEP THS1403QE –55°C to 125°C PQFP – PHP THS1408MPHPEP THS1408ME † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. functional block diagram VBG REF+ REF REF– 1.5 V BG IN+ PGA 0..7 dB 14-Bit ADC 14 15 Buffer D[13:0] + OV bit IN– 6 A[1:0] CLK 2 CONTROL LOGIC POST OFFICE BOX 655303 CS WR OE • DALLAS, TEXAS 75265 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 Terminal Functions TERMINAL NAME NO. A[1:0] 40, 41 AGND 7,8, 44, 45, 46 AVDD CLK 2, 43, 47 CML 4 CS 32 37 I/O I DESCRIPTION Address input Analog ground Analog power supply I Clock input Reference midpoint. This pin requires a 0.1-µF capacitor to AGND. I Chip select input. Active low DGND 9, 15, 25, 33, 34 Digital ground DVDD 14, 20, 26, 30, 31, 42 Digital power supply D[13:0] 11, 12, 13, 16, 17, 18, 19, 21, 22, 23, 24, 27, 28, 29 I/O Data inputs/outputs NC 38, 39 IN+ 48 I No connection, do not use. Reserved Positive differential analog input IN– 1 I Negative differential analog input OE 35 I Output enable. Active low OV 10 O Out of range output REF+ 5 O Positive reference output. This pin requires a 0.1-µF capacitor to AGND. REF– 6 O Negative reference output. This pin requires a 0.1-µF capacitor to AGND. VBG 3 I Reference input. This pin requires a 1-µF capacitor to AGND. WR 36 I Write signal. Active low POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, (AVDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V Supply voltage, (DVDD to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V Reference input voltage range, VBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AVDD + 0.3 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AVDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to DVDD + 0.3 V Operating free-air temperature range, TA: Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS Thermal resistance, junction-to-ambient, ΘJA Thermal resistance, junction-to-case, ΘJC † Thermal resistance is modeled data, is not production tested, and is given for informational purposes only. TYP UNIT 28.8 °C/W 0.79 °C/W UNIT recommended operating conditions MIN NOM MAX Supply voltage, AVDD, DVDD 3 3.3 3.6 High level digital input, VIH 2 3.3 V Low level digital input, VIL 0 Load capacitance, CL 5 0.8 15 Clock frequency, fCLK 4 POST OFFICE BOX 655303 V pF THS1401 0.1 1 1 MHz THS1403 0.1 3 3 MHz THS1408 0.1 8 8 MHz Clock duty cycle Operating free free-air air temperature V 45% 50% 55% Q suffix –40 25 125 M suffix –55 25 125 • DALLAS, TEXAS 75265 °C THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 electrical characteristics over recommended operating free-air temperature range, AVDD = DVDD = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 81 90 5 10 mA 270 360 mW Power Supply IDDA IDDD Analog supply current Digital supply current AVDD = 3.6 V DVDD = 3.6 V Power AVDD = DVDD = 3.6 V Power down current mA µA 20 DC Characteristics Resolution DNL 14 Differential nonlinearity THS1401 INL Integral nonlinearity Best fit THS1403 THS1408 Offset error IN+ = IN–, PGA = 0 dB Gain error PGA = 0 dB Bits ±0.6 ±1 ±1.5 ±2.5 ±2 ±3 ±3.5 ±7.5 LSB LSB 0.3 %FSR 1.75 %FSR AC Characteristics ENOB Effective number of bits 11.2 THS1401/3/8 THD Total harmonic distortion THS1403/8 THS1408 THS1401/3/8 SNR Signal-to-noise ratio THS1408 THS1401/3/8 SINAD Signal-to-noise ratio + distortion THS1403/8 THS1403, THS1408 THS1408 –77 –78 fi = 1 MHz fi = 4 MHz Analog input bandwidth 72 • DALLAS, TEXAS 75265 dB dB 71 70 69 70 dB 70 80 71 80 dB 80 140 POST OFFICE BOX 655303 Bits 72 70 fi = 4 MHz fi = 100 kHz THS1401/3/8 Spurious free dynamic range fi = 4 MHz fi = 100 kHz fi = 100 kHz fi = 1 MHz THS1408 SFDR –81 fi = 1 MHz fi = 4 MHz THS1403/8 11.5 fi = 100 kHz fi = 1 MHz MHz 5 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 electrical characteristics over recommended operating free-air temperature range, AVDD = DVDD = 3.3 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP MAX 1.425 1.5 1.575 UNIT Reference Voltage VBG Bandgap voltage, internal mode V Input impedance 40 kΩ Positive reference voltage, REF+ 2.5 V Negative reference voltage, REF– 0.5 V 2 V Reference difference, ∆REF, REF+ – REF– Accuracy, internal reference 5% Temperature coefficient Voltage coefficient 40 ppm/°C 200 ppm/V Analog Inputs Positive analog input, IN+ 0 Negative analog input, IN– 0 Analog input voltage difference ∆Ain = IN+ – IN–, Vref = REF+ – REF– AVDD AVDD –Vref Input impedance Vref 25 PGA range 0 PGA step size V V kΩ 7 1 dB dB ±0.25 PGA gain error V dB Digital Inputs VIH VIL High-level digital input 2 V Low-level digital input 0.8 Input capacitance 5 ±1 Input current V pF µA Digital Outputs VOH VOL High-level digital output Low-level digital output IOH = 50 µA IOL = 50 µA 2.6 V IOZ Output current, high impedance Clock Timing (CS low) td Clock frequency ±10 µA 1 1 MHz THS1403 3 3 MHz THS1408 0.1† 8 8 MHz Output delay time 25 Latency 9.5 † This parameter is not production tested. 6 V 0.1† 0.1† THS1401 fCLK 0.4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns Cycles THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 PARAMETER MEASUREMENT INFORMATION sample timing The THS1401/3/8 core is based on a pipeline architecture with a latency of 9.5 samples. The conversion results appear on the digital output 9.5 clock cycles after the input signal was sampled. S11 S9 S12 S10 Analog Input tw(CLK) tw(CLK) CLK td Data C1 C2 C3 Out Figure 1. Sample Timing The parallel interface of the THS1401/3/8 ADC features 3-state buffers, making it possible to directly connect it to a data bus. The output buffers are enabled by driving the OE input low. Besides the sample results, it is also possible to read back the values of the control register, the PGA register, and the offset register. Which register is read is determined by the address inputs A[1,0]. The ADC results are available at address 0. The timing of the control signals is described in the following sections. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 PARAMETER MEASUREMENT INFORMATION read timing (15-pF load) PARAMETER tsu(OE–ACS) ten Address and chip select setup time tdis th(A) Output disable MIN TYP 4 15 10 Address hold time th(CS) Chip select hold time NOTE: All timing parameters refer to a 50% level. ns ns OE tdis DATA OV th(A) A[1:0] X ADDRESS Figure 2. Read Timing 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns 0 th(CS) D[13:0] ns 1 CS ten UNIT ns Output enable tsu(OE–ACS) MAX X THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 PARAMETER MEASUREMENT INFORMATION write timing (15-pF load) PARAMETER MIN TYP MAX UNIT tsu(WE–CS) tsu(DA) Chip select setup time 4 ns Data and address setup time 29 ns th(DA) th(CS) Data and address hold time 0 ns 0 ns 15 ns Chip select hold time twH(WE) Write pulse duration high NOTE: All timing parameters refer to a 50% level. CS th(CS) WE tsu(WE–CS) D[13:0] tsu(DA) X DATA X th(DA) A X ADDRESS X Figure 3. Write Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 TYPICAL CHARACTERISTICS POWER vs FREQUENCY SUPPLY CURRENT vs TIME 284 90 282 80 I CC – Supply Current – mA Power – mW 280 278 276 274 272 270 70 60 50 40 30 20 10 0 268 0.1 1 f – Frequency – MHz 0 10 50 Figure 4 100 150 200 t – Time – ns 250 Figure 5 FAST FOURIER TRANSFORM 0 fs = 1 MSPS, fI = 100 kHz, –1 dB Output – dB –20 –40 –60 –80 –100 –120 –140 0 100 200 300 f – Frequency – kHz Figure 6 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 400 500 300 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 TYPICAL CHARACTERISTICS FAST FOURIER TRANSFORM 0 fs = 3 MSPS, fI = 1 MHz, –1 dB Output – dB –20 –40 –60 –80 –100 –120 –140 0.1 0.4 0.7 1.3 1 f – Frequency – MHz Figure 7 FAST FOURIER TRANSFORM 0 fs = 8 MSPS, fI = 1 MHz, –1 dB Output – dB –20 –40 –60 –80 –100 –120 –140 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.7 4 f – Frequency – MHz Figure 8 INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY 2 fs = 1 MSPS 1.5 1 0.5 0 –0.5 –1 –1.5 –2 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 TYPICAL CHARACTERISTICS INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY 2 fs = 3 MSPS 1.5 1 0.5 0 –0.5 –1 –1.5 –2 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 10 INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY 4 fs = 8 MSPS 3 2 1 0 –1 –2 –3 –4 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples DNL – Differential Nonlinearity – LSB Figure 11 DIFFERENTIAL NONLINEARITY 1 0.8 fs = 1 MSPS 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 2048 4096 6144 8192 10240 Samples Figure 12 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12288 14336 16384 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 DNL – Differential Nonlinearity – LSB TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY 1 0.8 fs = 3 MSPS 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples DNL – Differential Nonlinearity – LSB Figure 13 DIFFERENTIAL NONLINEARITY 1 0.8 fs = 8 MSPS 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION vs FREQUENCY –70 –72 fs = 3 MSPS, fI at –1 dB THD – Total Harmonic Distortion – dB THD – Total Harmonic Distortion – dB –70 –74 –76 –78 –80 –82 –84 –86 –88 fs = 8 MSPS, fI at –1 dB –72 –74 –76 –78 –80 –82 –84 –86 –88 –90 10 –90 1000 1500 100 f – Frequency – Hz 10 100 Figure 16 SIGNAL-TO-NOISE RATIO vs FREQUENCY SIGNAL-TO-NOISE RATIO vs FREQUENCY 80 78 SNR – Signal-to-Noise Ratio – dB SNR – Signal-to-Noise Ratio – dB 80 fs = 3 MSPS, fI at –1 dB 76 74 72 70 68 66 64 62 60 10 fs = 8 MSPS, fI at –1 dB 76 74 72 70 68 66 64 62 100 1000 1500 60 10 f – Frequency – Hz 100 f – Frequency – Hz Figure 17 14 4000 f – Frequency – Hz Figure 15 78 1000 Figure 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1000 4000 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 PRINCIPLES OF OPERATION registers The device contains several registers. The A register is selected by the values of bits A1 and A0: A1 A0 Register 0 0 Conversion result 0 1 PGA 1 0 Offset 1 1 Control Tables 1 and 2 describe how to read the conversion results and how to configure the data converter. The default values (were applicable) show the state after a power-on reset. Table 1. Conversion Result Register, Address 0, Read BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function MSB ... … … … … … … … … … … … LSB The output can be configured for two’s complement or straight binary format (see D11/control register). The output code is given by: 2s complement: –8192 at ∆IN = –∆REF 0 at ∆IN = 0 8191 ∆IN = –∆REF – 1 LSB 1 LSB Straight binary: 0 at ∆IN = –∆REF 8192 at ∆IN = 0 16383 at ∆IN = –∆REF – 1 LSB DREF + 216384 Table 2. PGA Gain Register, Address 1, Read/Write BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X X X X X X X X X X G2 G1 G0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The PGA gain is determined by writing to G2–0. Gain (dB) = 1dB × G2–0. max = 7dB. The range of G2–0 is 0 to 7. Table 3. Offset Register, Address 2, Read/Write BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X X X X X MSB … … … … … … LSB Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The offset correction range is from –128 to 127 LSB. This value is added to the conversion results from the ADC. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 PRINCIPLES OF OPERATION Table 4. Control Register, Address 3, Read BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function PWD REF FOR TM2 TM1 TM0 OFF RES RES RES RES RES RES RES Table 5. Control Register, Address 3, Write BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function PWD REF FOR TM2 TM1 TM0 OFF RES RES RES RES RES RES RES Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWD: Power down 0 = normal operation 1 = power down REF: Reference select 0 = internal reference 1 = external reference FOR: Output format 0 = straight binary 1 = 2s complement TM2–0: Test mode 000 = normal operation 001 = both inputs = REF– 010 = IN+ at Vref/2, IN– at REF– 011 = IN+ at REF+, IN– at REF– 100 = normal operation 101 = both inputs = REF+ 110 = IN+ at REF–, IN– at Vref/2 111 = IN+ at REF–, IN– at REF+ OF: Offset correction 0 = enable RES Reserved Must be set to 0. 16 POST OFFICE BOX 655303 1 = disable • DALLAS, TEXAS 75265 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 APPLICATION INFORMATION driving the analog input The THS1401/3/8 ADCs have a fully differential input. A differential input is advantageous with respect to SNR, SFDR, and THD performance because the signal peak-to-peak level is 50% of a comparable single-ended input. There are three basic input configurations: D D D Fully differential Transformer coupled single-ended to differential Single-ended fully differential configuration In this configuration, the ADC converts the difference (∆IN) of the two input signals on IN+ and IN–. 22 Ω IN+ 100 pF THS1401/3/8 22 Ω IN– 100 pF Figure 19. Differential Input The resistors and capacitors on the inputs decouple the driving source output from the ADC input and also serve as first order low pass filters to attenuate out of band noise. The input range on both inputs is 0 V to AVDD. The full-scale value is determined by the voltage reference. The positive full-scale output is reached, if ∆IN equals ∆REF, the negative full-scale output is reached, if ∆IN equals –∆REF. ∆IN [V] OUTPUT –∆REF – full scale 0 0 ∆REF + full scale POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 APPLICATION INFORMATION transformer coupled single-ended to differential configuration If the application requires the best SNR, SFDR, and THD performance, the input should be transformer coupled. The signal amplitude on both inputs of the ADC is one half as high as in a single-ended configuration thus increasing the ADC ac performance. 22 Ω IN+ 100 pF R THS1401/3/8 22 Ω IN– 100 pF + CML 1 µF 0.1 µF Figure 20. Transformer Coupled The following table shows the input voltages for negative full-scale output, zero output, and positive full-scale output: IN [VPEAK] –∆REF OUTPUT [PEAK] – full scale† 0 0 ∆REF + full scale† † n = 1 (winding ratio) The resistor R of the transformer coupled input configuration must be set to match the signal source impedance R = n2 Rs, where Rs is the source impedance and n is the transformer winding ratio. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 APPLICATION INFORMATION single-ended configuration In this configuration, the input signal is level shifted by ∆REF/2. 10 kΩ + 10 kΩ 10 kΩ 10 kΩ IN+ 100 pF REF+ THS1401/3/8 – 22 Ω IN– 100 pF + 10 kΩ REF– 10 kΩ Figure 21. Single-Ended With Level Shift The following table shows the input voltages for negative full-scale output, zero output, and positive full-scale output: ∆IN+ [V] OUTPUT –∆REF – full scale 0 0 ∆REF + full scale Note that the resistors of the op-amp and the op-amp all introduce gain and offset errors. Those errors can be trimmed by varying the values of the resistors. Because of the added offset, the op-amp does not necessarily operate in the best region of its transfer curve (best linearity around zero) and therefore may introduce unacceptable distortion. For ac signals, an alternative is described in the following section. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 APPLICATION INFORMATION AC-coupled single-ended configuration If the application does not require the signal bandwidth to include dc, the level shift shown in Figure 4 is not necessary. 10 kΩ 10 kΩ 10 kΩ 10 kΩ IN+ 100 pF REF+ THS1401/3/8 – + 10 nF 22 Ω IN– 100 pF REF– 10 kΩ 10 kΩ Figure 22. Single-Ended With Level Shift Because the signal swing on the op-amp is centered around ground, it is more likely that the signal stays within the linear region of the op-amp transfer function, thus increasing the overall ac performance. IN [VPEAK] OUTPUT [PEAK] –∆REF – full scale 0 0 ∆REF + full scale Compared to the transformer-coupled configuration, the swing on IN– is twice as big, which can decrease the ac performance (SNR, SFD, and THD). 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 APPLICATION INFORMATION internal/external reference operation The THS1401/3/8 ADC can either be operated using the built-in band gap reference or using an external precision reference in case very high dc accuracy is needed. ǒ Ǔ The REF+ and REF+ outputs are given by: REF )+ VBG 1 ) 23 and REF– ǒ Ǔ + VBG 1– 23 If the built-in reference is used, VBG equals 1.5 V which results in REF+ = 2.5 V, REF– = 0.5 V and ∆REF = 2 V. The internal reference can be disabled by writing 1 to D12 (REF) in the control register (address 3). The band gap reference is then disconnected and can be substituted by a voltage on the VBG pin. programmable gain amplifier The on-chip programmable gain amplifier (PGA) has eight gain settings. The gain can be changed by writing to the PGA gain register (address 1). The range is 0 to 7dB in steps of one dB. out of range indication The OV output of the ADC indicates an out of range condition. Every time the difference on the analog inputs exceeds the differential reference, this signal is asserted. This signal is updated the same way as the digital data outputs and therefore subject to the same pipeline delay. offset compensation With the offset register it is possible to automatically compensate system offset errors, including errors caused by additional signal conditioning circuitry. If the offset compensation is enabled (D7 (OFF) in the control register), the value in the offset register (address 2) is automatically subtracted from the output of the ADC. In order to set the correct value of the offset compensation register, the ADC result when the input signal is 0 must be read by the host processor and written to the offset register (address 2). test modes The ADC core operation can be tested by selecting one of the available test modes (see control register description). The test modes apply various voltages to the differential input depending on the setting in the control register. digital I/O The digital inputs and outputs of the THS1401/3/8 ADC are 3-V CMOS compatible. In order to avoid current feed back errors, the capacitive load on the digital outputs should be as low as possible (50 pF max). Series resistors (100 Ω) on the digital outputs can improve the performance by limiting the current during output transitions. The parallel interface of the THS1401/3/8 ADC features 3-state buffers, making it possible to directly connect it to a data bus. The output buffers are enabled by driving the OE input low. Refer to the read and write timing diagrams in the parameter measurement information section for information on read and write access. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 THS1401-EP THS1403-EP THS1408-EP 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA SGLS129A – JULY 2002 – REVISED NOVEMBER 2002 MECHANICAL DATA PHP (S-PQFP-G48) PowerPAD PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 Thermal Pad (see Note D) 48 13 0,13 NOM 1 12 5,50 TYP Gage Plane 7,20 SQ 6,80 9,20 SQ 8,80 0,25 0,15 0,05 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4146927/A 01/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MS-026 PowerPAD is a trademark of Texas Instruments. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty THS1401QPHPEP ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR THS1403QPHPEP ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR THS1408MPHPEP ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR V62/03608-01XE ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR V62/03608-02XE ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR V62/03608-03XE ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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