NEC UPD16326GB-3B4

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16326
32-BIT FLUORESCENT DISPLAY TUBE DRIVER
The µPD16326 is a fluorescent display tube driver using a high breakdown voltage CMOS process. It consists
of 32-bit bidirectional shift registers, a latch circuit, and a high breakdown voltage CMOS driver block. The logic block
operates on a 5 V power supply designed to be connected directly to a microcontroller (CMOS level input). The driver
block has a 130 V and 20 mA high breakdown voltage output, and both the logic block and driver block consist of CMOS,
allowing operation with low power consumption.
FEATURES
• High breakdown voltage CMOS structure
• High breakdown voltage, high current output (130 V, 20 mA)
• 32-bit bidirectional shift registers on chip
• Data control by transfer clock (external) and latch
• High-speed data transfer capability (fmax = 8.0 MHz
MIN)
• Wide operating temperature range (TA = –40 to 85 ˚C)
ORDERING INFORMATION
Part Number
µPD16326GB-3B4
Package
44-pin plastic QFP (4-direction leads)
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Document No. S10948EJ1V0DS00 (1st edition)
Date Published July 1996 P
Printed in Japan
©
1996
µPD16326
BLOCK DIAGRAM
CLK
32-bit bidirectional shift registers
A
B
R/L
STB
32-bit latch
BLK
O2
O1
O32
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
44
43
42
41
40
39
38
37
36
35
34
PIN CONFIGURATION (Top View)
VDD2
1
33
O12
VSS2
2
32
O13
O21
23
O22
22
24
11
O23
10
21
B
VSS2
20
O20
O24
25
O25
9
19
VDD1
18
O19
O26
O18
26
O27
27
8
17
7
R/L
16
VSS1
O28
O17
O29
O16
28
15
29
6
14
5
CLK
O30
STB
O31
O15
13
O14
30
O32
31
4
12
3
VDD2
A
BLK
Remark Be sure to enter the power to VDD1, logic signal, and VDD2, in that order, and turn off the power in the reverse
order.
2
µPD16326
PIN DESCRIPTION
Pin Symbol
Pin Name
Pin Number
Description
STB
Latch strobe input
5
H: Data through L: Data retention
A
RIGHT data input
3
When R/L = H, A: Input B: Output
B
LEFT data input
10
When R/L = L, A: Output B: Input
CLK
Clock input
6
Shift is executed on a fall.
BLK
Blanking input
4
H: O1 to O32: ALL “L”
R/L
Shift control input
8
H: Right shift mode A → O1 ... O32 → B
L: Left shift mode
B → O32 ... O1 → A
O1 to O32
High breakdown voltage output
VDD1
Logic block power supply
9
5 V ±10 %
VDD2
Driver block power supply
1, 12
30 to 125 V
VSS1
Logic ground
5
Connected to system GND
VSS2
Driver ground
2, 11
Connected to system GND
13 - 44
130 V, 20 mA
MAX
TRUTH TABLE 1 (SHIFT REGISTER BLOCK)
Input
Output
Shift Register
R/L
CLK
H
↓
H
H or L
L
↓
L
H or L
A
Input
OutputNote 2
B
OutputNote 1
Execution of right shift
Output
Retained
Input
Execution of left shift
Output
Retained
Notes 1. On a clock fall, the data items of S31 are shifted to S32, and output from B.
2. On a clock fall, the data items of S2 are shifted to S1, and output from A.
TRUTH TABLE 2 (LATCH BLOCK)
STB
Operation
L
Retains Sn data immediately before STB becomes L.
H
Outputs shift register data.
TRUTH TABLE 3 (DRIVER BLOCK)
LnNote
STB
BLK
×
×
H
L (all driver outputs: L)
×
L
L
Outputs Sn data on STB fall.
L
H
L
L
H
H
L
H
Driver output state
Note Ln: Latch output
Remark × = H or L, H = high level, L = Low level
3
µPD16326
ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C, VSS = 0 V)
Item
Symbol
Rating
Unit
Logic block supply voltage
VDD1
–0.5 to +7.0
V
Driver block supply voltage
VDD2
–0.5 to +130
V
Logic block input voltage
VI
–0.5 to VDD1 + 0.5
V
Driver block output current
IO
20
mA
Package allowable power dissipation
PD
800Note
mW
Operating ambient temperature
TA
–40 to +85
˚C
Storage temperature
Tstg
–65 to +150
˚C
Note When TA ≥ 25 °C, load should be alleviated at a rate of –8.0 mW/°C. (Tj = 125 °C
(MAX.))
RECOMMENDED OPERATING RANGE (TA = –40 to +85 ˚C, VSS = 0 V)
Item
Symbol
MIN.
TYP.
MAX.
Unit
Logic block supply voltage
VDD1
4.5
5.0
5.5
V
Driver block supply voltage
VDD2
30
125
V
Input voltage high
VIH
0.7·VDD1
VDD1
V
Input voltage low
VIL
0
0.2·VDD1
V
Driver output current
IOH
–10
mA
IOL
+2.5
mA
ELECTRICAL SPECIFICATIONS (TA = 25 ˚C, VDD1 = 4.5 to 5.5 V, VDD2 = 125 V, VSS = 0 V)
Item
Condition
MIN.
TYP.
MAX.
Unit
0.9·VDD1
VDD1
V
0
0.1·VDD1
V
Output voltage high
VOH1
Logic, IOH = –1.0 mA
Output voltage low
VOL1
Logic, IOL = 1.0 mA
Output voltage high
VOH21
O1 to O40, IOH = –0.5 mA
121
V
VOH22
O1 to O40, IOH = –5.0 mA
115
V
VOL2
O1 to O40, IOL = 0.5 mA
2.5
V
VI = VDD1 or VSS1
±1.0
µA
Output voltage low
4
Symbol
Input leakage current
IIL
Input voltage high
VIH
0.7·VDD1
VDD1
V
Input voltage low
VIL
0
0.2·VDD1
V
Static consumption current
IDD1
Logic, TA = –40 to +85 ˚C
1 000
µA
IDD1
Logic, TA = 25 ˚C
100
µA
IDD2
Driver, TA = –40 to +85 ˚C
1 000
µA
IDD2
Driver, TA = 25 ˚C
100
µA
µPD16326
SWITCHING CHARACTERISTICS (TA = 25 ˚C, VDD1 = 5.0 V, VDD2 = 125 V, VSS = 0 V, logic CL =
15 pF, driver CL = 50 pF, driver RL = 220 kΩ, tr = tf = 10 ns)
Item
Transmission delay time
Symbol
tPHL1
Condition
MIN.
TYP.
CLK ↓→ A/B
tPLH1
tPHL2
BLK ↓→ O1 to O32
tPLH2
MAX.
Unit
110
ns
110
ns
300
ns
300
ns
Fall time
tTHL
O1 to O32
600
ns
Rise time
tTLH
O1 to O32
500
ns
Maximum clock frequency
fmax
With cascading, Duty = 50 %
Input capacitance
8.0
MHz
15
CI
pF
TIMING REQUIREMENTS (TA = – 40 to +85 ˚C, VDD1 = 4.5 to 5.5 V, VSS = 0 V, tr = tf = 10 ns)
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Clock pulse width
PWCLK
40
ns
Strobe pulse width
PWSTB
80
ns
Blank pulse width
PWBLK
1 500
ns
Data setup time
tsetup
15
ns
Data hold time
thold
30
ns
Clock-strobe time
tCLK-STB
CLK ↓→ STB ↑
45
ns
Strobe-clock time
tSTB-CLK
STB ↓→ CLK ↓
45
ns
Strobe-blank time
tSTB-BLK
STB ↑→ BLK ↓
80
ns
5
µPD16326
SWITCHING CHARACTERISTIC WAVEFORM (R/L = H)
1/fmax.
PWCLK (L)
PWCLK (H)
VDD1
CLK
50 %
50 %
50 %
VSS
tsetup
thold
VDD1
A/B
(Input)
50 %
50 %
VSS
tPHL1
tPLH 1
VOH1
B/A
(Output)
50 %
50 %
VOL1
tCLK-STB
PWSTB
tSTB-CLK
VDD1
50 %
STB
50 %
VSS
tSTB-BLK
PWBLK
VDD1
BLK
50 %
50 %
VSS
tPLH2
tTLH
90 %
tPHL2
tTHL
90 %
VOH2
On
10 %
6
10 %
VOL2
µPD16326
PACKAGE DRAWINGS
44 PIN PLASTIC QFP (Unit: mm)
A
B
23
22
33
34
detail of lead end
C
D
S
R
Q
12
11
44
1
F
G
J
H
I
M
K
M
P
N
L
NOTE
Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
13.6±0.4
0.535 +0.017
–0.016
B
10.0±0.2
0.394 +0.008
–0.009
C
10.0±0.2
0.394 +0.008
–0.009
D
13.6±0.4
0.535 +0.017
–0.016
F
1.0
0.039
G
1.0
0.039
H
0.35±0.10
0.014 +0.004
–0.005
I
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P)
K
1.8±0.2
0.071 +0.008
–0.009
L
0.8±0.2
0.031 +0.009
–0.008
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
P
Q
R
S
0.10
2.7
0.1±0.1
5°±5°
3.0 MAX.
0.004
0.106
0.004±0.004
5°±5°
0.119 MAX.
P44GB-80-3B4-3
7
µPD16326
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions recommended below.
For soldering methods and conditions other than those recommended, please contact your NEC sales representative.
SURFACE MOUNT TYPE
For details of recommended soldering conditions, refer to the information document “Semiconductor Device
Mounting Technology Manual” (C10535E).
µPD16326GB-3B4
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235 ˚C, Duration: 30 sec. MAX.
(at 210 ˚C or above), Number of times: Twice, Time limit: None Note
IR35-00-2
VPS
Package peak temperature: 215 ˚C, Duration: 40 sec. MAX.
(at 200 ˚C or above), Number of times: Twice, Time limit: None Note
VP15-00-2
Wave soldering
Solder bath temperature: 260 ˚C MAX., Duration: 10 sec. MAX.,
Number of times: Once, Time limit: NoneNote
WS60-00-1
Pin partial heating
Pin partial temperature: 300 ˚C MAX., Duration: 10 sec. MAX.,
Time limit: NoneNote
Note For the storage period after dry-pack decapsulation, storage conditions are max. 25 ˚C, 65 % RH.
Caution Use of more than one soldering method should be avoided (except in the case of pin partial
heating).
REFERENCES
NEC Semiconductor Device Reliability/Quality Control System (IEI-1212)
Quality Grade on NEC Semiconductor Devices (IEI-1209)
8
µPD16326
[MEMO]
9
µPD16326
[MEMO]
10
µPD16326
[MEMO]
11
µPD16326
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consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
2