DATA SHEET MOS INTEGRATED CIRCUIT µPD16857 MONOLITHIC 6 channel H-BRIDGE DRIVER DESCRIPTION µPD16857 is monolithic 6 channel H-bridge driver employing power MOS FETs in the output stages. The MOS FETs in the output stage lower the saturation voltage and power consumption as compared with conventional drivers using bipolar transistors. In addition, a low-voltage malfunction prevention circuit is also provided that prevents the IC from malfunctioning when the supply voltage drops. A 30-pin plastic shrink SOP package is adopted to help create compact and slim application sets. In the output stage H bridge circuits, two low-ON resistance H-bridge circuits for driving actuators, and another three channels for driving sled motors and tilt control, and another channel for driving loading motor are provided, making the product ideal for applications in DVD-ROM/DVD-RAM. FEATURES • Six H-bridge outputs employing power MOS FETs. • High speed PWM drive corresponding: Operating input frequency 120 kHz (MAX.) • Low voltage malfunction prevention circuit: Operating control block voltage under 2.5 V (TYP.) • Loading into 38-pin shrink SOP (300 mil). ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) Parameter Symbol Condition Rating Unit Control block supply voltage VDD –0.5 to +6.0 V Output block supply voltage VM –0.5 to +13.5 V Input voltage VIN –0.5 to VDD+0.5 V ±1.0 A/ch PT 1.0 W Peak junction temperature TCH(MAX) 150 °C Storage temperature range Tstg –55 to +150 °C Output current Power consumptionNote Note ID(pulse) PW ≤ 5 ms, Duty ≤ 20 % When mounted on a glass epoxy board (10 cm × 10 cm × 1 mm, 15 % copper foil) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S13908EJ1V0DS00 (1st edition) Date Published July 1999 N CP(K) Printed in Japan © 1999 µPD16857 RECOMMENDED OPERATING CONDITIONS Parameter MIN. TYP. MAX. Unit Control block supply voltage VDDNote 3.0 3.3 3.6 V Output block supply voltage VM 10.8 12 13.2 V Output current (pulse) ID(pulse) 0.6 A Operating frequency fIN 120 kHz Operating temperature range TA 75 °C Peak junction temperature TCH(MAX) 125 °C Note Symbol Condition PW < 5 ms, Duty < 10 % –0.6 0 The low-voltage malfunction prevention circuit (UVLO) operates when VDD is 2.1 V TYP. CHARACTERISTICS TA = 25 °C and the other parameters are within their recommended operating ranges as described above unless otherwise specified. The parameters other than changes in delay time are when the current is ON. Parameter Symbol Condition TYP. MAX. Unit VM pin current (OFF state) IM VM = 13.2 V 50 µA VDD pin current IDD VDD = 3.6 V 200 µA High level input current IIH VIN = VDD 0.15 mA Low level input current IIL VIN = 0, IN and SEL pins High level input voltage VIH VDD = 3.3 V, VM = 12 V Low level input voltage VIL IN and SEL pins H-bridge ON resistance (ch1, 3, 5, 6) RONa H-bridge ON resistance (ch2, 4) RONb H-bridge switching current Isa(AVE) H-bridge switching current without load (ch2, 4)Note Note µA –2.0 0.7VDD VDD V –0.3 0.3VDD V 2.5 3.5 Ω 1.5 2.0 Ω 3.0 mA 4.5 mA VDD = 3.3 V, VM = 12 V without load (ch1, 3, 5, 6)Note upper + lower VDD = 3.3 V, VM = 12 V Isb(AVE) 100 kHz switching Average value of the current consumed internally by an H-bridge circuit when the circuit is switched without load. 2 MIN. Data Sheet S13908EJ1V0DS00 µPD16857 CHARACTERISTICS TA = 25 °C and the other parameters are within their recommended operating ranges as described above unless otherwise specified. The parameters other than changes in delay time are when the current is ON. Parameter Symbol Condition (ch1, 3, 5 MIN. TYP. MAX. Unit 200 ns 1A, 1B, 3A, 3B, 5A, 5B output) Rise time tTLHa Rising delay time tPLHa VDD = 3.3 V 350 ns Change in rising delay time ∆tPLHa VM = 12 V 110 ns Fall time tTHLa RL(load) = 20 Ω 200 ns Falling delay time tPHLa 100 kHz switching 350 ns Change in falling delay time ∆tPHLa 130 ns (ch1, 3, 5 1A-1B, 3A-3B, 5A-5B) Rising delay time differential tPLHa(A-B) VDD = 3.3 V, VM = 12 V 50 ns Falling delay time differential tPHLa(A-B) RL = 20 Ω, 100 kHz SW 50 ns 200 ns (ch2, 4 2A, 2B, 4A, 4B output) Rise time tTLHb Rising delay time tPLHb VDD = 3.3 V 350 ns Change in rising delay time ∆tPLHb VM = 12 V 110 ns Fall time tTHLb RL(load) = 10 Ω 200 ns Falling delay time tPHLb 100 kHz switching 350 ns Change in falling delay time ∆tPHLb 130 ns (ch2, 4 2A-2B, 4A-4B) Rising delay time differential tPLHb(A-B) VDD = 3.3 V, VM = 12 V 50 ns Falling delay time differential tPHLb(A-B) RL = 10 Ω, 100 kHz SW 50 ns (ch6 6A, 6A output) Rise time tTLHC VDD = 3.3 V Rising delay time tPLHC VM = 12 V Fall time tTHLC RL(load) = 20 Ω Falling delay time tPHLC 100 kHz switching Data Sheet S13908EJ1V0DS00 100 ns 1.0 100 µs ns 1.0 µs 3 µPD16857 PIN CONNECTION ch1 ch2 ch5 ch6 Pin No. Pin name 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VDD IN1A IN1B IN2A IN2B 1A GND 1B VM 2A GND 2B VM 5A GND 6A VMLD IN5A IN5B Pin function IN3B IN3A IN4B IN4A VM 3B GND 3A VM 4B GND 4A VM 5B GND 6B IN6B IN6A SEL 38 37 36 35 34 33 32 31 30 29 28 2B 26 25 24 23 22 21 20 ch3 ch4 Pin No. Pin name Pin function 1 VDD Control block supply voltage pin (3.3 V input) 20 SEL Output enable pin 2 IN1A ch1 input pin 21 IN6A ch6 input pin 3 IN1B ch1 input pin 22 IN6B ch6 input pin 4 IN2A ch2 input pin 23 6B ch6 output pin 5 IN2B ch2 input pin 24 GND 6 1A ch1 output pin 25 5B ch5 output pin 7 GND Ground pin 26 VM Output block supply voltage pin (12 V input) 8 1B ch1 output pin 27 4A ch4 output pin 9 VM Output block supply voltage pin (12 V input) 28 GND 10 2A ch2 output pin 29 4B ch4 output pin 11 GND Ground pin 30 VM Output block supply voltage pin (12 V input) 12 2B ch2 output pin 31 3A ch3 output pin 13 VM Output block supply voltage pin (12 V input) 32 GND 14 5A ch5 output pin 33 3B ch3 output pin 15 GND Ground pin 34 VM Output block supply voltage pin (12 V input) 16 6A ch6 output pin 35 IN4A ch4 input pin 17 VMLD Output block supply voltage pin (12 V input) 36 IN4B ch4 input pin 18 IN5A ch5 input pin 37 IN3A ch3 input pin 19 IN5A ch5 input pin 38 IN3B ch3 input pin Data Sheet S13908EJ1V0DS00 Ground pin Ground pin Ground pin µPD16857 BLOCK DIAGRAM 4 5 6 7 8 9 10 11 12 13 14 15 IN1B IN1A VDD IN3B IN3A IN4B 3 2 1 38 37 36 IN2A ch2 Control ch1 Control level shift level shift LVP ch3 Control ch4 Control level shift level shift IN4A IN2B VM 1A Predriver 3B Predriver H Bridge (ch3) H Bridge (ch1) GND Predriver 1B GND Predriver 3A VM VM 2A 4B Predriver H Bridge (ch2) GND 2B Predriver Predriver H Bridge (ch4) GND 4A Predriver VM VM 5A Predriver H Bridge (ch5) Predriver 5B H Bridge (ch5) GND GND 6A H Bridge (ch6) ch5 Control 16 Predriver level shift 17 18 19 VMLD IN5A IN5B SEL 34 33 32 31 30 29 28 27 26 25 24 6B H Bridge (ch6) Predriver 35 level shift ch6 Control 20 21 22 SEL IN6A IN6B 23 Remark Plural terminal (VM, VMLD, GND) is not only 1 terminal and connect all terminals. Data Sheet S13908EJ1V0DS00 5 µPD16857 FUNCTION TABLE VM, VMLD VDD (COMMON) IN1A - IN6A 1A - 6A(OUTA) IN1B - IN6B 1B - 6B(OUTB) SEL GND (COMMON) PGND INPUT IN1A - IN6A IN1A - IN6A SEL 1A - 6A 1B - 6B L L H L L L H H L H H L H H L H H H H H X X L Z Z X: Don’t care 6 OUTPUT Z: High impedance Data Sheet S13908EJ1V0DS00 µPD16857 TYPICAL CHARACTERISTICS PT vs. TA characteristics IDD vs. VDD characteristics 50 40 1.0 VDD pin current IDD ( µ A) Total power dissipation PT (W) TA=25°C VM=12V 125°C/W 0.5 30 20 10 0 25 50 75 100 125 0 150 3.0 VIH vs. VIL-VDD characteristics RON vs. VM characteristics 3.0 3.0 H-bridge ON resistance RONa, RONb (Ω) TA=25°C VM=12V High level input voltage VIH (V) Low level input voltage VIL (V) 3.6 Control block supply voltage VDD (V) Ambient temperature TA (°C) VIH , VIL 1.5 1.0 TA=25°C VDD=3.3V RONa(ch6) RONa(ch1. 3. 5) 2.0 RONb(ch2. 4) 1.0 3.0 3.3 3.6 10 Isa, Isb. vs. VDD characteristics 13 14 IDD vs. TA characteristics VDD=3.6V 80 VDD pin current IDD ( µ A) Isb(ch2. 4) 2.0 Isa(ch1. 3. 5) 1.0 12 100 TA=25°C VM : 10.8V 12V 13.2V VDD : 3.0V 3.3V 3.6V 3.0 11 Output block supply voltage VM (V) Control block supply voltage VDD (V) Switching current without load Isa, Isb (mA) 3.3 60 40 20 Isa(ch6) 0 10 11 12 13 14 0 Output block supply voltage VM (V) Data Sheet S13908EJ1V0DS00 20 40 60 80 Ambient temperature TA (°C) 7 µPD16857 RON vs. TA characteristics tTLHa, tTLHb, tTLHc, vs. TA characteristics 250 VDD=3.3V VM=12V RONa(ch6) 2.5 Rise time tTLHa, tTLHb, tTLHc (ns) H-bridge ON resistance RONa, RONb (Ω) VM=12V 3.0 RONa(ch1. 3. 5) 2.0 1.5 RONb(ch2. 4) 200 tTLHc 150 tTLHb 100 tTLHa 50 1.0 0 20 40 60 0 80 20 40 60 Ambient temperature TA (°C) Ambient temperature TA (°C) tTHLa, tTHLb, tTHLc vs. TA characteristics tPLHa, tPLHb, tPLHc, vs. TA characteristics 80 250 Rising delay time tPLHa, tPLHb, tPLHc (ns) Fall time tTHLa, tTHLb, tTHLc (ns) VDD=3.3V VM=12V 200 150 tTHLa tTHLb 100 tTHLc 50 0 20 40 60 500 tPLHc 400 300 tPLHb tPLHa 200 80 0 Ambient temperature TA (°C) tPLHa, tPHLa, tPHLb, tPHLc vs. TA characteristics 60 80 tPLHb, vs. TA characteristics tPLHb (ns) 300 tPHLa tPHLb VDD=3.3V VM=12V 80 tPLHa, VDD=3.3V VM=12V tPLHb 60 250 tPHLc 200 150 0 20 40 60 80 Change in rising delay time Falling delay time tPHLa, tPHLb, tPHLc (ns) 40 100 tPLHa 40 20 0 Ambient temperature TA (°C) 8 20 Ambient temperature TA (°C) 350 100 VDD=3.3V VM=12V 600 20 40 60 Ambient temperature TA (°C) Data Sheet S13908EJ1V0DS00 80 µPD16857 tPLHa(A−B), tPLHb(A−B), vs. TA characteristics VDD=3.3V VM=12V 100 Change in falling delay time 80 tPHLa tPHLb 60 40 20 0 20 40 60 80 Rising delay time differential tPLHa(A−B), tPLHb(A−B) (ns) tPHLc, vs. TA characteristics tPHLa, tPHLb (ns) tPHLa, 120 25 VDD=3.3V VM=12V 20 15 10 5 tPLHb(A−B) tPLHa(A−B) 0 Ambient temperature TA (°C) 20 40 60 80 Ambient temperature TA (°C) Falling delay time differential tPHLa(A−B), tPHLb(A−B) (ns) tPHLa(A−B), tPHLb(A−B), vs. TA characteristics 25 VDD=3.3V VM=12V 20 15 10 5 tPHLa(A−B) tPHLb(A−B) 0 20 40 60 80 Ambient temperature TA (°C) Data Sheet S13908EJ1V0DS00 9 µPD16857 ABOUT SWITCHING OPERATION VM When output A is switched as shown in the figure on the right, a dead time (time during which both Pch and Nch are off) elapses to prevent Pch through current. Therefore, the waveform of output A (rise time, fall time, Pch and delay time) changes depending on whether output B is fixed to the high or low level. A B The output voltage waveforms of A in response to an input waveform where output B is fixed to the low level (1) or high level (2) are shown below. Nch Nch (1) Output B: Fixed to low level Output A: Switching operation (Operations of Pch switch and Nch switch are shown.) Dead time Input waveform Pch : OFF → OFF → ON → Nch : ON → OFF → OFF → ⋅ ⋅ ⋅ ⋅ ON ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ OFF ⋅ ⋅ ⋅ ⋅ Voltage waveform at point A Current ON OFF → OFF → OFF → ON → Current OFF Output A goes into high-impedance state and is in an undefined status during the dead time period. But, because output B is pulled down by the load, a low level is output to A. (2) Output B: Fixed to high level Output A: Switching operation (Operations of Pch switch and Nch switch are shown.) Dead time Input waveform Pch : OFF → OFF → ON → Nch : ON → OFF → OFF → ⋅ ⋅ ⋅ ⋅ ON ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ OFF ⋅ ⋅ ⋅ ⋅ Voltage waveform at point A Current OFF OFF → OFF → OFF → ON → Current ON Output A goes into high-impedance state and is in an undefined status during the dead time period. But, because output B is pulled up by the load, a high level is output to A. 10 Data Sheet S13908EJ1V0DS00 µPD16857 The switching characteristics shown on the preceding pages are specified as follow (“output at one side” means output B for H-bridge output A, or output A for output B). [Rise time] Rise time when the output at one side is fixed to the low level (specified on current ON). [Fall time] Fall time when the output at one side is fixed to the high level (specified on current ON). [Rising delay time] Rising delay time when the output at one side is fixed to the low level (specified on current ON). [Falling delay time] Falling delay time when the output at one side is fixed to the high level (specified on current ON). [Change in rising delay time] Change (difference) in the rising delay time between when the output at one side is fixed to the low level and when the output at the other side is fixed to the high level. [Change in falling delay time] Change (difference) in the falling delay time between when the output at one side is fixed to the low level and when the output at the other side is fixed to the high level. [Rising delay time differential] Difference in rising delay time between output A and output B. [Falling delay time differential] Difference in falling delay time between output A and output B. Caution Because this LSI switches a high current at high speeds, surge may occur due to the VM and GND wiring and inductance and degrade the performance of the LSI. On the PWB, keep the pattern width of the VM and GND lines as wide and short as possible, and insert the bypass capacitors between VM and GND at location as close to the LSI as possible. Connect a low inductance magnetic capacitor (4700 pF or more) and an electrolytic capacitor of 10 µF or so, depending on the load current, in parallel. Data Sheet S13908EJ1V0DS00 11 µPD16857 PACKAGE DIMENSION 38-PIN PLASTIC SSOP (300 mil) 38 20 detail of lead end F G 1 P 19 A L E H I S C N S B K D M M NOTE ITEM Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 12.7±0.3 B 0.65 MAX. C 0.65 (T.P.) D 0.37+0.05 −0.1 E 0.125±0.075 F 1.675±0.125 G H 1.55 7.7±0.2 I J 5.6±0.2 1.05±0.2 K 0.2 +0.1 −0.05 L 0.6±0.2 M 0.10 N 0.10 P 3°+7° −3° P38GS-65-BGG 12 Data Sheet S13908EJ1V0DS00 J µPD16857 RECOMMENDED SOLDERING CONDITIONS Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, consult NEC. Soldering Method Soldering Conditions Recommended Condition symbol Infrared reflow Package peak temperature: 235 °C; Time: 30 secs. max. (210 °C min.); Number of times: 3 times max.; Number of day: none; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2 Wt% max.) is recommended IR35-00-3 VPS Package peak temperature: 215 °C; Time: 40 secs. max. (200 °C min.); Number of times: 3 times max.; Number of day: none; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2 Wt% max.) is recommended. VP15-00-3 Wave soldering Package peak temperature: 260 °C; Time: 10 secs. max.; Number of times: once; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2 Wt% max.) is recommended. WS60-00-1 Caution Do not use two or more soldering methods in combination. Data Sheet S13908EJ1V0DS00 13 µPD16857 [MEMO] 14 Data Sheet S13908EJ1V0DS00 µPD16857 [MEMO] Data Sheet S13908EJ1V0DS00 15 µPD16857 • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98.8