DATA SHEET MOS INTEGRATED CIRCUIT µPD442000A-X 2M-BIT CMOS STATIC RAM 256K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION Description The µPD442000A-X is a high speed, low power, 2,097,152 bits (262,144 words by 8 bits) CMOS static RAM. The µPD442000A-X has two chip enable pins (/CE1, CE2) to extend the capacity. And battery backup is available. The µPD442000A-X is packed in 32-pin PLASTIC TSOP (I) (Normal bent) and 32-pin PLASTIC TSOP (I) (Reverse bent). Features • 262,144 words by 8 bits organization • Fast access time : 55, 70, 85, 100, 120 ns (MAX.) • Low voltage operation : VCC = 2.7 to 3.6 V (-BB55X, -BB70X, -BB85X) VCC = 2.2 to 3.6 V (-BC70X, -BC85X, -BC10X) VCC = 1.8 to 2.2 V (-DD85X, -DD10X, -DD12X) • Low VCC data retention : 1.0 V (MIN.) • Operating ambient temperature : TA = –25 to +85 °C • Output Enable input for easy application • Two Chip Enable inputs : /CE1, CE2 µPD442000A Access time Operating supply Operating ambient ns (MAX.) Supply current voltage temperature At operating At standby At data retention V °C mA (MAX.) µA (MAX.) µA (MAX.) −25 to +85 2 1 30 Note -BB55X, -BB70X, -BB85X 55, 70, 85 2.7 to 3.6 -BC70X, -BC85X, -BC10X 70, 85, 100 2.2 to 3.6 30 -DD85X, -DD10X, -DD12X 85, 100, 120 1.8 to 2.2 15 1.5 Note Cycle time ≥ 70 ns, -BB55X : 35 mA The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M14669EJ7V0DS00 (7th edition) Date Published October 2002 NS CP (K) Printed in Japan The mark ★ shows major revised points. © 2000 µPD442000A-X Ordering Information Part number Package Access time Operating Operating ns (MAX.) supply voltage temperature V °C 2.7 to 3.6 −25 to +85 µPD442000AGU-BB55X-9JH 32-pin PLASTIC TSOP (I) 55 µPD442000AGU-BB70X-9JH (8×13.4) (Normal bent) 70 µPD442000AGU-BB85X-9JH 85 µPD442000AGU-BC70X-9JH 70 µPD442000AGU-BC85X-9JH 85 µPD442000AGU-BC10X-9JH 100 µPD442000AGU-DD85X-9JH 85 µPD442000AGU-DD10X-9JH 100 µPD442000AGU-DD12X-9JH 120 µPD442000AGU-BB55X-9KH 32-pin PLASTIC TSOP (I) 55 µPD442000AGU-BB70X-9KH (8×13.4) (Reverse bent) 70 µPD442000AGU-BB85X-9KH 85 µPD442000AGU-BC70X-9KH 70 µPD442000AGU-BC85X-9KH 85 µPD442000AGU-BC10X-9KH 100 µPD442000AGU-DD85X-9KH 85 µPD442000AGU-DD10X-9KH 100 µPD442000AGU-DD12X-9KH 120 2 Data Sheet M14669EJ7V0DS 2.2 to 3.6 1.8 to 2.2 2.7 to 3.6 2.2 to 3.6 1.8 to 2.2 µPD442000A-X Pin Configurations /xxx indicates active low signal. 32-pin PLASTIC TSOP (I) (8× ×13.4) (Normal bent) [ µPD442000AGU-9JH ] Marking Side A11 A9 A8 A13 /WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A0 to A17 /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 : Address inputs I/O1 to I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M14669EJ7V0DS 3 µPD442000A-X 32-pin PLASTIC TSOP (I) (8× ×13.4) (Reverse bent) [ µPD442000AGU-9KH ] Marking Side /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A0 to A17 : Address inputs I/O1 to I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground Remark Refer to Package Drawings for the 1-pin index mark. 4 Data Sheet M14669EJ7V0DS A11 A9 A8 A13 /WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 µPD442000A-X Block Diagram VCC GND A0 Address buffer A17 I/O1 Row decoder Input data controller I/O8 Memory cell array 2,097,152 bits Sense amplifier / Switching circuit Column decoder Output data controller Address buffer /CE1 CE2 /OE /WE Truth Table /CE1 CE2 /OE /WE Mode I/O Supply current H × × × Not selected High-Z ISB × L × × Not selected High-Z L H H H Output disable High-Z L H L H Read DOUT L H × L Write DIN ICCA Remark × : VIH or VIL Data Sheet M14669EJ7V0DS 5 µPD442000A-X Electrical Specifications Absolute Maximum Ratings Parameter Symbol Condition Rating -BB55X, -BB70X, -BB85X Unit -DD85X, -DD10X, -DD12X -BC70X, -BC85X, -BC10X Supply voltage –0.5 Note to +4.0 VCC –0.5 Note to VCC+0.4 (4.0 V MAX.) –0.5 Note –0.5 Note to +2.7 V to VCC+0.4 (2.7 V MAX.) V Input / Output voltage VT Operating ambient temperature TA –25 to +85 –25 to +85 °C Storage temperature Tstg –55 to +125 –55 to +125 °C Note –3.0 V (MIN.) (Pulse width : 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Supply voltage VCC High level input voltage VIH Low level input voltage VIL Operating ambient TA Condition -BB55X,-BB70X,-BB85X -BC70X,-BC85X,-BC10X -DD85X,-DD10X,-DD12X Unit MIN. MAX. MIN. MAX. MIN. MAX. 2.7 3.6 2.2 3.6 1.8 2.2 V 2.7 V ≤ VCC ≤ 3.6 V 2.4 VCC+0.4 2.4 VCC+0.4 – – V 2.2 V ≤ VCC < 2.7 V – – 2.0 VCC+0.3 – – 1.8 V ≤ VCC < 2.2 V – – – – 1.6 –0.3 Note –25 +0.5 +85 –0.3 Note –25 +0.4 –0.2 +85 Note –25 VCC+0.2 +0.2 V +85 °C temperature Note –1.0 V (MIN.) (Pulse width : 20 ns) Capacitance (TA = 25 °C, f = 1 MHz) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input capacitance CIN VIN = 0 V 8 pF Input / Output capacitance CI/O VI/O = 0 V 10 pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are not 100% tested. 6 Data Sheet M14669EJ7V0DS µPD442000A-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2) Parameter Symbol Test condition -BB55X, -BB70X, -BB85X MIN. TYP. Unit MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /CE1 = VIH or –1.0 +1.0 µA mA CE2 = VIL or /WE = VIL or /OE = VIH Operating supply current ICCA1 /CE1 = VIL, CE2 = VIH, Cycle time = 55 ns – 35 Minimum cycle time, Cycle time ≥ 70 ns – 30 – 4 – 4 – 0.35 mA µA II/O = 0 mA ICCA2 /CE1 = VIL, CE2 = VIH, Cycle time = ∞, II/O = 0 mA ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle time = 1 µs, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V Standby supply current ISB /CE1 = VIH or CE2 = VIL ISB1 /CE1 ≥ VCC – 0.2 V, CE2 ≥ VCC – 0.2 V 0.1 2 ISB2 CE2 ≤ 0.2 V 0.1 2 High level output voltage VOH IOH = –0.5 mA Low level output voltage VOL IOL = 1.0 mA 2.4 V 0.4 V Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of product classification. Data Sheet M14669EJ7V0DS 7 µPD442000A-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2) Parameter Symbol Test condition -BC70X, -BC85X, -BC10X -DD85X, -DD10X, -DD12X MIN. TYP. MAX. MIN. TYP. Unit MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /CE1 = VIH or –1.0 +1.0 –1.0 +1.0 µA mA CE2 = VIL or /WE = VIL or /OE = VIH Operating supply current ICCA1 ICCA2 ICCA3 /CE1 = VIL, CE2 = VIH, – 30 – – Minimum cycle time, VCC ≤ 2.7 V – 25 – – II/O = 0 mA VCC ≤ 2.2 V – – – 15 – 4 – – /CE1 = VIL, CE2 = VIH, Cycle time = ∞, VCC ≤ 2.7 V – 2 – – II/O = 0 mA VCC ≤ 2.2 V – – – 1 – 4 – – /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle time = 1 µs, II/O = 0 mA, Standby supply current ISB ISB1 VIL ≤ 0.2 V, VCC ≤ 2.7 V – 3 – – VIH ≥ VCC – 0.2 V VCC ≤ 2.2 V – – – 3 – 0.35 – – VCC ≤ 2.7 V – 0.35 – – VCC ≤ 2.2 V – – – 0.35 0.1 2 – – VCC ≤ 2.7 V 0.08 2 – – VCC ≤ 2.2 V – – 0.05 1.5 0.1 2 – – VCC ≤ 2.7 V 0.08 2 – – VCC ≤ 2.2 V – – 0.05 1.5 /CE1 = VIH or CE2 = VIL /CE1 ≥ VCC – 0.2 V, CE2 ≥ VCC – 0.2 V ISB2 High level output voltage Low level output voltage VOH VOL CE2 ≤ 0.2 V IOH = –0.5 mA 2.4 – VCC ≤ 2.7 V 1.8 – VCC ≤ 2.2 V – 1.5 IOL = 1.0 mA – VCC ≤ 2.7 V 0.4 – VCC ≤ 2.2 V – 0.4 VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of product classification. 8 Data Sheet M14669EJ7V0DS µA V 0.4 Remarks 1. VIN : Input voltage mA V µPD442000A-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions Input Waveform (Rise and Fall Time ≤ 5 ns) 0.9 VCC VCC/2 Test points VCC/2 VCC/2 Test points VCC/2 0.1 VCC Output Waveform Output Load [ -BB55X, -BB70X, -BB85X ] 1TTL + 50 pF [ -BC70X, -BC85X, -BC10X, -DD85X, -DD10X, -DD12X ] 1TTL + 30 pF Data Sheet M14669EJ7V0DS 9 µPD442000A-X Read Cycle (1/3) Parameter VCC ≥ 2.7 V Symbol -BB55X MIN. MAX. 55 Unit -BB70X MIN. MAX. 70 Condition -BB85X MIN. MAX. Read cycle time tRC 85 ns Address access time tAA 55 70 85 ns /CE1 access time tCO1 55 70 85 ns CE2 access time tCO2 55 70 85 ns /OE to output valid tOE 30 35 40 ns Output hold from address change tOH 10 10 10 ns /CE1 to output in Low-Z tLZ1 10 10 10 ns CE2 to output in Low-Z tLZ2 10 10 10 ns /OE to output in Low-Z tOLZ 5 5 5 ns /CE1 to output in High-Z tHZ1 20 25 30 ns CE2 to output in High-Z tHZ2 20 25 30 ns /OE to output in High-Z tOHZ 20 25 30 ns Note 1 Note 2 Notes 1. The output load is 1TTL + 50 pF. 2. The output load is 1TTL + 5 pF. Read Cycle (2/3) Parameter VCC ≥ 2.2 V Symbol -BC70X MIN. MAX. 70 Unit -BC85X MIN. MAX. 85 -BC10X MIN. MAX. Read cycle time tRC Address access time tAA 70 85 100 ns /CE1 access time tCO1 70 85 100 ns CE2 access time tCO2 70 85 100 ns /OE to output valid tOE 35 40 50 ns Output hold from address change tOH 10 10 10 ns /CE1 to output in Low-Z tLZ1 10 10 10 ns CE2 to output in Low-Z tLZ2 10 10 10 ns /OE to output in Low-Z tOLZ 5 5 5 ns /CE1 to output in High-Z tHZ1 25 30 35 ns CE2 to output in High-Z tHZ2 25 30 35 ns /OE to output in High-Z tOHZ 25 30 35 ns Notes 1. The output load is 1TTL + 30 pF. 2. The output load is 1TTL + 5 pF. 10 Data Sheet M14669EJ7V0DS Condition 100 ns Note 1 Note 2 µPD442000A-X Read Cycle (3/3) Parameter VCC ≥ 1.8 V Symbol -DD85X MIN. MAX. 85 Unit -DD10X MIN. MAX. 100 Condition -DD12X MIN. MAX. Read cycle time tRC 120 ns Address access time tAA 85 100 120 ns /CE1 access time tCO1 85 100 120 ns CE2 access time tCO2 85 100 120 ns /OE to output valid tOE 40 50 60 ns Output hold from address change tOH 10 10 10 ns /CE1 to output in Low-Z tLZ1 10 10 10 ns CE2 to output in Low-Z tLZ2 10 10 10 ns /OE to output in Low-Z tOLZ 5 5 5 ns /CE1 to output in High-Z tHZ1 30 35 40 ns CE2 to output in High-Z tHZ2 30 35 40 ns /OE to output in High-Z tOHZ 30 35 40 ns Note 1 Note 2 Notes 1. The output load is 1TTL + 30 pF. 2. The output load is 1TTL + 5 pF. Data Sheet M14669EJ7V0DS 11 µPD442000A-X Read Cycle Timing Chart tRC Address (Input) tAA tOH /CE1 (Input) tHZ1 tCO1 tLZ1 CE2 (Input) tCO2 tHZ2 tLZ2 /OE (Input) tOE tOHZ tOLZ I/O (Output) High-Z Remark In read cycle, /WE should be fixed to high level. 12 Data Sheet M14669EJ7V0DS Data out µPD442000A-X Write Cycle (1/3) Parameter VCC ≥ 2.7 V Symbol -BB55X MIN. MAX. Unit -BB70X MIN. MAX. -BB85X MIN. MAX. Write cycle time tWC 55 70 85 ns /CE1 to end of write tCW1 50 55 70 ns CE2 to end of write tCW2 50 55 70 ns Address valid to end of write tAW 50 55 70 ns Address setup time tAS 0 0 0 ns Write pulse width tWP 45 50 55 ns Write recovery time tWR 0 0 0 ns Data valid to end of write tDW 25 30 35 ns Data hold time tDH 0 0 0 ns /WE to output in High-Z tWHZ Output active from end of write tOW 20 5 25 5 Condition 30 5 ns Note ns Note The output load is 1TTL + 5 pF. Write Cycle (2/3) Parameter VCC ≥ 2.2 V Symbol -BC70X MIN. MAX. Unit -BC85X MIN. MAX. -BC10X MIN. MAX. Write cycle time tWC 70 85 100 ns /CE1 to end of write tCW1 55 70 80 ns CE2 to end of write tCW2 55 70 80 ns Address valid to end of write tAW 55 70 80 ns Address setup time tAS 0 0 0 ns Write pulse width tWP 50 55 60 ns Write recovery time tWR 0 0 0 ns Data valid to end of write tDW 30 35 40 ns Data hold time tDH 0 0 0 ns /WE to output in High-Z tWHZ Output active from end of write tOW 25 5 30 5 Condition 35 5 ns Note ns Note The output load is 1TTL + 5 pF. Data Sheet M14669EJ7V0DS 13 µPD442000A-X Write Cycle (3/3) Parameter VCC ≥ 1.8 V Symbol -DD85X MIN. MAX. Unit -DD10X MIN. MAX. -DD12X MIN. MAX. Write cycle time tWC 85 100 120 ns /CE1 to end of write tCW1 70 80 100 ns CE2 to end of write tCW2 70 80 100 ns Address valid to end of write tAW 70 80 100 ns Address setup time tAS 0 0 0 ns Write pulse width tWP 55 60 85 ns Write recovery time tWR 0 0 0 ns Data valid to end of write tDW 35 40 60 ns Data hold time tDH 0 0 0 ns /WE to output in High-Z tWHZ Output active from end of write tOW 30 5 35 5 Note The output load is 1TTL + 5 pF. 14 Data Sheet M14669EJ7V0DS Condition 40 5 ns ns Note µPD442000A-X Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tAS tWP tWR /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out tDW High-Z tDH Data in High-Z Indefinite data out Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. Data Sheet M14669EJ7V0DS 15 µPD442000A-X Write Cycle Timing Chart 2 (/CE1 Controlled) tWC Address (Input) tAS tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tDW High-Z Data in I/O (Input) tDH High-Z Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2. 16 Data Sheet M14669EJ7V0DS µPD442000A-X Write Cycle Timing Chart 3 (CE2 Controlled) tWC Address (Input) tCW1 /CE1 (Input) tAS tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tDW High-Z Data in I/O (Input) tDH High-Z Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2. Data Sheet M14669EJ7V0DS 17 µPD442000A-X Low VCC Data Retention Characteristics (TA = –25 to +85 °C) Parameter Symbol Test Condition -BB55X, -BB70X, -BB85X -BC70X,-BC85X, -BC10X -DD85X,-DD10X, -DD12X Unit MIN. Data retention VCCDR1 /CE1 ≥ VCC − 0.2 V, VCCDR2 CE2 ≤ 0.2 V TYP. MAX. MIN. TYP. MAX. 1.0 3.6 1.0 3.6 1.0 2.2 1.0 3.6 1.0 3.6 1.0 2.2 ICCDR1 VCC = 1.2 V, /CE1 ≥ VCC − 0.2 V, V 0.05 1 0.05 1 0.05 1 0.05 1 0.05 1 0.05 1 µA CE2 ≥ VCC − 0.2 V supply current ICCDR2 VCC = 1.2 V, CE2 ≤ 0.2 V Chip deselection MIN. CE2 ≥ VCC − 0.2 V supply voltage Data retention TYP. MAX. tCDR 0 0 0 ns tR tRCNote tRCNote tRCNote ns to data retention mode Operation recovery time Note tRC : Read cycle time 18 Data Sheet M14669EJ7V0DS µPD442000A-X Data Retention Timing Chart (1) /CE1 Controlled tCDR Data retention mode tR VCC VCC (MIN.) Note /CE1 VIH (MIN.) VCCDR (MIN.) /CE1 ≥ VCC – 0.2 V VIL (MAX.) GND Note 2.7 V (-BB55X, -BB70X, -BB85X), 2.2 V (-BC70X, -BC85X, -BC10X), 1.8 V (-DD85X, -DD10X, -DD12X) Remark On the data retention mode by controlling /CE1, the input level of CE2 must be ≥ VCC − 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state. (2) CE2 Controlled tCDR Data retention mode tR VCC Note VCC (MIN.) VIH (MIN.) VCCDR (MIN.) CE2 VIL (MAX.) CE2 ≤ 0.2 V GND Note 2.7 V (-BB55X, -BB70X, -BB85X), 2.2 V (-BC70X, -BC85X, -BC10X), 1.8 V (-DD85X, -DD10X, -DD12X) Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE) can be in high impedance state. Data Sheet M14669EJ7V0DS 19 µPD442000A-X Package Drawings 32-PIN PLASTIC TSOP(I) (8x13.4) detail of lead end 1 32 S T R L 16 17 U Q P I J A G S H K B C N S NOTES D M M ITEM 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) A MILLIMETERS 8.0±0.1 B 0.45 MAX. C D 0.5 (T.P.) 0.22±0.05 G 1.0±0.05 H 12.4±0.2 I 11.8±0.1 J 0.8±0.2 K 0.145 +0.025 −0.015 L M 0.5 0.08 N 0.08 P 13.4±0.2 Q 0.1±0.05 R 3° +5° −3° S 1.2 MAX. T 0.25 U 0.6±0.15 P32GU-50-9JH-2 20 Data Sheet M14669EJ7V0DS µPD442000A-X 32-PIN PLASTIC TSOP(I) (8x13.4) detail of lead end 1 32 U Q L R T 16 17 N K S D S M M C H B S G I J A P NOTES ITEM 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) A MILLIMETERS 8.0±0.1 B 0.45 MAX. C 0.5 (T.P.) D 0.22±0.05 G 1.0±0.05 H 12.4±0.2 I 11.8±0.1 J 0.8±0.2 K 0.145 +0.025 −0.015 L 0.5 M 0.08 N 0.08 P 13.4±0.2 Q 0.1±0.05 R 3° +5° −3° S 1.2 MAX. T 0.25 U 0.6±0.15 P32GU-50-9KH-2 Data Sheet M14669EJ7V0DS 21 µPD442000A-X Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD442000A-X. Types of Surface Mount Device µPD442000AGU-9JH : 32-pin PLASTIC TSOP (I) (8×13.4) (Normal bent) µPD442000AGU-9KH : 32-pin PLASTIC TSOP (I) (8×13.4) (Reverse bent) 22 Data Sheet M14669EJ7V0DS µPD442000A-X Revision History Edition/ Page Date Type of This Previous edition edition 6th edition/ pp.6, 7 pp.6, 7 Location Description (Previous edition → This edition) revision Modification DC Characteristics -BB55X,-BB70X,-BB85X(MAX.) : ISB = 0.6mA → 0.35mA -BC70X,-BC85X,-BC10X(MAX.) : ISB = 0.6mA → 0.35mA Jul. 2002 -BC70X,-BC85X,-BC10X(MAX.) : ISB(VCC ≥ 2.7 V) = 0.6mA → 0.35mA -DD85X,-DD10X,-DD12X(MAX.) : ISB = 0.6mA → 0.35mA p.8 p.8 Modification AC Characteristics Integration of Input Waveform and Output Waveform 7th edition/ pp.2, 4, 21-22 pp.2, 3, 19-20 Addition Ordering Information, 32-pin PLASTIC TSOP (I) (8×13.4) (Reverse bent) Oct. 2002 Pin Configurations, µPD442000AGU-***-9KH Package Drawings, *** : Speed grades Recommended BB55X, BB70X, BB85X, BC70X, BC85X, BC10X, Soldering Conditions DD85X, DD10X, DD12X Data Sheet M14669EJ7V0DS 23 µPD442000A-X [ MEMO ] 24 Data Sheet M14669EJ7V0DS µPD442000A-X [ MEMO ] Data Sheet M14669EJ7V0DS 25 µPD442000A-X [ MEMO ] 26 Data Sheet M14669EJ7V0DS µPD442000A-X NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M14669EJ7V0DS 27 µPD442000A-X • The information in this document is current as of October, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4