DATA SHEET MOS INTEGRATED CIRCUIT µPD43256B 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT Description The µPD43256B is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM. Battery backup is available. And A and B versions are wide voltage operations. The µPD43256B is packed in 28-pin plastic DIP, 28-pin plastic SOP and 28-pin plastic TSOP (I) (8 x 13.4 mm). Features • 32,768 words by 8 bits organization • Fast access time: 70, 85, 100, 120, 150 ns (MAX.) • Low voltage operation (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V) • Low VCC data retention: 2.0 V (MIN.) • /OE input for easy application Part number Access time Operating supply Operating ambient ns (MAX.) µPD43256B-xxL 70, 85 Supply current voltage temperature At operating At standby At data retention V °C mA (MAX.) µA (MAX.) µA (MAX.) Note1 4.5 to 5.5 0 to 70 45 50 3 15 2 µPD43256B-xxLL µPD43256B-Axx µPD43256B-Bxx Note2 85, 100 Note2 , 120 Note2 100, 120, 150 3.0 to 5.5 2.7 to 5.5 Notes 1. TA ≤ 40 °C, VCC = 3.0 V 2. Access time: 85 ns (MAX.) (VCC = 4.5 to 5.5 V) Version X and P This Data sheet can be applied to the version X and P. Each version is identified with its lot number. Letter X in the fifth character position in a lot number signifies version X, letter P, version P. JAPAN D43256B Lot number The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M10770EJCV0DS00 (12th edition) Date Published June 2000 NS CP (K) Printed in Japan The mark ★ shows major revised points. © 1990, 1993, 1994 µPD43256B Ordering Information Part number Package Access time ns (MAX.) µPD43256BCZ-70L 28-PIN PLASTIC DIP 70 µPD43256BCZ-85L (15.24 mm (600)) 85 µPD43256BCZ-70LL 70 µPD43256BCZ-85LL 85 µPD43256BGU-70L 28-PIN PLASTIC SOP 70 µPD43256BGU-85L (11.43 mm (450)) 85 µPD43256BGU-70LL 70 µPD43256BGU-85LL 85 µPD43256BGU-A85 85 µPD43256BGU-A10 100 µPD43256BGU-A12 120 µPD43256BGU-B10 100 µPD43256BGU-B12 120 µPD43256BGW-70LL-9JL 28-PIN PLASTIC TSOP (I) 70 µPD43256BGW-85LL-9JL (8x13.4) (Normal bent) 85 µPD43256BGW-A85-9JL 85 µPD43256BGW-A10-9JL 100 µPD43256BGW-A12-9JL 120 µPD43256BGW-B10-9JL 100 µPD43256BGW-B12-9JL 120 µPD43256BGW-B15-9JL 150 µPD43256BGW-70LL-9KL 28-PIN PLASTIC TSOP (I) 70 µPD43256BGW-85LL-9KL (8x13.4) (Reverse bent) 85 µPD43256BGW-A85-9KL 85 µPD43256BGW-A10-9KL 100 µPD43256BGW-A12-9KL 120 µPD43256BGW-B10-9KL 100 µPD43256BGW-B12-9KL 120 µPD43256BGW-B15-9KL 150 2 Data Sheet M10770EJCV0DS00 Operating supply Operating ambient voltage temperature V °C 4.5 to 5.5 0 to 70 Remark L version LL version L version LL version 3.0 to 5.5 A version 2.7 to 5.5 B version 4.5 to 5.5 LL version 3.0 to 5.5 A version 2.7 to 5.5 B version 4.5 to 5.5 LL version 3.0 to 5.5 A version 2.7 to 5.5 B version µPD43256B Pin Configurations (Marking Side) /xxx indicates active low signal. 28-PIN PLASTIC DIP (15.24 mm (600)) [ µPD43256BCZ-xxL ] [ µPD43256BCZ-xxLL ] A14 1 28 VCC A12 2 27 /WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 /OE A2 8 21 A10 A1 9 20 /CS A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 GND 14 15 I/O4 A0 - A14 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CS : Chip Select /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M10770EJCV0DS00 3 µPD43256B 28-PIN PLASTIC SOP (11.43 mm (450)) [ µPD43256BGU-xxL ] [ µPD43256BGU-xxLL ] [ µPD43256BGU-Axx ] [ µPD43256BGU-Bxx ] A14 1 28 VCC A12 2 27 /WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 /OE A2 8 21 A10 A1 9 20 /CS A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 GND 14 15 I/O4 A0 - A14 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CS : Chip Select /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground Remark Refer to Package Drawings for the 1-pin index mark. 4 Data Sheet M10770EJCV0DS00 µPD43256B 28-PIN PLASTIC TSOP (I) (8x13.4) (Normal bent) [ µPD43256BGW-xxLL-9JL ] [ µPD43256BGW-Axx-9JL ] [ µPD43256BGW-Bxx-9JL ] /OE A11 A9 A8 A13 /WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 28-PIN PLASTIC TSOP (I) (8x13.4) (Reverse bent) [ µPD43256BGW-xxLL-9KL ] [ µPD43256BGW-Axx-9KL ] [ µPD43256BGW-Bxx-9KL ] A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A0 - A14 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CS : Chip Select /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground /OE A11 A9 A8 A13 /WE VCC A14 A12 A7 A6 A5 A4 A3 Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M10770EJCV0DS00 5 µPD43256B Block Diagram A0 Address buffer A14 Row decoder I/O1 Input data controller I/O8 Memory cell array 262,144 bits Sense amplifier / Switching circuit Column decoder Output data controller Address buffer /CS /OE /WE VCC GND Truth Table /CS /OE /WE Mode I/O Supply current H × × Not selected High impedance ISB L H H Output disable L × L Write DIN L L H Read DOUT ICCA Remark × : VIH or VIL 6 Data Sheet M10770EJCV0DS00 µPD43256B Electrical Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage Condition Rating VCC –0.5 –0.5 Note Note Unit to +7.0 V to VCC + 0.5 V Input / Output voltage VT Operating ambient temperature TA 0 to 70 °C Storage temperature Tstg –55 to +125 °C Note –3.0 V (MIN.) (Pulse width : 50 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition µPD43256B-xxL µPD43256B-Axx µPD43256B-Bxx Unit µPD43256B-xxLL MIN. MAX. MIN. MAX. MIN. MAX. Supply voltage VCC 4.5 5.5 3.0 5.5 2.7 5.5 V High level input voltage VIH 2.2 VCC+0.5 2.2 VCC+0.5 2.2 VCC+0.5 V +0.5 V 70 °C Low level input voltage VIL –0.3 Operating ambient temperature TA 0 Note +0.8 –0.3 70 Note +0.5 0 70 –0.3 0 Note Note –3.0 V (MIN.) (Pulse width: 50 ns) Capacitance (TA = 25 °C, f = 1 MHz) Parameter Symbol Test conditions MIN. TYP. MAX. Unit Input capacitance CIN VIN = 0 V 5 pF Input / Output capacitance CI/O VI/O = 0 V 8 pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are periodically sampled and not 100% tested. Data Sheet M10770EJCV0DS00 7 µPD43256B DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2) Parameter Symbol Test condition µPD43256B-xxL MIN. TYP. µPD43256B-xxLL MAX. MIN. TYP. Unit MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /OE = VIH or –1.0 +1.0 –1.0 +1.0 µA mA /CS = VIH or /WE = VIL Operating supply current ICCA1 /CS = VIL, Minimum cycle time, II/O = 0 mA 45 45 ICCA2 /CS = VIL, II/O = 0 mA 10 10 ICCA3 /CS ≤ 0.2 V, Cycle = 1 MHz, 10 10 3 3 mA 15 µA II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V Standby supply current High level output voltage Low level output voltage ISB /CS = VIH ISB1 /CS ≥ VCC − 0.2 V VOH1 IOH = –1.0 mA 2.4 2.4 VOH2 IOH = –0.1 mA VCC–0.5 VCC–0.5 VOL IOL = 2.1 mA 1.0 0.4 Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of package types. 8 50 Data Sheet M10770EJCV0DS00 0.5 V 0.4 V µPD43256B DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2) Parameter Symbol µPD43256B-Axx Test condition MIN. TYP. µPD43256B-Bxx MAX. MIN. TYP. Unit MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /OE = VIH or –1.0 +1.0 –1.0 +1.0 µA mA /CS = VIH or /WE = VIL Operating supply current ICCA1 /CS = VIL, µPD43256B-Axx 45 – Minimum cycle time, µPD43256B-Bxx – 45 VCC ≤ 3.3 V – 20 10 10 – 5 /CS ≤ 0.2 V, Cycle = 1 MHz, II/O = 0 mA, 10 10 VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V – 5 3 3 – 2 II/O = 0 mA ICCA2 /CS = VIL, II/O = 0 mA VCC ≤ 3.3 V ICCA3 Standby supply current ISB VCC ≤ 3.3 V /CS = VIH VCC ≤ 3.3 V ISB1 /CS ≥ VCC − 0.2 V 0.5 VCC ≤ 3.3 V High level output voltage Low level output voltage VOH1 15 0.5 15 – 0.5 10 IOH = –1.0 mA, VCC ≥ 4.5 V 2.4 2.4 IOH = –0.5 mA, VCC < 4.5 V 2.4 2.4 VCC–0.1 VCC–0.1 µA V VOH2 IOH = –0.02 mA VOL IOL = 2.1 mA, VCC ≥ 4.5 V 0.4 0.4 IOL = 1.0 mA, VCC < 4.5 V 0.4 0.4 IOL = 0.02 mA 0.1 0.1 VOL1 mA V Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of package types. Data Sheet M10770EJCV0DS00 9 µPD43256B AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [ µPD43256B-70L, µPD43256B-85L, µPD43256B-70LL, µPD43256B-85LL ] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.2 V Test points 1.5 V 1.5 V 0.8 V Output Waveform 1.5 V Test points 1.5 V Output Load AC characteristics should be measured with the following output load conditions. Figure 1 Figure 2 (tAA, tACS, tOE, tOH) (tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW) +5 V +5 V 1.8 kΩ I/O (Output) 1.8 kΩ I/O (Output) 990 Ω 990 Ω 100 pF CL 5 pF CL Remark CL includes capacitance of the probe and jig, and stray capacitance. [ µPD43256B-A85, µPD43256B-A10, µPD43256B-A12, µPD43256B-B10, µPD43256B-B12, µPD43256B-B15 ] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.2 V 1.5 V Test points 1.5 V 0.5 V Output Waveform 1.5 V Test points 1.5 V Output Load AC characteristics should be measured with the following output load conditions. 10 tAA, tACS, tOE, tOH tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW 1TTL + 100 pF 1TTL + 5 pF Data Sheet M10770EJCV0DS00 µPD43256B Read Cycle (1/2) Parameter VCC ≥ 4.5 V Symbol Unit µPD43256B-70 Condition µPD43256B-85 µPD43256B-A85/A10/A12 µPD43256B-B10/B12/B15 MIN. MAX. MIN. Read cycle time tRC Address access time tAA 70 85 ns /CS access time tACS 70 85 ns /OE access time tOE 35 40 ns Output hold from address change tOH 10 10 ns /CS to output in low impedance tCLZ 10 10 ns /OE to output in low impedance tOLZ 5 5 ns /CS to output in high impedance tCHZ 30 30 ns /OE to output in high impedance tOHZ 30 30 ns Note 70 MAX. 85 ns Note See the output load. Remark These AC characteristics are in common regardless of package types and L, LL versions. Read Cycle (2/2) Parameter VCC ≥ 3.0 V Symbol µPD43256B -A85 µPD43256B -A10 VCC ≥ 2.7 V µPD43256B -A12 µPD43256B -B10 µPD43256B -B12 Unit µPD43256B -B15 Condition MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Read cycle time tRC Address access time tAA 85 100 120 100 120 150 ns /CS access time tACS 85 100 120 100 120 150 ns /OE access time tOE 50 60 60 60 60 70 ns Output hold from address change tOH 10 10 10 10 10 10 ns /CS to output in low impedance tCLZ 10 10 10 10 10 10 ns /OE to output in low impedance tOLZ 5 5 5 5 5 5 ns /CS to output in high impedance tCHZ 35 35 40 35 40 50 ns /OE to output in high impedance tOHZ 35 35 40 35 40 50 ns Note 85 100 120 100 120 150 ns Note See the output load. Remark These AC characteristics are in common regardless of package types. Data Sheet M10770EJCV0DS00 11 µPD43256B Read Cycle Timing Chart tRC Address (Input) tAA tOH /CS (Input) tCHZ tACS tCLZ /OE (Input) tOHZ tOE tOLZ I/O (Output) Remark 12 High impedance In read cycle, /WE should be fixed to high level. Data Sheet M10770EJCV0DS00 Data out µPD43256B Write Cycle (1/2) Parameter VCC ≥ 4.5 V Symbol Unit µPD43256B-70 Condition µPD43256B-85 µPD43256B-A85/A10/A12 µPD43256B-B10/B12/B15 MIN. MAX. MIN. MAX. Write cycle time tWC 70 85 ns /CS to end of write tCW 50 70 ns Address valid to end of write tAW 50 70 ns Write pulse width tWP 55 60 ns Data valid to end of write tDW 30 35 ns Data hold time tDH 0 0 ns Address setup time tAS 0 0 ns Write recovery time tWR 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW Note 30 30 10 Note ns 10 ns See the output load. Remark These AC characteristics are in common regardless of package types and L, LL versions. Write Cycle (2/2) Parameter VCC ≥ 3.0 V Symbol µPD43256B -A85 µPD43256B -A10 VCC ≥ 2.7 V µPD43256B -A12 µPD43256B -B10 µPD43256B -B12 Unit Con- µPD43256B -B15 dition MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Write cycle time tWC 85 100 120 100 120 150 ns /CS to end of write tCW 70 70 90 70 90 100 ns Address valid to end of write tAW 70 70 90 70 90 100 ns Write pulse width tWP 60 60 80 60 80 90 ns Data valid to end of write tDW 60 60 70 60 70 80 ns Data hold time tDH 0 0 0 0 0 0 ns Address setup tAS 0 0 0 0 0 0 ns Write recovery tWR 0 0 0 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW Note 30 10 35 10 40 10 35 10 40 10 50 10 ns Note ns See the output load. Remark These AC characteristics are in common regardless of package types. Data Sheet M10770EJCV0DS00 13 µPD43256B Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW /CS (Input) tAW tAS tWP tWR /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out tDW High impedance Data in tDH High impedance Indefinite data out Cautions 1. /CS or /WE should be fixed to high level during address transition. • 2. When I/O pins are in the output state, therefore the input signals must not be applied to the output. Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE. 2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. 3. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 14 Data Sheet M10770EJCV0DS00 µPD43256B Write Cycle Timing Chart 2 (/CS Controlled) tWC Address (Input) tAS tCW /CS (Input) tAW tWP tWR /WE (Input) tDW tDH High impedance Data in I/O (Input) High impedance Cautions 1. /CS or /WE should be fixed to high level during address transition. • 2. When I/O pins are in the output state, therefore the input signals must not be applied to the output. Remark Write operation is done during the overlap time of a low level /CS and a low level /WE. Data Sheet M10770EJCV0DS00 15 µPD43256B Low VCC Data Retention Characteristics (TA = 0 to 70 °C) Parameter Symbol µPD43256B-xxL Test Condition µPD43256B-xxLL Unit µPD43256B-Axx µPD43256B-Bxx MIN. TYP. MAX. MIN. 5.5 2.0 TYP. MAX. VCCDR /CS ≥ VCC − 0.2 V Data retention supply current ICCDR VCC = 3.0 V, /CS ≥ VCC − 0.2 V Chip deselection to data retention mode tCDR 0 0 ns tR 5 5 ms Data retention supply voltage Operation recovery time 2.0 0.5 20 Note1 Notes 1. 3 µA (TA ≤ 40 °C) 2. 2 µA (TA ≤ 40 °C), 1 µA (TA ≤ 25 °C) Data Retention Timing Chart tCDR Data retention mode VCC 4.5 V Note /CS VIH (MIN.) VCCDR (MIN.) /CS ≥ VCC – 0.2 V VIL (MAX.) GND Note A version : 3.0 V, B version : 2.7 V Remark The other pins (Address, /OE, /WE, I/O) can be in high impedance state. 16 Data Sheet M10770EJCV0DS00 tR 5.5 0.5 7 Note2 V µA µPD43256B Package Drawings 28-PIN PLASTIC DIP (15.24 mm (600)) 28 15 1 14 A J K I L F D C N B R M M H G NOTES 1. Each lead centerline is located within 0.25 mm of its true position (T.P.) at maximum material condition. 2. Item "K" to center of leads when formed parallel. ITEM MILLIMETERS A 38.10 MAX. B 2.54 MAX. C 2.54 (T.P.) D 0.50±0.10 F 1.2 MIN. G 3.6±0.3 H 0.51 MIN. I 4.31 MAX. J 5.72 MAX. K L 15.24 (T.P.) 13.2 M 0.25 +0.10 −0.05 N 0.25 R 0 - 15° P28C-100-600A1-2 Data Sheet M10770EJCV0DS00 17 µPD43256B • 28-PIN PLASTIC SOP (11.43 mm (450)) 28 15 detail of lead end P 1 14 A F H G I J S C D M N M L S B K E NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 18.0 +0.6 −0.05 B 1.27 MAX. C 1.27 (T.P.) D 0.42 +0.08 −0.07 E 0.2±0.1 F 2.95 MAX. G 2.55±0.1 H 11.8±0.3 I 8.4±0.1 J 1.7±0.2 K 0.22±0.05 L M 0.7±0.2 0.12 N 0.10 P 3° +7° −3° P28GU-50-450A-4 18 Data Sheet M10770EJCV0DS00 µPD43256B 28-PIN PLASTIC TSOP(I) (8x13.4) 1 28 detail of lead end S R 14 Q 15 P A J I G S L B C H N S D M M K NOTES 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.) ITEM A MILLIMETERS 8.0±0.1 B C 0.6 MAX. 0.55 (T.P.) D 0.22 +0.08 −0.07 G H 1.0 12.4±0.2 I 11.8±0.1 J 0.8±0.2 K 0.145 +0.025 −0.015 L 0.5±0.1 M 0.08 N 0.10 P 13.4±0.2 Q 0.1±0.05 R S 3° +7° −3° 1.2 MAX. P28GW-55-9JL-2 Data Sheet M10770EJCV0DS00 19 µPD43256B 28-PIN PLASTIC TSOP(I) (8x13.4) 1 28 detail of lead end Q R 14 15 S K N H D S L M M C B S G I J A P NOTE 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.) ITEM MILLIMETERS A 8.0±0.1 B C 0.6 MAX. 0.55 (T.P.) D 0.22 +0.08 −0.07 G H 1.0 12.4±0.2 I 11.8±0.1 J 0.8±0.2 K 0.145 +0.025 −0.015 L M 0.5±0.1 0.08 N 0.10 P 13.4±0.2 Q 0.1±0.05 R 3° +7° −3° S 1.2 MAX. P28GW-55-9KL-2 20 Data Sheet M10770EJCV0DS00 µPD43256B Recommended Soldering Conditions The following conditions (See table below) must be met when soldering µPD43256B. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. Types of Surface Mount Device µPD43256BGU-xxL : 28-PIN PLASTIC SOP (11.43 mm (450)) µPD43256BGU-xxLL : 28-PIN PLASTIC SOP (11.43 mm (450)) µPD43256BGU-Axx : 28-PIN PLASTIC SOP (11.43 mm (450)) µPD43256BGU-Bxx : 28-PIN PLASTIC SOP (11.43 mm (450)) µPD43256BGW-xxLL-9JL : 28-PIN PLASTIC TSOP (I) (8x13.4) (Normal bent) µPD43256BGW-xxLL-9KL : 28-PIN PLASTIC TSOP (I) (8x13.4) (Reverse bent) µPD43256BGW-Axx-9JL : 28-PIN PLASTIC TSOP (I) (8x13.4) (Normal bent) µPD43256BGW-Axx-9KL : 28-PIN PLASTIC TSOP (I) (8x13.4) (Reverse bent) µPD43256BGW-Bxx-9JL : 28-PIN PLASTIC TSOP (I) (8x13.4) (Normal bent) µPD43256BGW-Bxx-9KL : 28-PIN PLASTIC TSOP (I) (8x13.4) (Reverse bent) Please consult with our sales offices. Types of Through Hole Mount Device µPD43256BCZ-xxL : 28-PIN PLASTIC DIP (15.24 mm (600)) µPD43256BCZ-xxLL : 28-PIN PLASTIC DIP (15.24 mm (600)) Soldering process Wave soldering (only to leads) Soldering conditions Solder temperature : 260 °C or below, Flow time : 10 seconds or below Partial heating method Terminal temperature : 300 °C or below, Time : 3 seconds or below (Per one lead) Caution Do not jet molten solder on the surface of package. Data Sheet M10770EJCV0DS00 21 µPD43256B [ MEMO ] 22 Data Sheet M10770EJCV0DS00 µPD43256B NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M10770EJCV0DS00 23 µPD43256B • The information in this document is current as of June, 2000. The information is subject to change without notice. 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