NEC UPD75P0076CU

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P0076
4-BIT SINGLE-CHIP MICROCONTROLLER
The µPD75P0076 replaces the µPD750068’s internal mask ROM with a one-time PROM and features expanded ROM
capacity.
Because the µPD75P0076 supports programming by users, it is suitable for use in prototype testing for system
development using the µPD750064, 750066, and 750068 products, and for use in small-lot production.
Detailed information about function is provided in the following user’s manual.
Be sure to read it before designing:
µPD750068 User’s Manual: U10670E
FEATURES
Compatible with µPD750068
Memory capacity:
• PROM : 16384 x 8 bits
• RAM
: 512 x 4 bits
Can operate with same power supply voltage as the mask ROM version µPD750068
VDD = 1.8 to 5.5 V
On-chip A/D converter capable of low-voltage operation (AVREF = 1.8 to 5.5 V)
8-bit resolution x 8 channels
Small shrink SOP package
ORDERING INFORMATION
Part Number
Package
µPD75P0076CU
42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
µPD75P0076GT
42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
Caution On-chip pull-up resistors by mask option cannot be provided.
The information in this document is subject to change without notice.
Document No. U10232EJ1V0DS00 (1st edition)
Date Published December 1996 N
Printed in Japan
The mark
shows major revised points.
©
1995
µPD75P0076
Functional Outline
Parameter
Instruction execution time
• 0.95, 1.91, 3.81, 15.3 µs (@ 4.19 MHz with main system clock)
• 0.67, 1.33, 2.67, 10.7 µs (@ 6.0 MHz with main system clock)
• 122 µs (@ 32.768 kHz with subsystem clock)
On-chip memory
PROM
16384 x 8 bits
RAM
512 x 4 bits
General-purpose register
• 4-bit operation: 8 x 4 banks
• 8-bit operation: 4 x 4 banks
Input/
output
CMOS input
12
Connections of on-chip pull-up resistors can be specified by software: 7
Also used for analog input pins: 4
CMOS input/output
12
Connections of on-chip pull-up resistors can be specified by software: 12
Also used for analog input pins: 4
N-ch open-drain
input/output pins
8
13-V withstand voltage
Total
32
port
2
Function
Timer
4
•
•
•
channels
8-bit timer/event counter: 2 channels (can be used as the 16-bit timer/event counter)
8-bit basic interval timer/watchdog timer: 1 channel
Watch timer: 1 channel
Serial interface
• 3-wire serial I/O mode ··· MSB or LSB can be selected for transferring first bit
• 2-wire serial I/O mode
A/D converter
8-bit resolution x 8 channels (1.8 V ≤ AVREF ≤ VDD)
Bit sequential buffer
16 bits
Clock output (PCL)
• Φ, 1.05 MHz, 262 kHz, 65.5 kHz (@ 4.19 MHz with main system clock)
• Φ, 1.5 MHz, 375 kHz, 93.8 kHz (@ 6.0 MHz with main system clock)
Buzzer output (BUZ)
• 2, 4, 32 kHz (@ 4.19 MHz with main system clock or
@ 32.768 kHz with subsystem clock)
• 2.93, 5.86, 46.9 kHz (@ 6.0 MHz with main system clock)
Vectored interrupts
External: 3, Internal: 4
Test input
External: 1, Internal: 1
System clock oscillator
• Ceramic or crystal oscillator for main system clock oscillation
• Crystal oscillator for subsystem clock oscillation
Standby function
STOP/HALT mode
Operating ambient temperature
T A = –40 to +85 ˚C
Power supply voltage
VDD = 1.8 to 5.5 V
Package
• 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
• 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
µPD75P0076
CONTENTS
1. PIN CONFIGURATION (Top View) ...................................................................................................
4
2. BLOCK DIAGRAM ............................................................................................................................
5
3. PIN FUNCTIONS ...............................................................................................................................
6
3.1
Port Pins ...................................................................................................................................................
6
3.2
Non-port Pins ...........................................................................................................................................
7
3.3
Equivalent Circuits for Pins ....................................................................................................................
9
3.4
Handling of Unused Pins ......................................................................................................................... 12
4. SWITCHING BETWEEN Mk I AND Mk II MODES ............................................................................ 13
4.1
Difference betweens Mk I Mode and Mk II Mode .................................................................................... 13
4.2
Setting of Stack Bank Selection (SBS) Register .................................................................................... 14
5. DIFFERENCES BETWEEN µPD75P0076 AND µPD750064, 750066 AND 750068 ........................ 15
6. MEMORY CONFIGURATION ............................................................................................................ 16
7. INSTRUCTION SET ........................................................................................................................... 18
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY .................................................... 29
8.1
Operation Modes for Program Memory Write/Verify ............................................................................. 29
8.2
Steps in Program Memory Write Operation ............................................................................................ 30
8.3
Steps in Program Memory Read Operation ............................................................................................ 31
8.4
One-time PROM Screening ..................................................................................................................... 32
9. ELECTRICAL SPECIFICATIONS...................................................................................................... 33
10. CHARACTERISTICS CURVES (REFERENCE VALUES) ................................................................ 49
11. PACKAGE DRAWINGS .................................................................................................................... 51
12. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 53
APPENDIX A DIFFERENCES AMONG µPD75068, 750068 AND 75P0076 ......................................... 54
APPENDIX B DEVELOPMENT TOOLS ................................................................................................. 55
APPENDIX C RELATED DOCUMENTS ................................................................................................. 58
3
µPD75P0076
1. PIN CONFIGURATION (Top View)
• 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
µPD75P0076CU
• 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
µPD75P0076GT
XT1
XT2
RESET
X1
X2
P33/MD3
P32/MD2
P31/MD1
P30/MD0
AVSS
P63/KR3/AN7
P62/KR2/AN6
P61/KR1/AN5
P60/KR0/AN4
P113/AN3
P112/AN2
P111/AN1
P110/AN0
AVREF
VPP
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VSS
P40/D0
P41/D1
P42/D2
P43/D3
P50/D4
P51/D5
P52/D6
P53/D7
P00/INT4
P01/SCK
P02/SO/SB0
P03/SI/SB1
P10/INT0
P11/INT1
P12/TI1/INT2
P13/TI0
P20/PTO0
P21/PTO1
P22/PCL
P23/BUZ
In normal operation mode, make sure to connect VPP directly to VDD.
Pin Identification
AN0 to AN7
AVREF
AVSS
BUZ
D0 to D7
INT0, INT1, INT4
INT2
KR0 to KR3
MD0 to MD3
P00 to P03
P10 to P13
P20 to P23
P30 to P33
P40 to P43
P50 to P53
P60 to P63
4
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Analog Input 0 to 7
Analog Reference
Analog Ground
Buzzer Clock
Data Bus 0 to 7
External Vectored Interrupt 0, 1, 4
External Test Input 2
Key Return
Mode Selection 0 to 3
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
P110 to P113
PCL
PTO0, PTO1
RESET
SB0, SB1
SCK
SI
SO
TI0, TI1
VDD
VPP
VSS
X1, X2
XT1, XT2
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Port 11
Programmable Clock
Programmable Timer Output 0, 1
Reset Input
Serial Data Bus 0, 1
Serial Clock
Serial Input
Serial Output
Timer Input 0, 1
Positive Power Supply
Programmable Power Supply
Ground
Main System Clock Oscillation 1, 2
Subsystem Clock Oscillation 1, 2
µPD75P0076
2. BLOCK DIAGRAM
PORT0
4
P00 to P03
PORT1
4
P10 to P13
PORT2
4
P20 to P23
PORT3
4
P30/MD0 to
P33/MD3
BANK
PORT4
4
P40/D0 to
P43/D3
GENERAL REG.
PORT5
4
P50/D4 to
P53/D7
PORT6
4
P60 to P63
PORT11
4
P110 to P113
BASIC INTERVAL
TIMER/WATCHDOG
TIMER
SP (8)
INTBT
WATCH TIMER
BUZ/P23
INTW
INTW
INTT0
8-BIT
TIMER/
EVENT
CASCADED
COUNTER#0 16-BIT
TI0/P13
PTO0/P20
CY
ALU
SBS
PROGRAM COUNTER
TIMER/
EVENT
8-BIT
COUNTER
TIMER/
EVENT
COUNTER#1
TI1/P12/INT2
PTO1/P21
INTT1
SI/SB1/P03
PROGRAM
MEMORY
(PROM)
16384 x 8 BITS
DATA MEMORY
(RAM)
512 x 4BITS
CLOCKED SERIAL
INTERFACE
SO/SB0/P02
SCK/P01
INTCSI TOUT0
BIT SEQ. BUFFER (16)
DECODE
AND
CONTROL
INT0/P10
INT1/P11
INTERRUPT
CONTROL
INT4/P00
INT2/P12/TI1
KR0/P60 to
4
KR3/P63
AN0/P110 to
AN3/P113
4
AN4/P60 to
AN7/P63
4
fx/2N
CPU CLOCK Φ
SYSTEM CLOCK
CLOCK
CLOCK GENERATOR
STAND BY
OUTPUT
CONTROL
CONTROL DIVIDER SUB
MAIN
A/D CONVERTER
PCL/P22
XT1 XT2 X1 X2
VPP VDD
VSS RESET
AVREF
AVSS
5
µPD75P0076
3. PIN FUNCTIONS
3.1 Port Pins
Pin name
I/O
Alternate function
Function
After
reset
I/O circuit
typeNote 1
Not
available
Input
<B>
P00
I
INT4
P01
I/O
SCK
P02
I/O
SO/SB0
<F>-B
P03
I/O
SI/SB1
<M>-C
P10
I
INT0
P11
INT1
P12
TI1/INT2
P13
TI0
P20
I/O
PTO0
P21
PTO1
P22
PCL
P23
BUZ
P30
I/O
MD0
P31
MD1
P32
MD2
P33
P40
<F>-A
This is a 4-bit input port (PORT1).
Connections of on-chip pull-up resistors are
software-specifiable in 4-bit units. P10/INT0
can select a noise elimination circuit.
Not
available
Input
<B>-C
This is a 4-bit I/O port (PORT2).
Connections of on-chip pull-up resistors are
software-specifiable in 4-bit units.
Not
available
Input
E-B
This is a programmable 4-bit I/O port (PORT3).
Input and output can be specified in single-bit
units. Connections of on-chip pull-up resistors
are software-specifiable in 4-bit units.
Not
available
Input
E-B
This is an N-ch open-drain 4-bit I/O port
(PORT4). In the open-drain mode, withstands
up to 13 V. Also used as data I/O pin
(lower 4 bits) for program memory (PROM)
write/verify.
Available
High
impedance
M-E
High
impedance
M-E
MD3
Note 2
I/O
D0
P41Note 2
D1
P42Note 2
D2
P43Note 2
D3
P50
This is a 4-bit input port (PORT0).
For P01 to P03, on-chip pull-up resistors are
software-specifiable in 3-bit units.
8-bit
accessible
Note 2
I/O
D4
P51Note 2
D5
P52Note 2
D6
P53Note 2
D7
P60
I/O
KR0/AN4
P61
KR1/AN5
P62
KR2/AN6
P63
KR3/AN7
P110
I
AN0
P111
AN1
P112
AN2
P113
AN3
This is an N-ch open-drain 4-bit I/O port
(PORT5). In the open-drain mode, withstands
up to 13 V. Also used as data I/O pin
(upper 4 bits) for program memory (PROM)
write/verify.
This is a programmable 4-bit I/O port (PORT6).
Input and output can be specified in single-bit
units. Connections of on-chip pull-up resistors
are software-specifiable in 4-bit units.
Not
available
Input
<Y>-D
This is a 4-bit input port (PORT11).
Not
available
Input
Y-A
Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs.
2. Low-level input current leakage increases when input instructions or bit manipulation instructions are executed.
6
µPD75P0076
3.2 Non-port Pins (1/2)
Pin name
TI0
I/O
I
TI1
PTO0
O
Alternate function
Function
P13
Inputs external event pulses to the timer/event
P12/INT2
counter.
P20
Timer/event counter output
After
reset
Circuit
typeNote
Input
<B>-C
Input
E-B
Input
<F>-A
PTO1
P21
PCL
P22
Clock output
BUZ
P23
Optional frequency output (for buzzer output or
system clock trimming)
P01
Serial clock I/O
SO/SB0
P02
Serial data output
Serial data bus I/O
<F>-B
SI/SB1
P03
Serial data input
Serial data bus I/O
<M>-C
SCK
I/O
INT4
I
P00
Edge detection vectored interrupt input (both rising
edge and falling edge detection)
INT0
I
P10
Edge detection vectored
interrupt input (detection
edge can be selected).
INT0/P10 can select a noise
eliminator.
Rising edge detection
testable input
INT1
P11
INT2
P12/TI1
Noise eliminator/
asynchronous selection
Asynchronous
<B>
Input
<B>-C
Asynchronous
KR0 to KR3
I
P60/AN4 to
P63/AN7
Falling edge detection testable input
Input
<Y>-D
AN0 to AN3
I
P110 to P113
Analog signal input
Input
Y-A
AN4 to AN7
P60/KR0 to
<Y>-D
P63/KR3
AV REF
—
—
A/D converter reference voltage
—
Z-N
AV SS
—
—
A/D converter reference GND potential
—
Z-N
X1
I
—
Crystal/ceramic connection pin for the main system
—
—
X2
—
—
—
—
<B>
clock oscillator. When inputting the external clock,
input the external clock to pin X1, and the inverted
phase of the external clock to pin X2.
XT1
XT2
I
—
—
Crystal connection pin for the subsystem clock
oscillator. When the external clock is used, input the
external clock to pin XT1, and the inverted phase of
the external clock to pin XT2. Pin XT1 can be used
as a 1-bit input (test) pin.
RESET
I
—
System reset input (low-level active)
Note Circuit types enclosed in brackets indicate Schmitt triggered inputs.
7
µPD75P0076
3.2 Non-port Pins (2/2)
Pin name
I/O
MD0 to MD3
I
P30 to 33
I/O
P40 to 43
D0 to D3
D4 to D7
After
reset
Circuit
type
Mode selection for program memory (PROM)
write/verify.
Input
E-B
Data bus pin for program memory (PROM) write/verify.
Input
M-E
—
—
Alternate function
Function
P50 to 53
V PPNote
—
—
Programmable voltage supply in program memory
(PROM) write/verify mode.
In normal operation mode, connect directly to V DD.
Apply +12.5 V in PROM write/verify mode.
VDD
—
—
Positive power supply
—
—
VSS
—
—
Ground
—
—
Note During normal operation, the VPP pin will not operate normally unless connected to VDD pin.
8
µPD75P0076
3.3 Equivalent Circuits for Pins
The equivalent circuits for the µPD75P0076’s pin are shown in schematic diagrams below.
(1/3)
TYPE A
TYPE D
VDD
VDD
Data
P-ch
OUT
P-ch
IN
Output
disable
N-ch
CMOS standard input buffer
TYPE B
N-ch
Push-pull output that can be set to high impedance output
(with both P-ch and N-ch OFF).
TYPE E-B
VDD
P.U.R.
P.U.R.
enable
IN
P-ch
Data
IN/OUT
Type D
Output
disable
Type A
Schmitt trigger input with hysteresis characteristics.
P.U.R. : Pull-Up Resistor
TYPE B-C
TYPE F-A
VDD
VDD
P.U.R.
P-ch
P.U.R.
P.U.R.
enable
P.U.R.
enable
P-ch
Data
IN/OUT
Type D
IN
Output
disable
P.U.R. : Pull-Up Resistor
Schmitt trigger input with hysteresis characteristics.
Type B
P.U.R. : Pull-Up Resistor
9
µPD75P0076
(2/3)
TYPE F-B
TYPE Y
VDD
P.U.R.
P.U.R.
enable
P-ch
Output
disable
(P)
VDD
VDD
IN
P-ch
N-ch
+
–
VDD
Sampling C
P-ch
IN/OUT
AVSS
Data
Output
disable
N-ch
Input
enable
Output
disable
(N)
AVSS
Reference voltage
(from the voltage tap of
the serial resistor string)
P.U.R. : Pull-Up Resistor
TYPE M-C
TYPE Y-A
VDD
P.U.R.
P.U.R.
enable
P-ch
IN instruction
IN/OUT
Type A
Data
N-ch
Input butfer
Output
disable
IN
P.U.R. : Pull-Up Resistor
TYPE M-E*
IN/OUT
Data
N-ch
(+13 V withstand
voltage)
Output
disable
VDD
Input
instruction
P-ch
P.U.R. Note
Voltage
control
circuit
(+13 V withstand
voltage)
Note This is a pull-up resistor which only
operates when an input instruction
is executed (when the pin is low
a current flows from VDD to the pin).
10
Type Y
µPD75P0076
(3/3)
TYPE Y-D
TYPE Z-N
VDD
AVREF
P.U.R.
P.U.R.
enable
P-ch
Data
Output
disable
IN/OUT
Type D
Reference
voltage
Type B
ADEN
N-ch
Type Y
P.U.R.: Pull-Up Resistor
AVSS
11
µPD75P0076
3.4 Handling of Unused Pins
Pin
P00/INT4
Recommended connection
Connect to VSS or VDD
P01/SCK
Independently connect to VSS or VDD through
P02/SO/SB0
resistor
P03/SI/SB1
Connected to VSS
P10/INT0, P11/INT1
Connect to VSS or VDD
P12/TI1/INT2
P13/TI0
P20/PTO0
Input mode
: independently connected to VSS
P21/PTO1
P22/PCL
or VDD through resistor
Output mode : open
P23/BUZ
P30/MD0 to P33/MD3
P40/D0 to P43/D3
Connected to VSS
P50/D4 to P53/D7
P60/KR0/AN4 to P63/KR3/AN7
Input mode
: independently connected to VSS
or VDD through resistor
Output mode : open
P110/AN0 to P113/AN3
Connected to VSS or VDD
Note
Connect to VSS or VDD
Note
XT2
Open
VPP
Make sure to connect directly to VDD
AVREF
Connect to VSS
XT1
AVSS
Note When the subsystem clock is not used, set SOS.0 = 1 (on-chip feedback resistor is not used).
12
µPD75P0076
4. SWITCHING BETWEEN Mk I AND Mk II MODES
Setting a stack bank selection (SBS) register for the µPD75P0076 enables the program memory to be switched between
the Mk I mode and the Mk II mode. This capability enables the evaluation of the µPD750064, 750066, and 750068 using
the µPD75P0076.
When the SBS bit 3 is set to 1: sets Mk I mode (corresponds to Mk I mode of µPD750064, 750066, and 750068)
When the SBS bit 3 is set to 0: sets Mk II mode (corresponds to Mk II mode of µPD750064, 750066, and 750068)
4.1 Differences between Mk I Mode and Mk II Mode
Table 4-1 lists the differences between the Mk I mode and the Mk II mode of the µPD75P0076.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Item
Mk I Mode
Mk II Mode
Program counter
PC13 to 0
Program memory (bytes)
16384
Data memory (bits)
512 x 4
Stack
Stack bank
Selectable from memory banks 0 and 1
Stack bytes
2 bytes
3 bytes
Instruction
BRA !addr1
CALLA !addr1
Not provided
Provided
Instruction
CALL !addr
3 machine cycles
4 machine cycles
execution time CALLF !faddr
2 machine cycles
3 machine cycles
Supported mask ROM versions and
mode
Mk I mode of µPD750064, 750066,
and 750068
Mk II mode of µPD750064, 750066,
and 750068
Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This
mode enhances the software compatibility with products which have more than 16K bytes.
When the Mk II mode is selected, the number of stack bytes used in execution of a subroutine call
instruction increases by 1 per stack for the usable area compared to the Mk I mode. Furthermore, when
a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle.
Therefore, when more importance is attached to RAM utilization or throughput than software
compatibility, use the Mk I mode.
13
µPD75P0076
4.2 Setting of Stack Bank Selection (SBS) Register
Use the stack bank selection register to switch between the Mk I mode and the Mk II mode. Figure 4-1 shows the format
for doing this.
The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be
sure to initialize the stack bank selection register to 100xBNote at the beginning of the program. When using the Mk II mode,
be sure to initialize it to 000xBNote.
Note Set the desired value for x.
Figure 4-1. Format of Stack Bank Selection Register
Address
F84H
3
2
1
0
SBS3 SBS2 SBS1 SBS0
Symbol
SBS
Stack area specification
0
0
Memory bank 0
0
1
Memory bank 1
1
0
1
1
0
Setting prohibited
Be sure to enter “0” for bit 2.
Mode selection specification
0
Mk II mode
1
Mk I mode
Cautions 1. SBS3 is set to “1” after RESET input, and consequently the CPU operates in the Mk I mode. When
using instructions for the Mk II mode, set SBS3 to “0” to enter the Mk II mode before using the
instructions.
2. When using the Mk II mode, execute a subroutine call instruction and an interrupt instruction after
RESET input and after setting the stack bank selection register.
14
µPD75P0076
5. DIFFERENCES BETWEEN µPD75P0076 AND µPD750064, 750066 AND 750068
The µPD75P0076 replaces the internal mask ROM in the µPD750064, 750066, and 750068 with a one-time PROM and
features expanded ROM capacity. The µPD75P0076’s Mk I mode supports the Mk I mode in the µPD750064, 750066,
and 750068 and the µPD75P0076’s Mk II mode supports the Mk II mode in the µPD750064, 750066, and 750068.
Table 5-1 lists differences among the µPD75P0076 and the µPD750064, 750066, 750068. Be sure to check the
differences between corresponding versions beforehand, especially when a PROM version is used for debugging or
prototype testing of application systems and later the corresponding mask ROM version is used for full-scale production.
For further description of CPU functions and internal hardware, see the µPD750064 and 750068 Preliminary Product
Information (U10165E).
Table 5-1. Differences between µPD75P0076 and µPD750064, 750066, 750068
µPD750064
Item
µPD750066
µPD750068
µPD75P0076
Program counter
12-bit
Program memory (bytes)
Mask ROM
4096
Data memory (x 4 bits)
512
Mask options
Pull-up resistor for
ports 4 and 5
Yes (on-chip specifiable)
No (off chip)
Wait time when
RESET
Yes (217/fX, 215/fX selectable)Note
No (fixed at 215/fX)Note
Feedback resistor of
subsystem clock
Yes (Use/not use selectable)
No (Use)
Pins 6 to 9
P33 to P30
P33/MD3 to P30/MD0
Pin 20
IC
VPP
Pins 34 to 37
P53 to P50
P53/D7 to P53/D4
Pins 38 to 41
P43 to P40
P43/D3 to P40/D0
Pin configuration
Other
Mask ROM
6144
13-bit
14-bit
Mask ROM
8192
One-time PROM
16384
Noise resistance and noise radiation may differ due to different circuit complexities
and mask layouts.
Note 217/fX is 21.8 ms in 6.0 MHz operation and 31.3 ms in 4.19 MHz operation.
215/fX is 5.46 ms in 6.0 MHz operation and 7.81 ms in 4.19 MHz operation.
Caution Noise resistance and noise radiation are different in PROM version and mask ROM versions. If using
a mask ROM version instead of the PROM version for processes between prototype development and
full production, be sure to fully evaluate the CS of the mask ROM version (not ES).
15
µPD75P0076
6. MEMORY CONFIGURATION
Figure 6-1. Program Memory Map
0000H
7
6
MBE
RBE
0
Internal reset start address (upper 6 bits)
Internal reset start address (lower 8 bits)
0002H
MBE
RBE
INTBT/INT4 start address (upper 6 bits)
INTBT/INT4 start address (lower 8 bits)
0004H
MBE
RBE
INT0 start address (upper 6 bits)
CALLF
!faddr instruction
entry address
INT0 start address (lower 8 bits)
0006H
MBE
RBE
0008H
MBE
RBE
INT1 start address (upper 6 bits)
INT1 start address (lower 8 bits)
INTCSI start address (upper 6 bits)
BRCB
!caddr instruction
branch address
INTCSI start address (lower 8 bits)
000AH
MBE
RBE
INTT0 start address (upper 6 bits)
INTT0 start address (lower 8 bits)
000CH
MBE
RBE
INTT1 start address (upper 6 bits)
INTT1 start address (lower 8 bits)
0020H
Reference table for GETI instruction
007FH
0080H
Branch address for
the following instructions
• BR BCDE
• BR BCXA
• BR !addr
• BRA !addr1 Note
• CALLA !addr1 Note
CALL !addr instruction
subroutine
entry address
BR $addr instruction
relative branch address
(–15 to –1,
+2 to +16)
07FFH
0800H
0FFFH
1000H
BRCB
!caddr instruction
branch address
1FFFH
2000H
BRCB
!caddr instruction
branch address
2FFFH
3000H
Branch destination
address specified by
GETI instruction,
subroutine entry
address
BRCB
!caddr instruction
branch address
3FFFH
Note Can be used only in Mk II mode.
Remark
For instructions other than those noted above, the “BR PCDE” and “BR PCXA” instructions can be used to
branch to addresses with changes in the PC’s lower 8 bits only.
16
µPD75P0076
Figure 6-2. Data Memory Map
Data memory
General
register
area
Memory bank
000H
(32 x 4)
01FH
020H
Stack area
0
Note
256 x 4
(224 x 4)
Data area
static RAM
(512 x 4)
0FFH
100H
256 x 4
1
1FFH
Unimplemented
F80H
128 x 4
Peripheral hardware area
15
FFFH
Note Either memory bank 0 or 1 can be selected as the stack area.
17
µPD75P0076
7. INSTRUCTION SET
(1) Representation and coding formats for operands
In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s
operand representations (for further description, see the RA75X Assembler Package User’s Manual–Language (EEU1363)). When there are several codes, select and use just one. Uppercase letters, and + and – symbols are key words
that should be entered as they are.
For immediate data, enter an appropriate numerical value or label.
Instead of mem, fmem, pmem, bit, etc., a register flag symbol can be described as a label descriptor (for further description,
see the µPD750068 User’s Manual (U10670E)). Labels that can be entered for fmem and pmem are restricted.
Representation
Coding format
reg
X, A, B, C, D, E, H, L
reg1
X, B, C, D, E, H, L
rp
XA, BC, DE, HL
rp1
BC, DE, HL
rp2
BC, DE
rp’
XA, BC, DE, HL, XA’, BC’, DE’, HL’
rp’1
BC, DE, HL, XA’, BC’, DE’, HL’
rpa
HL, HL+, HL–, DE, DL
rpa1
DE, DL
n4
4-bit immediate data or label
n8
8-bit immediate data or label
mem
8-bit immediate data or labelNote
bit
2-bit immediate data or label
fmem
FB0H to FBFH, FF0H to FFFH immediate data or label
pmem
FC0H to FFFH immediate data or label
addr
0000H to 3FFFH immediate data or label
addr1
000H to 3FFFH immediate data or label (in Mk II mode only)
caddr
12-bit immediate data or label
faddr
11-bit immediate data or label
taddr
20H to 7FH immediate data (however, bit0 = 0) or label
PORTn
PORT0 to PORT6, PORT11
IEXXX
IEBT, IECSI, IET0, IET1, IE0 to IE2, IE4, IEW
RBn
RB0 to RB3
MBn
MB0, MB1, MB15
Note When processing 8-bit data, only even addresses can be specified.
18
µPD75P0076
(2) Operation legend
A
: A register; 4-bit accumulator
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
X
: X register
XA
: Register pair (XA); 8-bit accumulator
BC
: Register pair (BC)
DE
: Register pair (DE)
HL
: Register pair (HL)
XA’
: Expansion register pair (XA’)
BC’
: Expansion register pair (BC’)
DE’
: Expansion register pair (DE’)
HL’
: Expansion register pair (HL’)
PC
: Program counter
SP
: Stack pointer
CY
: Carry flag; bit accumulator
PSW
: Program status word
MBE
: Memory bank enable flag
RBE
: Register bank enable flag
PORTn : Port n (n = 0 to 6, 11)
IME
: Interrupt master enable flag
IPS
: Interrupt priority select register
IExxx
: Interrupt enable flag
RBS
: Register bank select register
MBS
: Memory bank select register
PCC
: Processor clock control register
.
: Delimiter for address and bit
(xx)
: Contents of address xx
xxH
: Hexadecimal data
19
µPD75P0076
(3) Description of symbols used in addressing area
*1
MB = MBE • MBS
MBS = 0, 1, 15
*2
MB = 0
*3
MBE = 0
: MB = 0 (000H to 07FH)
MB = 15 (F80H to FFFH)
MBE = 1
Data memory
addressing
: MB = MBS
MBS = 0, 1, 15
*4
MB = 15, fmem = FB0H to FBFH, FF0H to FFFH
*5
MB = 15, pmem = FC0H to FFFH
*6
addr = 0000H to 3FFFH
*7
addr, addr1 = (Current PC) –15 to (Current PC) –1
(Current PC) +2 to (Current PC) +16
*8
caddr = 0000H to 0FFFH (PC13, 12 = 00B) or
1000H to 1FFFH (PC13, 12 = 01B) or
2000H to 2FFFH (PC13, 12 = 10B) or
3000H to 3FFFH (PC13, 12 = 11B)
*9
faddr = 0000H to 07FFH
*10
taddr = 0020H to 007FH
*11
addr1 = 0000H to 3FFFH (Mk II mode only)
Remarks 1. MB indicates access-enabled memory banks.
2. In area *2, MB = 0 for both MBE and MBS.
3. In areas *4 and *5, MB = 15 for both MBE and MBS.
4. Areas *6 to *11 indicate corresponding address-enabled areas.
20
Program memory
addressing
µPD75P0076
(4) Description of machine cycles
S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as
shown below.
• No skip .......................................................................... S = 0
• Skipped instruction is 1-byte or 2-byte instruction ......... S = 1
• Skipped instruction is 3-byte instructionNote ................... S = 2
Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1
Caution
The GETI instruction is skipped for one machine cycle.
One machine cycle equals one cycle (= tCY) of the CPU clock Φ. Use the PCC setting to select among four cycle times.
21
µPD75P0076
Group
Transfer
Mnemonic
MOV
XCH
Table
reference
MOVT
Operand
No. of Machine
bytes cycle
Operation
Skip
condition
A, #n4
1
1
A ← n4
reg1, #n4
2
2
reg1 ← n4
XA, #n8
2
2
XA ← n8
String-effect A
HL, #n8
2
2
HL ← n8
String-effect B
rp2, #n8
2
2
rp2 ← n8
A, @HL
1
1
A ← (HL)
A, @HL+
1
2 + S A ← (HL), then L ← L + 1
*1
L=0
A, @HL–
1
2 + S A ← (HL), then L ← L – 1
*1
L = FH
A, @rpa1
1
1
A ← (rpa1)
*2
XA, @HL
2
2
XA ← (HL)
*1
@HL, A
1
1
(HL) ← A
*1
@HL, XA
2
2
(HL) ← XA
*1
A, mem
2
2
A ← (mem)
*3
XA, mem
2
2
XA ← (mem)
*3
mem, A
2
2
(mem) ← A
*3
mem, XA
2
2
(mem) ← XA
*3
A, reg1
2
2
A ← reg1
XA, rp’
2
2
XA ← rp’
reg1, A
2
2
reg1 ← A
rp’1, XA
2
2
rp’1 ← XA
A, @HL
1
1
A ↔ (HL)
A, @HL+
1
2 + S A ↔ (HL), then L ← L + 1
*1
L=0
A, @HL–
1
2 + S A ↔ (HL), then L ← L – 1
*1
L = FH
A, @rpa1
1
1
A ↔ (rpa1)
*2
XA, @HL
2
2
XA ↔ (HL)
*1
A, mem
2
2
A ↔ (mem)
*3
XA, mem
2
2
XA ↔ (mem)
*3
A, reg1
1
1
A ↔ reg1
XA, rp’
2
2
XA ↔ rp’
XA, @PCDE
1
3
XA ← (PC13-8 + DE)ROM
XA, @PCXA
1
3
XA ← (PC13-8 + XA)ROM
XA, @BCDE
1
3
XA ← (BCDE)ROMNote
*11
XA, @BCXA
1
3
XA ← (BCXA)
*11
Note As for the B register, only the lower 2 bits are valid.
22
Addressing
area
String-effect A
*1
*1
ROMNote
µPD75P0076
Group
Bit transfer
Operation
Mnemonic
MOV1
ADDS
ADDC
SUBS
SUBC
AND
OR
XOR
Operand
No. of Machine
bytes cycle
Operation
Addressing
area
Skip
condition
CY, fmem.bit
2
2
CY ← (fmem.bit)
*4
CY, [email protected]
2
2
CY ← (pmem7-2 + L3-2.bit(L1-0))
*5
CY, @H + mem.bit
2
2
CY ← (H + mem3-0.bit)
*1
fmem.bit, CY
2
2
(fmem.bit) ← CY
*4
[email protected], CY
2
2
(pmem7-2 + L3-2.bit(L1-0)) ← CY
*5
@H + mem.bit, CY
2
2
(H + mem3-0.bit) ← CY
*1
A, #n4
1
1 + S A ← A + n4
carry
XA, #n8
2
2 + S XA ← XA + n8
carry
A, @HL
1
1 + S A ← A + (HL)
XA, rp’
2
2 + S XA ← XA + rp’
carry
rp’1, XA
2
2 + S rp’1 ← rp’1 + XA
carry
A, @HL
1
1
A, CY ← A + (HL) + CY
XA, rp’
2
2
XA, CY ← XA + rp’ + CY
rp’1, XA
2
2
rp’1, CY ← rp’1 + XA + CY
A, @HL
1
1 + S A ← A – (HL)
XA, rp’
2
2 + S XA ← XA – rp’
borrow
rp’1, XA
2
2 + S rp’1 ← rp’1 – XA
borrow
A, @HL
1
1
A, CY ← A – (HL) – CY
XA, rp’
2
2
XA, CY ← XA – rp’ – CY
rp’1, XA
2
2
rp’1, CY ← rp’1 – XA – CY
A, #n4
2
2
A ← A^n4
A, @HL
1
1
A ← A^(HL)
XA, rp’
2
2
XA ← XA^rp’
rp’1, XA
2
2
rp’1 ← rp’1^XA
A, #n4
2
2
A ← Avn4
A, @HL
1
1
A ← Av(HL)
XA, rp’
2
2
XA ← XAvrp’
rp’1, XA
2
2
rp’1 ← rp’1vXA
A, #n4
2
2
A ← Avn4
A, @HL
1
1
A ← Av(HL)
XA, rp’
2
2
XA ← XAvrp’
rp’1, XA
2
2
rp’1 ← rp’1vXA
*1
carry
*1
*1
borrow
*1
*1
*1
*1
23
µPD75P0076
Group
Mnemonic
Operand
No. of Machine
bytes cycle
Operation
Addressing
area
Skip
condition
Accumulator
RORC
A
1
1
CY ← A0, A3 ← CY, An-1 ← An
manipulate
NOT
A
2
2
A←A
Increment/
INCS
reg
1
1 + S reg ← reg + 1
reg = 0
rp1
1
1 + S rp1 ← rp1 + 1
rp1 = 00H
@HL
2
2 + S (HL) ← (HL) + 1
*1
(HL) = 0
mem
2
2 + S (mem) ← (mem) + 1
*3
(mem) = 0
reg
1
1 + S reg ← reg – 1
reg = FH
rp’
2
2 + S rp’ ← rp’ – 1
rp’ = FFH
reg, #n4
2
2 + S Skip if reg = n4
reg = n4
@HL, #n4
2
2 + S Skip if (HL) = n4
*1
(HL) = n4
A, @HL
1
1 + S Skip if A = (HL)
*1
A = (HL)
XA, @HL
2
2 + S Skip if XA = (HL)
*1
XA = (HL)
A, reg
2
2 + S Skip if A = reg
A = reg
XA, rp’
2
2 + S Skip if XA = rp’
XA = rp’
decrement
DECS
Compare
SKE
Carry flag
SET1
CY
1
1
CY ← 1
manipulate
CLR1
CY
1
1
CY ← 0
SKT
CY
1
NOT1
CY
1
24
1 + S Skip if CY = 1
1
CY ← CY
CY = 1
µPD75P0076
Group
Memory bit
Mnemonic
SET1
manipulate
CLR1
SKT
SKF
SKTCLR
AND1
OR1
XOR1
Operand
No. of Machine
bytes cycle
Operation
Addressing
area
Skip
condition
mem.bit
2
2
(mem.bit) ← 1
*3
fmem.bit
2
2
(fmem.bit) ← 1
*4
[email protected]
2
2
(pmem7-2 + L3-2.bit(L1-0)) ← 1
*5
@H + mem.bit
2
2
(H + mem3-0.bit) ← 1
*1
mem.bit
2
2
(mem.bit) ← 0
*3
fmem.bit
2
2
(fmem.bit) ← 0
*4
[email protected]
2
2
(pmem7-2 + L3-2.bit(L1-0)) ← 0
*5
@H + mem.bit
2
2
(H + mem3-0.bit) ← 0
*1
mem.bit
2
2 + S Skip if(mem.bit) = 1
fmem.bit
2
2 + S Skip if(fmem.bit) = 1
*4
(fmem.bit) = 1
[email protected]
2
2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 1
*5
([email protected]) = 1
@H + mem.bit
2
2 + S Skip if(H + mem3-0.bit) = 1
*1
(@H+mem.bit) = 1
mem.bit
2
2 + S Skip if(mem.bit) = 0
*3
(mem.bit) = 0
fmem.bit
2
2 + S Skip if(fmem.bit) = 0
*4
(fmem.bit) = 0
[email protected]
2
2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 0
*5
([email protected]) = 0
@H + mem.bit
2
2 + S Skip if(H + mem3-0.bit) = 0
*1
(@H+mem.bit) = 0
fmem.bit
2
2 + S Skip if(fmem.bit) = 1 and clear
*4
(fmem.bit) = 1
[email protected]
2
2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 1 and clear
*5
([email protected]) = 1
@H + mem.bit
2
2 + S Skip if(H + mem3-0.bit) = 1 and clear
*1
(@H+mem.bit) = 1
CY, fmem.bit
2
2
CY ← CY^(fmem.bit)
*4
CY, [email protected]
2
2
CY ← CY^(pmem7-2 + L3-2.bit(L1-0))
*5
CY, @H + mem.bit 2
2
CY ← CY^(H + mem3-0.bit)
*1
CY, fmem.bit
2
2
CY ← CYv(fmem.bit)
*4
CY, [email protected]
2
2
CY ← CYv(pmem7-2 + L3-2.bit(L1-0))
*5
CY, @H + mem.bit 2
2
CY ← CYv(H + mem3-0.bit)
*1
CY, fmem.bit
2
2
CY ← CYv(fmem.bit)
*4
CY, [email protected]
2
2
CY ← CYv(pmem7-2 + L3-2.bit(L1-0))
*5
CY, @H + mem.bit 2
2
CY ← CYv(H + mem3-0.bit)
*1
*3
(mem.bit) = 1
25
µPD75P0076
Group
Branch
Mnemonic
BRNote 1
Operand
No. of Machine
bytes cycle
Operation
Addressing
area
addr
—
—
PC13-0 ← addr
Assembler selects the most
appropriate instruction among
the following:
• BR !addr
• BRCB !caddr
• BR $addr
*6
addr1
—
—
PC13-0 ← addr1
Assembler selects the most
appropriate instruction among
the following:
• BRA !addr1
• BR !addr
• BRCB !caddr
• BR $addr1
*11
!addr
3
3
PC13-0 ← addr
*6
$addr
1
2
PC13-0 ← addr
*7
$addr1
1
2
PC13-0 ← addr1
PCDE
2
3
PC13-0 ← PC13-8 + DE
PCXA
2
3
PC13-0 ← PC13-8 + XA
BCDE
2
3
PC13-0 ← BCDENote 2
*6
*6
BCXA
2
3
PC13-0 ← BCXA
BRA
!addr1
3
3
PC13-0 ← addr1
*11
BRCB
!caddr
2
2
PC13-0 ← PC13, 12 + caddr11-0
*8
Note 1
Note 2
Skip
condition
Notes 1. Double boxes indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.
2. As for the B register, only the lower 2 bits are valid.
26
µPD75P0076
Group
Subroutine
Mnemonic
CALLANote
Operand
!addr1
No. of Machine
bytes cycle
3
3
Operation
(SP – 6)(SP – 3)(SP – 4) ← PC11-0
Addressing
area
Skip
condition
*11
(SP – 5) ← 0, 0, PC13,12
stack control
(SP – 2) ← X, X, MBE, RBE
PC13-0 ← addr1, SP ← SP – 6
CALL
Note
!addr
3
3
(SP – 4)(SP – 1)(SP – 2) ← PC11-0
*6
(SP – 3) ← MBE, RBE, PC13, 12
PC13-0 ← addr, SP ← SP – 4
4
(SP – 6)(SP – 3)(SP – 4) ← PC11-0
(SP – 5) ← 0, 0, PC13, 12
(SP – 2) ← X, X, MBE, RBE
PC13-0 ← addr, SP ← SP – 6
CALLFNote
!faddr
2
2
(SP – 4)(SP – 1)(SP – 2) ← PC11-0
*9
(SP – 3) ← MBE, RBE, PC13, 12
PC13-0 ← 000 + faddr, SP ← SP – 4
3
(SP – 6)(SP – 3)(SP – 4) ← PC11-0
(SP – 5) ← 0, 0, PC13, 12
(SP – 2) ← X, X, MBE, RBE
PC13-0 ← 000 + faddr, SP ← SP – 6
RET
Note
1
3
MBE, RBE, PC13, 12 ← (SP + 1)
PC11-0 → (SP)(SP + 3)(SP + 2)
SP ← SP + 4
X, X, MBE, RBE ← (SP + 4)
PC11-0 ← (SP)(SP + 3)(SP + 2)
0, 0, PC13, 12 ← (SP + 1)
SP ← SP + 6
RETS
Note
1
3 + S MBE, RBE, PC13, 12 ← (SP + 1)
Unconditional
PC11-0 ← (SP)(SP + 3)(SP + 2)
SP ← SP + 4
then skip unconditionally
X, X, MBE, RBE ← (SP + 4)
PC11-0 ← (SP)(SP + 3)(SP + 2)
0, 0, PC13, 12 ← (SP + 1)
SP ← SP + 6
then skip unconditionally
RETI
1
3
MBE, RBE, PC13, 12 ← (SP + 1)
PC11-0 ← (SP)(SP + 3)(SP + 2)
PSW ← (SP + 4)(SP + 5), SP ← SP + 6
0, 0, PC13, 12 ← SP + 1
PC11-0 ← (SP)(SP + 3)(SP + 2)
PSW ← (SP + 4)(SP + 5), SP ← SP + 6
Note Double boxes indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.
27
µPD75P0076
Group
Subroutine
Mnemonic
PUSH
stack control
POP
Interrupt
Operand
1
1
(SP – 1)(SP – 2) ← rp, SP ← SP – 2
BS
2
2
(SP – 1) ← MBS, (SP – 2) ← RBS, SP ← SP – 2
rp
1
1
rp ← (SP + 1)(SP), SP ← SP + 2
BS
2
2
MBS ← (SP + 1), RBS ← (SP), SP ← SP + 2
2
2
IME(IPS.3) ← 1
2
2
IEXXX ← 1
2
2
IME(IPS.3) ← 0
IEXXX
2
2
IEXXX ← 0
A, PORTn
2
2
A ← PORTn
IEXXX
DI
I/O
IN
Note 1
Special
2
2
XA ← PORTn + 1, PORTn (n = 4)
PORTn, A
2
2
PORTn ← A
PORTn, XA
2
2
PORTn + 1, PORTn ← XA (n = 4)
HALT
2
2
Set HALT Mode (PCC.2 ← 1)
STOP
2
2
Set STOP Mode (PCC.3 ← 1)
NOP
1
1
No Operation
RBn
2
2
RBS ← n (n = 0 to 3)
MBn
2
2
MBS ← n (n = 0, 1, 15)
taddr
1
3
• When using TBR instruction
SEL
GETI
Note 2, 3
Skip
condition
(n = 0 to 6, 11)
XA, PORTn
OUTNote 1
CPU control
Addressing
area
Operation
rp
EI
control
No. of Machine
bytes cycle
(n = 2 to 6)
*10
PC13-0 ← (taddr)5-0 + (taddr + 1)
- - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -
• When using TCALL instruction
(SP – 4)(SP – 1)(SP – 2) ← PC11-0
(SP – 3) ← MBE, RBE, PC13, 12
PC13-0 ← (taddr)5-0 + (taddr + 1)
SP ← SP – 4
- - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -
• When using instruction other than
TBR or TCALL
Execute (taddr)(taddr + 1) instructions
1
3
• When using TBR instruction
Determined by
referenced
instruction
*10
PC13-0 ← (taddr)5-0 + (taddr + 1)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4
- - - - - - - - - - -
• When using TCALL instruction
(SP – 6)(SP – 3)(SP – 4) ← PC11-0
(SP – 5) ← 0, 0, PC13, 12
(SP – 2) ← X, X, MBE, RBE
PC13-0 ← (taddr)5-0 + (taddr + 1)
SP ← SP – 6
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3
• When using instruction other than
TBR or TCALL
Execute (taddr)(taddr + 1) instructions
- - - - - - - - - - -
Determined by
referenced
instruction
Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15.
2. TBR and TCALL instructions are assembler pseudo-instructions for the GETI instruction’s table definitions.
3. Double box indicates support for the Mk II mode only. Other areas indicate support for the Mk I mode only.
28
µPD75P0076
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY
The program memory in the µPD75P0076 is a 16384 x 8-bit electronic write-enabled one-time PROM. The pins listed
in the table below are used for this PROM’s write/verify operations. Clock input from the X1 pins is used instead of address
input as a method for updating addresses.
Pin name
Function
VPP
Pin (usually VDD) where programming voltage is applied during
program memory write/verify
X1, X2
Clock input pin for address updating during program memory
write/verify. Input the X1 pin’s inverted signal to the X2 pin.
MD0 to MD3
Operation mode selection pin for program memory write/verify
D0/P40 to D3/P43 (lower 4)
D4/P50 to D7/P53 (upper 4)
8-bit data I/O pin for program memory write/verify
VDD
Pin where power supply voltage is applied. Power voltage
range for normal operation is 1.8 to 5.5 V. Apply 6 V for program
memory write/verify.
Caution Pins not used for program memory write/verify should be handled as follows.
• All unused pins except XT2 ...... Connect to Vss via a pull-down resistor
• XT2 pin ........................................ Leave open
8.1 Operation Modes for Program Memory Write/Verify
When +6 V is applied to the µPD75P0076’s VDD pin and +12.5 V is applied to its VPP pin, program memory write/verify
modes are in effect. Furthermore, the following detailed operation modes can be specified by setting pins MD0 to MD3
as shown below.
Operation mode specification
Operation mode
VPP
VDD
MD0
MD1
MD2
MD3
+12.5 V
+6 V
H
L
H
L
Zero-clear program memory address
L
H
H
H
Write mode
L
L
H
H
Verify mode
H
X
H
H
Program inhibit mode
X: L or H
29
µPD75P0076
8.2 Steps in Program Memory Write Operation
High-speed program memory write can be executed via the following steps.
(1) Pull down unused pins to VSS via resistors. Set the X1 pin to low.
(2) Apply +5 V to the VDD and VPP pins.
(3) Wait 10 µs.
(4) Zero-clear mode for program memory addresses.
(5) Apply +6 V to VDD and +12.5 V to VPP.
(6) Write data using 1-ms write mode.
(7) Verify mode. If write is verified, go to step (8) and if write is not verified, go back to steps (6) to (7).
(8) X [= number of write operations from steps (6) to (7)] x 1 ms additional write
(9) 4 pulse inputs to the X1 pin updates (increments +1) the program memory address.
(10) Repeat steps (6) to (9) until the last address is completed.
(11) Zero-clear mode for program memory addresses.
(12) Apply +5 V to the VDD and VPP pins.
(13) Power supply OFF
The following diagram illustrates steps (2) to (9).
X repetitions
Write
Verify
Additional
write
VPP
VPP
VDD
VDD + 1
VDD
VDD
X1
D0/P40-D3/P43
D4/P50-D7/P53
MD0/P30
MD1/P31
MD2/P32
MD3/P33
30
Data input
Data output
Data input
Address
increment
µPD75P0076
8.3 Steps in Program Memory Read Operation
The µPD75P0076 can read out the program memory contents via the following steps.
(1) Pull down unused pins to VSS via resistors. Set the X1 pin to low.
(2) Apply +5 V to the VDD and VPP pins.
(3) Wait 10 µs.
(4) Zero-clear mode for program memory addresses.
(5) Apply +6 V to VDD and +12.5 V to VPP.
(6) Verify mode. When a clock pulse is input to the X1 pin, data is output sequentially to one address at a time based
on a cycle of four pulse inputs.
(7) Zero-clear mode for program memory addresses.
(8) Apply +5 V to the VDD and VPP pins.
(9) Power supply OFF
The following diagram illustrates steps (2) to (7).
VPP
VPP
VDD
VDD + 1
VDD
VDD
X1
D0/P40-D3/P43
D4/P50-D7/P53
Data output
Data output
MD0/P30
MD1/P31
“L”
MD2/P32
MD3/P33
31
µPD75P0076
8.4 One-Time PROM Screening
Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends
the screening process, that is, after the required data is written to the PROM and the PROM is stored under the hightemperature conditions shown below, the PROM should be verified.
32
Storage temperature
Storage time
125 ˚C
24 hours
µPD75P0076
9. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25˚C)
Parameter
Symbol
Test Conditions
Rating
Unit
Power supply voltage
V DD
–0.3 to +7.0
V
PROM power supply
V PP
–0.3 to +13.5
V
–0.3 to VDD +0.3
V
–0.3 to +14
V
–0.3 to VDD +0.3
V
Per pin
–10
mA
Total of all pins
–30
mA
Per pin
30
mA
Total of all pins
220
mA
voltage
Input voltage
V I1
Except ports 4, 5
V I2
Ports 4, 5 (N-ch open drain)
Output voltage
VO
Output current high
IOH
Output current low
I OL
Operating ambient
temperature
TA
–40 to +85
˚C
Storage temperature
T stg
–65 to +150
˚C
Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the reliability of the
product may be impaired. The absolute maximum ratings are values that may physically damage the
products. Be sure to use the products within the ratings.
CAPACITANCE (TA = 25˚C,VDD = 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
CIN
f = 1 MHz
15
pF
Output capacitance
COUT
Unmeasured pins returned to 0 V.
15
pF
I/O capacitance
CIO
15
pF
33
µPD75P0076
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Recommended constant
Ceramic
X1
Parameter
Oscillation
X2
resonator
frequency (fx)
C1
Crystal
C2
X1
C2
After V DD reaches oscil-
stabilization timeNote 3
lation voltage range MIN.
1.0
Oscillation
V DD = 4.5 to 5.5 V
X1 input
X1
clock
X2
frequency (fx)
MAX.
Unit
6.0Note 2
MHz
4
ms
6.0Note 2
MHz
10
ms
Note 1
stabilization timeNote 3
External
TYP.
Note 1
Oscillation
frequency (fx)
MIN.
1.0
Oscillation
X2
resonator
C1
Test conditions
30
1.0
6.0Note 2
MHz
83.3
500
ns
Note 1
X1 input
high-/low-level width
(t XH, tXL)
Notes 1. The oscillation frequency and X1 input frequency indicate characteristics of the oscillator only. For the
instruction execution time, refer to AC Characteristics.
2. When the power supply voltage is 1.8 V ≤ VDD < 2.7 V and the oscillation frequency is 4.19 MHz < fx ≤ 6.0 MHz,
setting the processor clock control register (PCC) to 0011 results in 1 machine cycle being less than the required
0.95 µs. Therefore, set PCC to a value other than 0011.
3. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing the STOP
mode.
Caution When using the main system clock oscillator, wiring in the area enclosed with the dotted line should
be carried out as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as VSS.
• Do not ground it to the ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
34
µPD75P0076
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (T A = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Resonator
Recommended constant
Crystal
XT1
C3
Test conditions
Oscillation
XT2
resonator
Parameter
R
frequency (fXT)
C4
Oscillation
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.0
2
s
Note 1
V DD = 4.5 to 5.5 V
stabilization timeNote 2
External
XT1 input frequency
XT1
clock
XT2
(f XT)
10
32
100
kHz
5
15
µs
Note 1
XT1 input high-/low-level
width (t XTH, t XTL)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD.
Caution
When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should
be carried out as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as VSS.
• Do not ground it to the ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
The subsystem clock oscillator is designed as a low amplification circuit to provide low consumption
current, causing misoperation by noise more frequently than the main system clock oscillation
circuit. Special care should therefore be taken for wiring method when the subsystem clock is used.
35
µPD75P0076
RECOMMENDED OSCILLATION CIRCUIT CONSTANTS
CERAMIC RESONATOR (TA = –20 to +80 ˚C)
Manufacturer
Product Name
Frequency
(MHz)
Oscillation Circuit
Constants (pF)
Oscillation Voltage
Range (VDD)
C1
C2
MIN.
MAX.
5.5
Murata Mfg.
CSB1000JNote
1.0
100
100
2.2
Co., Ltd.
CSA2.00MG040
2.0
100
100
2.0
—
—
4.0
30
30
—
—
4.19
30
30
—
—
30
30
CST2.00MG040
CSA4.00MG
CST4.00MGW
CSA4.19MG
CST4.19MGW
CSA6.00MG
6.0
CST6.00MGW
—
—
CSA6.00MGU
30
30
CST6.00MGWU
—
—
Remarks
Rd = 5.6 KΩ
—
With on-chip capacitor
1.8
—
With on-chip capacitor
—
With on-chip capacitor
2.6
—
With on-chip capacitor
1.8
—
With on-chip capacitor
Note When the CSB1000J (1.0 MHz) manufactured by Murata Mfg. is used as a ceramic resonator, a limiting resistor
(Rd = 5.6 kΩ) is required (see the figure below). Other recommended resonators do not require such a limiting
resistor.
X2
X1
CSB1000J
C1
Rd
C2
Caution The oscillation circuit constants and oscillation voltage range only indicate the conditions under which
the circuit can oscillate stably, and do not guarantee the oscillation frequency accuracy. If oscillation
frequency accuracy is required in the actual circuit, it is necessary to adjust oscillation frequencies in
the actual circuit, and you should consult directly with the manufacturer of the resonator used.
36
µPD75P0076
DC CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
Output current low
Input voltage high
Symbol
IOL
VIH1
VIH2
VIH3
Input voltage low
Test conditions
MAX.
Unit
Per pin
15
mA
Total of all pins
150
mA
TYP.
2.7 ≤ VDD ≤ 5.5 V
0.7VDD
V DD
V
1.8 ≤ VDD < 2.7 V
0.9VDD
V DD
V
2.7 ≤ VDD ≤ 5.5 V
0.8VDD
V DD
V
1.8 ≤ VDD < 2.7 V
0.9VDD
V DD
V
Ports 4, 5
2.7 ≤ VDD ≤ 5.5 V
0.7VDD
13
V
(N-ch open-drain)
1.8 ≤ VDD < 2.7 V
0.9VDD
13
V
VDD – 0.1
V DD
V
2.7 ≤ VDD ≤ 5.5 V
0
0.3V DD
V
1.8 ≤ VDD < 2.7 V
0
0.1V DD
V
2.7 ≤ VDD ≤ 5.5 V
0
0.2V DD
V
1.8 ≤ VDD < 2.7 V
0
0.1V DD
V
0
0.1
V
Ports 2, 3, and 11
Ports 0, 1, 6, RESET
VIH4
X1, XT1
VIL1
Ports 2-5, 11
VIL2
MIN.
Ports 0, 1, 6, RESET
VIL3
X1, XT1
Output voltage high
VOH
SCK, SO, Ports 2, 3, 6
Output voltage low
VOL1
SCK, SO, Ports 2-6
IOH = –1.0 mA
VDD – 0.5
IOL = 15 mA,
V
0.2
2.0
V
0.4
V
0.2VDD
V
3
µA
X1, XT1
20
µA
VDD = 4.5 to 5.5 V
IOL = 1.6 mA
VOL2
SB0, SB1
When N-ch open-drain
pull-up resistor ≥ 1 kΩ
Input leakage
ILIH1
VIN = V DD
Pins other than X1, XT1
current high
ILIH2
ILIH3
VIN = 13 V
Ports 4, 5 (N-ch open-drain)
20
µA
Input leakage
ILIL1
VIN = 0 V
Ports 4, 5, pins other than X1, XT1
–3
µA
current low
ILIL2
X1, XT1
–20
µA
Ports 4, 5 (N-ch open-drain)
When input instruction is not executed
–3
µA
Ports 4, 5 (N-ch open-
–30
µA
ILIL3
drain) When input
VDD = 5.0 V
–10
–27
µA
instruction is executed
VDD = 3.0 V
–3
–8
µA
3
µA
20
µA
–3
µA
200
kΩ
Output leakage
ILOH1
VOUT = VDD
SCK, SO/SB0, SB1, Ports 2, 3, 6
current high
ILOH2
VOUT = 13 V
Ports 4, 5 (N-ch open-drain)
Output leakage
current low
ILOL
VOUT = 0 V
On-chip pull-up resistor
RL
VIN = 0 V
Ports 0-3, 6 (Excluding P00 pin)
50
100
37
µPD75P0076
DC CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
Supply current Note 1
Symbol
I DD1
I DD2
Test conditions
MIN.
TYP.
MAX.
Unit
6.0 MHzNote 2
VDD = 5.0 V ± 10%Note 3
3.4
10.2
mA
Crystal oscillation
VDD = 3.0 V ± 10%
0.8
2.4
mA
C1 = C2 = 22 pF
HALT mode
VDD = 5.0 V ± 10%
0.9
2.7
mA
VDD = 3.0 V ± 10%
0.5
1.5
mA
Note 4
4.19 MHzNote 2
VDD = 5.0 V ± 10%Note 3
2.7
7.4
mA
Crystal oscillation
VDD = 3.0 V ± 10%
0.6
1.8
mA
I DD2
C1 = C2 = 22 pF
HALT mode
VDD = 5.0 V ± 10%
0.8
2.4
mA
VDD = 3.0 V ± 10%
0.4
1.2
mA
I DD3
Note 5
VDD = 3.0 V ± 10%
42
126
µA
VDD = 2.0 V ± 10%
23
69
µA
VDD = 3.0 V, TA = 25˚C
42
84
µA
VDD = 3.0 V ± 10%
40
120
µA
VDD = 3.0 V, TA = 25˚C
40
80
µA
Low-
VDD = 3.0 V ± 10%
8
24
µA
voltage
VDD = 2.0 V ± 10%
4
12
µA
modeNote 6 VDD = 3.0 V, TA = 25˚C
8
16
µA
Low current VDD = 3.0 V ± 10%
7
21
µA
consumption VDD = 3.0 V,
7
14
µA
VDD = 5.0 V ± 10%
0.05
10
µA
VDD = 3.0 V
0.02
5.0
µA
0.02
3.0
µA
I DD1
32.768 kHz
Crystal oscillation
Low-voltage
mode
Note 6
Low current consumption mode
I DD4
Note 7
HALT mode
Note 4
modeNote 7 T A = 25˚C
I DD5
XT1 = 0 V
STOP mode
Note 8
± 10%
TA = 25˚C
Notes 1. Not including currents flowing in on-chip pull-up resistors.
2. Including oscillation of the subsystem clock.
3. When the processor clock control register (PCC) is set to 0011 and the device is operated in the high-speed
mode.
4. When PCC is set to 0000 and the device is operated in the low-speed mode.
5. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem clock,
with main system clock oscillation stopped.
6. When the sub-oscillation circuit control register (SOS) is set to 0000.
7. When SOS is set to 0010.
8. When SOS is set to 00×1, the feedback resistors of the sub-oscillation circuit is cutoff. (×: don’t care)
38
µPD75P0076
AC CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
MAX.
Unit
0.67
64
µs
main system clock
0.95
64
µs
(Minimum instruction execution
Operating on
114
125
µs
time = 1 machine cycle)
subsystem clock
0
1.0
MHz
0
275
kHz
CPU clock cycle
time
t CY
Note 1
TI0, TI1 input
f TI
Test conditions
Operating on
MIN.
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
frequency
TI0, TI1 input
t TIH, t TIL
µs
1.8
µs
IM02 = 0
Note 2
µs
IM02 = 1
10
µs
INT1, 2, 4
10
µs
KR0 to KR3
10
µs
10
µs
tINTH, t INTL INT0
low-level width
RESET low-level width
122
0.48
VDD = 2.7 to 5.5 V
high-/low-level width
Interrupt input high-/
TYP.
tRSL
Notes 1. The cycle time (minimum instruction
tCY vs VDD
(At main system clock operation)
execution time) of the CPU clock (Φ)
is determined by the oscillation
64
60
frequency of the connected resonator
(and external clock), the system clock
6
control register (SCC) and the
(PCC).
The figure at the right
indicates the cycle time tCY versus
supply voltage VDD characteristic with
the main system clock operating.
2. 2tCY or 128/fx is set by setting the
5
Cycle Time tCY [ µ s]
processor clock control register
Guaranteed Operation
Range
4
3
2
interrupt mode register (IM0).
1
0.5
0
1
2
3
4
5
6
Supply Voltage VDD [V]
39
µPD75P0076
SERIAL TRANSFER OPERATION
2-Wire and 3-Wire Serial I/O Mode (SCK...Internal clock output): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high-/low-level
Symbol
t KCY1
t KL1, t KH1
Test conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
SI Note 1 setup time
t SIK1
MIN.
SI
hold time
t KSI1
t KSO1
3800
ns
tKCY1/2–50
ns
tKCY1/2–150
ns
150
ns
500
ns
400
ns
600
ns
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
RL = 1 kΩ,
VDD = 2.7 to 5.5 V
CL = 100 pFNote 2
delay time
Unit
ns
(from SCK↑)
SCK↓→SONote 1 output
MAX.
1300
(to SCK↑)
Note 1
TYP.
0
250
ns
0
1000
ns
Notes 1. In 2-wire serial I/O mode, read SB0 or SB1 instead.
2. RL and CL are the load resistance and load capacitance of the SO output lines.
2-Wire and 3-Wire Serial I/O Mode (SCK...External clock input): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high-/low-level
Symbol
t KCY2
t KL2, tKH2
Test conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
SI
Note 1
setup time
t SIK2
VDD = 2.7 to 5.5 V
(to SCK↑)
SI Note 1 hold time
t KSI2
VDD = 2.7 to 5.5 V
(from SCK↑)
SCK↓→SONote 1 output
delay time
t KSO2
RL = 1 kΩ,
VDD = 2.7 to 5.5 V
CL = 100 pFNote 2
Notes 1. In 2-wire serial I/O mode, read SB0 or SB1 instead.
2. RL and CL are the load resistance and load capacitance of the SO output lines.
40
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
150
ns
400
ns
600
ns
0
300
ns
0
1000
ns
µPD75P0076
A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V, 1.8 V ≤ AVREF ≤ VDD)
Parameter
Symbol
Test conditions
Resolution
Absolute accuracy
Note 1
VDD = AVREF
MIN.
TYP.
MAX.
Unit
8
8
8
bit
1.5
LSB
3
LSB
2.7 ≤ VDD
1.8 V ≤ VDD < 2.7 V
VDD ≠ AVREF
3
LSB
tCONV
168/fX
µs
Sampling time
tSAMP
44/fX
µs
Analog input voltage
VIAN
AVREF
V
Conversion timeNote 2
Note 3
AVSS
Analog input impedance
RAN
1000
AVREF current
IREF
0.25
MΩ
2.0
mA
Notes 1. Absolute accuracy excluding quantization error (±1/2 LSB).
2. Time after execution of conversion start instruction until completion of conversion (EOC = 1) (40.1 µs: in fX =
4.19 MHz operation)
3. Time after conversion start instruction until completion of sampling (10.5 µs: in fX = 4.19 MHz operation)
41
µPD75P0076
AC Timing Test Point (Excluding X1, XT1 Input)
VIH (MIN.)
VIL (MAX.)
VIH (MIN.)
VIL (MAX.)
VOH (MIN.)
VOL (MAX.)
VOH (MIN.)
VOL (MAX.)
Clock Timing
1/fX
tXL
tXH
VDD–0.1 V
0.1 V
X1 Input
1/fXT
tXTL
tXTH
VDD–0.1 V
0.1 V
XT1 Input
TI0, TI1 Timing
1/fTI
tTIL
TI0, TI1
42
tTIH
µPD75P0076
Serial Transfer Timing
3-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
SI
tKSI1, 2
Input Data
tKSO1, 2
SO
Output Data
2-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
tKSI1, 2
SB0, 1
tKSO1, 2
43
µPD75P0076
Interrupt input timing
tINTL
INT0, 1, 2, 4
KR0 to 3
RESET input timing
tRSL
RESET
44
tINTH
µPD75P0076
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
(TA = –40 to +85˚C)
Parameter
Symbol
Release signal set time
tSREL
Oscillation stabilization
tWAIT
Test conditions
MIN.
TYP.
wait timeNote 1
Release by interrupt request
Unit
µs
0
Release by RESET
MAX.
215/fX
ms
Note 2
ms
Notes 1. The oscillation stabilization wait time is the time during which the CPU operation is stopped to prevent unstable
operation at the oscillation start.
2. Depends on the basic interval timer mode register (BTM) settings (See the table below).
BTM3
—
—
—
—
BTM2
0
0
1
1
BTM1
0
1
0
1
BTM0
0
1
1
1
Wait time
220/fx
217/fx
215/fx
213/fx
fx = at 4.19 MHz
(approx. 250 ms)
(approx. 31.3 ms)
(approx. 7.81 ms)
(approx. 1.95 ms)
220/fx
217/fx
215/fx
213/fx
fx = at 6.0 MHz
(approx. 175 ms)
(approx. 21.8 ms)
(approx. 5.46 ms)
(approx. 1.37 ms)
45
µPD75P0076
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
46
µPD75P0076
DC PROGRAMMING CHARACTERISTICS (TA = 25 ± 5˚C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V)
Parameter
Symbol
Input voltage high
Input voltage low
Test conditions
MAX.
Unit
0.7V DD
V DD
V
V DD–0.5
V DD
V
Except X1, X2
0
0.3VDD
V
0
0.4
V
10
µA
VIH1
Except X1, X2
VIH2
X1, X2
VIL1
VIL2
X1, X2
Input leakage current
ILI
VIN = VIL or V IH
Output voltage high
VOH
IOH = –1 mA
Output voltage low
V OL
IOL = 1.6 mA
VDD power supply current
IDD
VPP power supply current
IPP
MIN.
TYP.
V DD–1.0
V
MD0 = VIL, MD1 = V IH
0.4
V
30
mA
30
mA
Cautions 1. Avoid exceeding +13.5 V for VPP including the overshoot.
2. V DD must be applied before VPP, and cut after VPP.
AC PROGRAMMING CHARACTERISTICS (TA = 25 ± 5˚C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V)
Parameter
Symbol
Note 1
Test conditions
MIN.
TYP.
MAX.
Unit
t AS
tAS
2
µs
MD1 setup time (to MD0↓)
t M1S
tOES
2
µs
Data setup time (to MD0↓)
t DS
tDS
2
µs
t AH
tAH
2
µs
t DH
tDH
2
µs
Address setup time
Address hold time
Note 2
Note 2
(to MD0↓)
(from MD0↑)
Data hold time (from MD0↑)
MD0↑→data output float delay time
tDF
tDF
0
VPP setup time (to MD3↑)
t VPS
tVPS
2
130
µs
VDD setup time (to MD3↑)
t VDS
tVCS
2
µs
Initial program pulse width
tPW
tPW
0.95
Additional program pulse width
t OPW
tOPW
0.95
MD0 setup time (to MD1↑)
t M0S
tCES
2
MD0↓→data output delay time
t DV
tDV
MD0 = MD1 = VIL
MD1 hold time (from MD0↑)
t M1H
tOEH
tM1H + t M1R ≥ 50 µs
2
µs
MD1 recovery time (from MD0↓)
t M1R
tOR
2
µs
Program counter reset time
t PCR
–
10
µs
X1 input high-/low-level width
tXH, tXL
–
0.125
X1 input frequency
fX
–
Initial mode set time
tI
–
2
µs
MD3 setup time (to MD1↑)
t M3S
–
2
µs
MD3 hold time (from MD1↓)
t M3H
–
2
µs
MD3 setup time (to MD0↓)
t M3SR
–
During program memory read
2
µs
1.0
1.05
ms
21.0
ms
µs
1
Address
→data output delay time
t DAD
tACC
During program memory read
Address
Note 2
→data output hold time
2
t HAD
tOH
During program memory read
0
MD3 hold time (from MD0↑)
t M3HR
–
During program memory read
2
MD3↓→data output float delay time
t DFR
–
During program memory read
µs
µs
4.19
Note 2
ns
130
MHz
µs
ns
µs
2
µs
Notes1. Corresponding symbol of µPD27C256A
2. The internal address signal is incremented by 1 at the rising edge of the fourth X1 input and is not
connected to the pin.
47
µPD75P0076
Program Memory Write Timing
tVPS
VPP
VPP
VDD
VDD
VDD+1
VDD
tVDS
tXH
X1
D0/P40-D3/P43
D4/P50-D7/P53
Data input
Data output
tDS
tI
tDS
tDH
tDV
tXL
Data input
Data input
tDH
tDF
tAH
tAS
MD0/P30
tPW
tM1R
tM0S
tOPW
MD1/P31
tPCR
tM1S
tM1H
MD2/P32
tM3S
tM3H
MD3/P33
Program Memory Read Timing
tVPS
VPP
VPP
VDD
VDD
VDD+1
VDD
tVDS
tXH
X1
tXL
D0/P40-D3/P43
D4/P50-D7/P53
tDAD
tHAD
Data output
Data output
tDV
tI
MD0/P30
MD1/P31
tPCR
MD2/P32
tM3SR
MD3/P33
48
tDFR
tM3HR
µPD75P0076
10. CHARACTERISTICS CURVES (REFERENCE VALUES)
IDD vs VDD (Main System Clock: 6.0-MHz Crystal Resonator)
(TA = 25°C)
10
5.0
PCC = 0011
PCC = 0010
PCC = 0001
PCC = 0000
1.0
Main system clock
HALT mode + 32-kHz oscillation
Supply Current IDD (mA)
0.5
0.1
Subsystem clock operation
mode (SOS.1 = 0)
0.05
Subsystem clock HALT
mode (SOS.1 = 0) and
main system clock STOP mode
+ 32-kHz oscillation
(SOS.1 = 0)
Subsystem clock HALT mode
(SOS.1 = 1) and main
system clock STOP mode
+ 32-kHz oscillation
(SOS.1 = 1)
0.01
0.005
X1
22 pF
0.001
0
1
2
3
4
5
X2 XT1
XT2
Crystal resonator
6.0 MHz
Crystal resonator
32.768 kHz
330 kΩ
22 pF
33 pF
33 pF
6
7
8
Supply Voltage VDD (V)
49
µPD75P0076
IDD vs VDD (Main System Clock: 4.19-MHz Crystal Resonator)
(TA = 25°C)
10
5.0
PCC = 0011
PCC = 0010
PCC = 0001
1.0
PCC = 0000
Main system clock
HALT mode + 32-kHz oscillation
Supply Current IDD (mA)
0.5
0.1
Subsystem clock operation
mode (SOS.1 = 0)
0.05
Subsystem clock HALT mode
(SOS.1 = 0) and main sysyem
clock STOP mode + 32-kHz
oscillation (SOS.1 = 0)
Subsystem clock HALT
mode (SOS.1 = 1) and
main system clock STOP
mode + 32-kHz oscillation
(SOS.1 = 1)
0.01
0.005
X1
X2 XT1
Crystal resonator
32.768 kHz 330 kΩ
4.19 MHz
22 pF
0.001
0
1
2
3
4
Supply Voltage VDD (V)
50
5
XT2
Crystal resonator
22 pF
33 pF
6
33 pF
7
8
µPD75P0076
11. PACKAGE DRAWINGS
42PIN PLASTIC SHRINK DIP (600 mil)
42
22
1
21
A
K
H
G
J
I
L
F
B
D
N
R
M
C
M
NOTES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
2) Item "K" to center of leads when formed parallel.
ITEM
MILLIMETERS
INCHES
A
39.13 MAX.
1.541 MAX.
B
1.78 MAX.
0.070 MAX.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.50±0.10
0.020 +0.004
–0.005
F
0.9 MIN.
0.035 MIN.
G
3.2±0.3
0.126±0.012
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
J
5.08 MAX.
0.200 MAX.
K
L
15.24 (T.P.)
13.2
0.600 (T.P.)
0.520
M
0.25 +0.10
–0.05
0.010 +0.004
–0.003
N
0.17
0.007
R
0~15°
0~15°
P42C-70-600A-1
51
µPD75P0076
42 PIN PLASTIC SHRINK SOP (375 mil)
42
22
3° +7°
–3°
detail of lead end
1
21
A
H
J
E
K
F
G
I
N
C
D
M
B
L
M
S42GT-80-375B-1
NOTE
Each lead centerline is located within 0.10
mm (0.004 inch) of its true position (T.P.) at
maximum material condition.
52
ITEM
MILLIMETERS
INCHES
A
18.16 MAX.
0.715 MAX.
B
1.13 MAX.
0.044 MAX.
C
0.8 (T.P.)
0.031 (T.P.)
D
0.35 +0.10
–0.05
0.014 +0.004
–0.003
E
0.125 ±0.075
0.005 ±0.003
F
2.9 MAX.
0.115 MAX.
G
2.5 ±0.2
0.098+0.009
–0.008
H
10.3 ±0.3
0.406+0.012
–0.013
I
7.15 ±0.2
0.281+0.009
–0.008
J
1.6 ±0.2
0.063 ±0.008
K
0.15 +0.10
–0.05
0.006 +0.004
–0.002
L
0.8 ±0.2
0.031 +0.009
–0.008
M
0.10
0.004
N
0.10
0.004
µPD75P0076
12. RECOMMENDED SOLDERING CONDITIONS
The µ PD75P0076 should be soldered and mounted under the conditions recommended in the table below.
For details of recommended soldering conditions, refer to the information document “Semiconductor Device
Mounting Technology Manual” (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC Sales representative.
Table 12-1. Surface Mounting Type Soldering Conditions
µPD75P0076GT: 42-pin plastic shrink SOP (375 mil, 0.8 mm pitch)
Soldering
Method
Soldering Conditions
Symbol
Infrared reflow
Package peak temperature: 235˚C, Time: 30 seconds or less (at 210˚C or higher),
Number of reflow processes: Twice or less
IR35-00-2
VPS
Package peak temperature: 215˚C, Time: 40 seconds or less (at 200˚C or higher),
VP15-00-2
Number of reflow processes: Twice or less
Wave soldering
Solder temperature: 260˚C or below, Time: 10 seconds or less, Number of flow
process: 1, Preheating temperature: 120˚C or below (Package surface temperature)
Partial heating
Pin temperature: 300˚C or below, Time : 3 seconds or less (per device side)
Caution
WS60-00-1
—
Use of more than one soldering method should be avoided (except for partial heating).
Table 12-2. Insertion Type Soldering Conditions
µPD75P0076CU: 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)
Soldering Method
Soldering Conditions
Wave soldering (pins only)
Solder bath temperature: 260 ˚C or less, Time: 10 seconds or less
Partial heating
Pin temperature: 300 ˚C or below, Time: 3 seconds or less (per device side)
Caution
Ensure that the application of wave soldering is limited to the pins and no solder touches the
main unit directly.
53
µPD75P0076
APPENDIX A
DIFFERENCES AMONG µPD75068, 750068 AND 75P0076
Parameter
Program memory
µPD75068
µPD750068
µPD75P0076
Mask ROM
0000H to 1F7FH
(8064 x 8 bits)
Mask ROM
0000H to 1FFFH
(8192 x 8 bits)
One-time PROM
0000H to 3FFFH
(16384 x 8 bits)
Data memory
000H to 1FFH
(512 x 4 bits)
CPU
75X Standard CPU
75XL CPU
General-purpose register
4 bits x 8 or 8 bits x 4
(4 bits x 8 or 8 bits x 4) x 4 banks
Instruction
execution
time
When main system
clock is selected
0.95, 1.91, 15.3 µs
(during 4.19-MHz operation)
• 0.67, 1.33, 2.67, 10.7 µs (during 6.0-MHz operation)
• 0.95, 1.91, 3.81, 15.3 µ s (during 4.19-MHz operation)
When subsystem
clock is selected
122 µs (during 32.768-kHz operation)
CMOS input
12 (Connections of on-chip pull-up resistor specified by software: 7)
CMOS input/output
12 (Connections of on-chip pull-up resistor specified by software)
N-ch open-drain
input/output
8 (on-chip pull-up resistor
specified by mask option)
Withstand voltage is 10 V
Total
32
I/O port
8 (no mask option)
Withstand voltage is 13 V
Timer
3
•
•
•
A/D converter
• 8-bit resolution x 8 channels
(successive approximation)
• Can operate at the voltage
from V DD = 2.7 V
• 8-bit resolution x 8 channels
(successive approximation)
• Can operate at the voltage from V DD = 1.8 V
Clock output (PCL)
Φ, 524, 262, 65.5 kHz
(Main system clock:
during 4.19-MHz operation)
• Φ, 1.05 MHz, 262 kHz, 65.5 kHz
(Main system clock: during 4.19-MHz operation)
• Φ, 1.5 MHz, 375 kHz, 93.8 kHz
(Main system clock: during 6.0-MHz operation)
Buzzer output (BUZ)
2, 4, 32 kHz
(Main system clock:
during 4.19-MHz operation
or subsystem clock: during
32.768-kHz operation)
• 2, 4, 32 kHz
(Main system clock: during 4.19-MHz operation or
subsystem clock: during 32.768-kHz operation)
• 2.93, 5.86, 46.9 kHz
(Main system clock: during 6.0-MHz operation)
Serial interface
3 modes supported
• 3-wire serial I/O mode
...MSB/LSB first selectable
• 2-wire serial I/O mode
• SBI mode
2 modes supported
• 3-wire serial I/O mode...MSB/LSB first selectable
• 2-wire serial I/O mode
Vectored interrupt
3 external, 3 internal
3 external, 4 internal
Test inputs
1 external, 1 internal
Power supply voltage
V DD = 2.7 to 6.0 V
Operating ambient temperature
TA = –40 to +85 ˚C
Package
• 42-pin plastic shrink DIP
(600 mil)
• 44-pin plastic QFP
(10 x 10 mm)
Note Under development
54
channels
8-bit timer/event counter
8-bit basic interval timer
Watch timer
8 (on-chip pull-up resistor
specified by mask option)
Withstand voltage is 13 V
4 channels
• 8-bit timer/event counter 0 (watch timer output added)
• 8-bit timer/event counter 1 (can be used as a 16-bit timer/
event counter)
• 8-bit basic interval timer/watchdog timer
• Watch timer
VDD = 1.8 to 5.5 V
• 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
• 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
µPD75P0076
APPENDIX B
DEVELOPMENT TOOLS
The following development tools are provided for system development using the µPD75P0076. In the 75XL series, the
common relocatable assembler of the series is used together with device files according to the product.
RA75X relocatable assembler
Host machine
Order code (Part No.)
OS
PC-9800 Series
MS-DOS
Supply Medium
TM
Ver.3.30 to
Ver.6.2Note
Device file
3.5" 2HD
µS5A13RA75X
5" 2HD
µS5A10RA75X
IBM PC/ATTM
Refer to OS for
3.5" 2HC
µS7B13RA75X
or compatible
IBM PCs
5" 2HC
µS7B10RA75X
Host machine
PC-9800 Series
Order code (Part No.)
OS
Supply Medium
MS-DOS
3.5" 2HD
µS5A13DF750068
5" 2HD
µS5A10DF750068
Ver.3.30 to
Ver.6.2Note
IBM PC/AT
Refer to OS for
3.5" 2HC
µS7B13DF750068
or compatible
IBM PCs
5" 2HC
µS7B10DF750068
Note Ver. 5.00 or later include a task swapping function, but this software is not able to use that function.
Remark
Operation of the assembler and device file is guaranteed only when using the host machine and OS described
above.
PROM Write Tools
Hardware
Software
PG-1500
This is a PROM programmer which enables you to program a single-chip microcontroller with
on-chip PROM by stand-alone or host machine operation by connecting an attached board and
a programmer adapter (sold separately).
In addition, typical PROMs in capacities ranging from 256 K to 4 M bits can be programmed.
PA-75P0076CU
This is a PROM programmer adapter dedicated for the µPD75P0076CU and 75P0076GT. It
can be used when connected to a PG-1500.
PG-1500 controller
PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500 is
controlled on the host machine.
Host machine
PC-9800 Series
Order code (Part No.)
OS
Supply medium
MS-DOS
3.5" 2HD
µS5A13PG1500
5" 2HD
µS5A10PG1500
Ver.3.30 to
Ver.6.2Note
IBM PC/AT
Refer to OS for
3.5" 2HD
µS7B13PG1500
or compatible
IBM PCs
5" 2HC
µS7B10PG1500
Note Ver. 5.00 or later include a task swapping function, but this software is not able to use that function.
Remark
Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above.
55
µPD75P0076
Debugging Tools
In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the µPD75P0076.
Various system configurations using these in-circuit emulators are listed below.
Hardware
IE-75000-RNote 1
The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during
development of application systems that use 75X or 75XL Series products. For development
of the µPD750068 subseries, the IE-75000-R is used with a separately sold emulation board (IE75300-R-EM) and emulation probe.
These products can be applied for highly efficient debugging when connected to a host machine
and PROM programmer.
The IE-75000-R can include a connected emulation board (IE-75000-R-EM).
IE-75001-R
The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during
development of application systems that use 75X or 75XL Series products. The IE-75001-R is
used with a separately sold emulation board (IE-75300-R-EM) and emulation probe.
These products can be applied for highly efficient debugging when connected to a host machine
and PROM programmer.
IE-75300-R-EM
This is an emulation board for evaluating application systems that use the µPD750068
subseries. It is used in combination with the IE-75000-R or IE-75001-R in-circuit emulator.
EP-750068CU-R
This is an emulation probe for the µPD75P0076CU.
When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.
EP-750068GT-R
This is an emulation probe for the µPD75P0076GT.
EV-9500GT-42
Software
IE control program
When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.
It includes a flexible board (EV-9500GT-42) to facilitate connections with target systems.
This program can control the IE-75000-R or IE-75001-R on a host machine when connected to
the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface.
Host machine
PC-9800 Series
Order code (Part No.)
OS
Supply Medium
MS-DOS
3.5" 2HD
µS5A13IE75X
5" 2HD
µS5A10IE75X
Ver.3.30 to
Ver.6.2Note 2
IBM PC/AT
Refer to OS for
3.5" 2HC
µS7B13IE75X
or compatible
IBM PCs
5" 2HC
µS7B10IE75X
Notes 1. This is a service part provided for maintenance purpose only.
2. Ver. 5.00 or later include a task swapping function, but this software is not able to use that function.
Remarks 1. Operation of the IE control program is guaranteed only when using the host machine and OS described
above.
2. The generic name for the µPD750064, 750066, 750068, and 75P0076 is the µPD750068 subseries.
56
µPD75P0076
OS for IBM PCs
The following operating systems for the IBM PC are supported.
OS
TM
PC DOS
Version
Ver.5.02 to Ver.6.3
J6.1/VNote to J6.3/VNote
MS-DOS
Ver.5.0 to Ver.6.22
5.0/VNote to 6.2/VNote
IBM DOSTM
J5.02/VNote
Note Only the English mode is supported.
Caution Ver 5.0 and above include a task swapping function, but this software is not able to use that function.
57
µPD75P0076
APPENDIX C RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are
not marked as such.
Documents related to device
Document No.
Document Name
English
Japanese
µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Data Sheet
U10165E
µPD75P0076 Data Sheet
This document
U10232J
µPD750068 User’s Manual
U10670E
U10670J
µPD750068 Instruction Table
Note
—
75XL Series Selection Guide
U10165J
IEM-5606
U10453E
U10453J
Note Preliminary product information
Documents related to development tool
Document No.
Document Name
English
Hardware
Software
Japanese
IE-75000-R/IE-75001-R User’s Manual
EEU-1416
EEU-846
IE-75300-R-EM User’s Manual
U11345E
U11354J
EP-750068GT-R User’s Manual
U10950E
U10950J
PG-1500 User’s Manual
EEU-1335
EEU-651
Operation
EEU-1346
EEU-731
Language
EEU-1363
EEU-730
PC-9800 Series
(MS-DOS) base
EEU-1291
EEU-704
IBM PC Series
(PC DOS) base
U10540E
EEU-5008
RA75X Assembler Package User’s Manual
PG-1500 Controller User’s Manual
Other related documents
Document No.
Document Name
English
Japanese
IC Package Manual
C10943X
Semiconductor Device Mounting Technology Manual
C10535E
C10535J
NEC Semiconductor Device Quality Grades
C11531E
C11531J
NEC Semiconductor Device Reliability and Quality Control
C10983E
C10983J
Electrostatic Discharge (ESD) Test
Semiconductor Device Quality Assurance Guide
Microcontroller-related Product Guide —Third Party Products—
—
MEI-1202
—
MEM-539
MEI-603
U11416J
Caution The contents of the documents listed above are subject to change without prior notice to users. Make
sure to use the latest edition when starting design.
58
µPD75P0076
[MEMO]
59
µPD75P0076
NOTES FOR CMOS DEVICES
(1) PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
(2) HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
(3) STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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µPD75P0076
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics (France) S.A.
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
61
µPD75P0076
MS-DOS is a trademark of Microsoft Corporation.
PC DOS, PC/AT, and IBM DOS are trademarks of IBM Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without
governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country
other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5