DATA SHEET MOS INTEGRATED CIRCUIT µPD78P4916 16-BIT SINGLE-CHIP MICROCONTROLLER The µPD78P4916 is one of the µPD784915 subseries in the 78K/IV Series microcontrollers which incorporate a high-speed and high-performance 16-bit CPU. The µPD78P4916 replaces mask ROM with one-time PROM and increases on-chip ROM and RAM capacity compared to the µPD784915. It is suitable for evaluation at system development and for small quantity production. Detailed descriptions of functions are provided in the following user's manuals. Be sure to read these documents when designing. µPD784915 Subseries User’s Manual – Hardware : U10444E 78K/IV Series User's Manual – Instruction : U10905E FEATURES High-speed instruction execution using 16-bit CPU core • Minimum instruction execution time: 250 ns (at 8-MHz internal clock) On-chip high capacity memory • PROM : 62 Kbytes Note • RAM Note : 2048 bytes Note It is possible to change the capacity of the internal PROM and the internal RAM by specifying the internal memory capacity select (IMS) register. ORDERING INFORMATION Part Number Package µPD78P4916GF-3BA 100-pin plastic QFP (14 × 20 mm) The information in this document is subject to change without notice. Document No. U11045EJ1V0DS00 (1st edition) Date Published April 1996 P Printed in Japan The mark * shows major revised points. © 1996 µPD78P4916 78K/IV Series Products 78K/IV Series mPD784915 µ Subseries Subseries High-performance 16-bit CPU core High-speed operation On-chip analog circuit for VCR 78K/I Series µPD78148 Subseries µPD78138 Subseries 2 Enhanced peripheral hardware µPD78P4916 Function List (1/2) Item Function Note Internal PROM capacity 62 Kbytes Internal RAM capacity 2048 bytes Note Operation clock 16 MHz (Internal clock: 8 MHz) Low frequency oscillation mode: 8 MHz (Internal clock: 8 MHz) Low power consumption mode: 32.768 kHz (Subsystem clock) Minimum instruction execution time 250 ns (at 8-MHz internal clock) I/O ports Total: 54 Real-time output port 11 (including 3 outputs each for Pseudo-VSYNC , Head amplifier switch, and Chrominance rotate) Super Timer/counter timer unit Capture register Special circuit for VCR General purpose timer PWM output • • • • Input: 8 I/O: 46 Timer/counter Compare register Capture register TM0 (16-bit) TM1 (16-bit) FRC (22-bit) TM3 (16-bit) UDC (5-bit) EC (8-bit) 3 3 – 2 1 4 – 1 6 1 – – EDV (8-bit) 1 – Generates HSW signal Divides CFG signal Input signal Number of bits Measurement cycle Operation edge CFG DFG HSW VSYNC CTL TREEL SREEL 22 22 16 22 16 22 22 125 ns to 524 ms 125 ns to 524 ms 1 µs to 65.5 ms 125 ns to 524 ms 1 µs to 65.5 ms 125 ns to 524 ms 125 ns to 524 ms ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↓ ↓ ↓ ↓ ↓ VSYNC separator, HSYNC separator VISS detector, Wide-aspect detector Field identifier Head amplifier switch/chrominance rotate output circuit Timer Compare register Capture register TM2 (16-bit) TM4 (16-bit) TM5 (16-bit) 1 1 (Capture/compare) 1 – 1 – • 16-bit precision: 3 channels (Carrier frequency: 62.5 kHz) • 8-bit precision: 3 channels (Carrier frequency: 62.5 kHz) Serial interface 3-wire serial I/O: 2 channels • BUSY/STRB control available (only 1 channel) A/D converter 8-bit resolution × 12 channels, conversion time: 10 µs Note Remark It is possible to change the capacity of the internal PROM and the internal RAM by specifying the internal memory capacity select (IMS) register. 3 µPD78P4916 Function List (2/2) Item * Function Analog unit • • • • • • CTL amplifier RECCTL driver (supports re-write operation) DFG amplifier, DPG comparator, CFG amplifier DPFG separator (Three-value) Reel FG comparator (2 channels) CSYNC comparator Interrupt Programmable 4 levels, vectored interrupt, macro service, context switching External 9 (including NMI) Internal 19 (including software interrupt) Standby function HALT mode/STOP mode Low-power consumption mode: HALT mode Release from STOP mode by NMI pin’s active edge, Watch interrupt (INTW), or INTP1/INTP2/KEY0-KEY4 pins’ input. * Watch function 0.5-sec interval, capable of low-voltage operation (VDD = 2.7 V) Power supply voltage VDD = 2.7 to 5.5 V Package 100-pin plastic QFP (14 × 20 mm) 4 µPD78P4916 Pin Configuration (Top View) (1) Normal Operation Mode • 100-pin plastic QFP (14 × 20 mm) CSYNCIN REEL0IN/INTP3 REEL1IN DFGIN DPGIN CFGCPIN CFGAMPO CFGIN AVDD1 AVSS1 VREFC CTLOUT2 CTLOUT1 CTLIN RECTTL– RECTTL+ CTLDLY AVSS2 ANI11 ANI10 µPD78P4916GF-3BA 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 2 79 3 78 4 77 76 5 75 6 74 7 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 65 16 64 17 18 63 62 19 61 20 21 60 59 22 58 23 57 24 25 56 55 26 27 54 28 53 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ANI9 ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVREF AVDD2 P96 P95/KEY4 P94/KEY3 P93/KEY2 P92/KEY1 P91/KEY0 P90/ENV NMI INTP0 INTP1 INTP2 P00 P01 P02 P03 P04 P05 P06 P80 P57 P56 P55 P54 P53 P52 P51 P50 VSS VDD P47 P46 P45 P44 P43 P42 P41 P40 P07 P64 P65/HWIN P66/PWM4 P67/PWM5 P60/STRB/CLO P61/SCK1/BUZ P62/SO1 P63/SI1 PWM0 PWM1 SCK2 SO2 SI2/BUSY VDD XT1 XT2 VSS X2 X1 RESET IC PTO02 PTO01 PTO00 P87/PTO11 P86/PTO10 P85/PWM3 P84/PWM2 P83/ROTC P82/HASW Caution Connect the IC (Internally Connected) pin to VSS directly. 5 µPD78P4916 ANI0-ANI11 : Analog Input P00-P07 : Port0 AVDD1, AVDD2 : Analog Power Supply P40-P47 : Port4 AVSS1 , AVSS2 : Analog Ground P50-P57 : Port5 AVREF : Analog Reference Voltage P60-P67 : Port6 BUSY : Serial Busy P70-P77 : Port7 BUZ : Buzzer Output P80, P82-P87 : Port8 CFGAMPO : Capstan FG Amplifier Output P90-P96 : Port9 CFGCPIN : Capstan FG Capacitor Input PTO00-PTO02, : Programmable Timer Output CFGIN : Analog Unit Input PTO10, PTO11 CLO : Clock Output PWM0 - PWM5 CSYNCIN : Analog Unit Input RECCTL+, RECCTL– : RECCTL Output/PBCLT Input : Pulse Width Modulation Output CTLDLY : Control Delay Input REEL0IN, REEL1IN : Analog Unit Input CTLIN : CTL Amplifier Input Capacitor RESET : Reset CTLOUT1, CTLOUT2 : CTL Amplifier Output ROTC : Chrominance Rotate Output DFGIN : Analog Unit Input SCK1, SCK2 : Serial Clock DPGIN : Analog Unit Input SI1, SI2 : Serial Input ENV : Envelope Input SO1, SO2 : Serial Output HASW : Head Amplifier Switch Output STRB : Serial Strobe HWIN : Hardware Timer External Input VDD : Power Supply IC : Internally Connected VREFC : Reference Amplifier Capacitor INTP0-INTP3 : Interrupt From Peripherals Vss : Ground KEY0-KEY4 : Key Return X1, X2 : Crystal (Main System Clock) NMI : Nonmaskable Interrupt XT1, XT2 : Crystal (Subsystem Clock) 6 µPD78P4916 (2) PROM Programming Mode • 100-pin plastic QFP (14 × 20 mm) OE CE PGM (L) OPEN (L) VDD VSS OPEN VSS OPEN VSS RESET IC/VPP (L) (L) OPEN VSS 10099 98 97 9695 94 93 92 9190 89 88 87 8685 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 11 70 12 69 68 13 14 67 15 66 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 24 57 56 25 55 26 54 27 53 28 29 52 30 51 31 32 33 34 3536 37 38 39 4041 42 43 44 4546 47 48 49 50 (L) VDD (L) A9 (L) D0 D1 D2 D3 D4 D5 D6 (L) A15 A14 A13 A12 A11 A10 A16 A8 VSS VDD A7 A6 A5 A4 A3 A2 A1 A0 D7 (L) OPEN OPEN (L) OPEN (L) VDD VSS OPEN (L) µPD78P4916GF-3BA Cautions (L) VSS : Connect to VSS via pull-down resistors individually. : Connect to ground. OPEN : Leave this pin unconnected. RESET : Apply low level. A0 - A16 : Address Bus RESET : Reset D0 - D7 : Data Bus VDD : Power Supply CE : Chip Enable VPP : Programming Power Supply OE : Output Enable VSS : Ground PGM : Program 7 µPD78P4916 Internal Block Diagram NMI INTP0 INTP3 Interrupt Control PWM0 PWM5 PTO00 PTO02 System Control Super Timer Unit CE OE PGM VPP 78K/IV 16-bit CPU Core (RAM 512 bytes) Clock Output CLO Buzzer Output BUZ Key Input SI1 Serial Interface 1 SCK1 SI2/BUSY SO2 SCK2 STRB 8 Serial Interface 2 Used in PROM programming mode KEY0 - KEY4 P00 - P07 Analog Unit & A/D Converter Real-Time Output Port P80, P82, P83 ANI0 - ANI11 SO1 D0 - D7 A0 - A16 PTO10, PTO11 VREFC REEL0IN REEL1IN CSYNCIN DFGIN DPGIN CFGIN CFGAMPO CFGCPIN CTLOUT1 CTLOUT2 CTLIN RECCTL+ RECCTL– CTLDLY AVDD1, AVDD2 AVSS1, AVSS2 AVREF VDD VSS X1 X2 XT1 XT2 RESET RAM 1536 bytes ROM 62 Kbytes Port0 P00 - P07 Port4 P40 - P47 Port5 P50 - P57 Port6 P60 - P67 Port7 P70 - P77 Port8 P80, P82 - P87 Port9 P90 - P96 µPD78P4916 System Configuration Example • Camcorder µ PD78P4916 DFG DPG DFGIN DPGIN Key matrix PORT PORT Drum motor M Driver PWM0 CFG PORT SCK1 SI1 SO1 CFGIN INTP0 Capstan motor M Driver PWM1 Camera block RECCTL+ CTL head RECCTL– Loading motor M Driver INTP0 SCK Microcontroller for camera SO control SI µ PD78356 PORT PORT SCK2 SO2 PWM2 BUSY CS CLK DATA BUSY LCD C/D µ PD7225 PORT LCD display panel Composite sync signal Audio-video signal processor Video head switch Audio head switch Pseudo-vertical sync signal Remote control receive signal Signals from remote controller µ PC2800A CSYNCIN PORT CS P80 STRB CLK DATA BUSY STB INTP2 PORT Mechanical block PTO00 PTO01 X1 X2 16 MHz XT1 OSD µ PD6456 XT2 32.768 kHz 9 µPD78P4916 • Deck-type VCR µ PD78P4916 DFG DPG Drum motor M Driver CFG Capstan motor M Driver CTL head DFGIN DPGIN PORT SCK1 SI1 SO1 PWM0 PWM1 PORT SCK2 SO2 RECCTL+ PORT RECCTL– M Driver PWM2 CSYNCIN PTO01 P80 Reel FG0 Key matrix FIP CFGIN PTO00 Loading motor STB TM CLK FIP C/D DOUT µ PD16311 DIN CS OSD CLK µ PD6454 DATA Composite synchronous signal Video head switch Audio head switch Pseudo-vertical synchronous signal Audio-video signal processor unit REEL0IN PWM5 M Driver PWM3 M Driver PWM4 Reel motors Reel FG1 Tuner unit PORT PORT REEL1IN INTP2 Low-frequency oscillation mode X1 X2 XT1 XT2 8 MHz 10 32.768 kHz Mechanical block Signals from remote controller Remote control receive signal µ PC2800A µPD78P4916 CONTENTS 1. DIFFERENCES BETWEEN µPD78P4916 AND µPD784915, µPD784916A ································· 12 2. PIN FUNCTION ································································································································· 13 2.1 Normal Operation Mode ····························································································································· 13 2.2 PROM Programming Mode (VPP ≥ 5 V, RESET = L) ·················································································· 15 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ························································· 16 * 3. INTERNAL MEMORY CAPACITY SELECT REGISTER (IMS) ··················································· 20 4. PROM PROGRAMMING ··················································································································· 21 4.1 4.2 4.3 4.4 Operation Mode ·········································································································································· PROM Write Procedure ······························································································································ PROM Read Procedure ······························································································································ Screening One-time PROM Versions ······································································································· 21 23 27 27 5. ELECTRICAL SPECIFICATIONS ····································································································· 28 * 6. PACKAGE DRAWING ······················································································································ 46 7. RECOMMENDED SOLDERING CONDITIONS ················································································· 47 * APPENDIX A. DEVELOPMENT TOOLS ····························································································· 48 APPENDIX B. SOCKET DRAWING AND RECOMMENDED FOOTPRINT ········································ 50 APPENDIX C. RELATED DOCUMENTS ···························································································· 52 11 * µPD78P4916 * 1. DIFFERENCES BETWEEN µPD78P4916 AND µPD784915, µPD784916A Other than the memory types, their capacities, and memory-related points, the functions of the three devices are identical: the µ PD78P4916 incorporates a one-time PROM that is rewritable by users, while the µPD784915 and 784916A contain mask ROMs. Table 1-1 shows the differences among these devices. Be sure to keep in mind these differences especially when debugging and pre-producing the application system with the PROM version and then mass-producing it with the mask-ROM version. For the details about the CPU functions and on-chip hardware, refer to the µPD784915 Subseries User’s Manual—Hardware (U10444E). Table 1-1. Differences among µPD784915 Subseries Devices Parameters µPD78P4916 µPD784915 µPD784916A Internal ROM One-time PROM Mask ROM Mask ROM 62 KbytesNote 48 Kbytes 62 Kbytes Internal RAM 2048 bytesNote 1280 bytes 1280 bytes Internal memory size select register (IMS) Provided Not provided Not provided Pinouts Pins related to PROM writing and reading are provided on the µPD78P4916. Other There are differences in noise immunity, noise radiation, and some electrical specifications, because of the differences in circuit complexity and mask layout. Note The internal PROM and RAM capacities of the µPD78P4916 can be changed through its internal memory size select register (IMS). Caution There are differences in noise immunity and noise radiation between the PROM and mask-ROM versions. When pre-producing the application set with the PROM version and then massproducing it with the mask-ROM version, be sure to conduct sufficient evaluations for the set using consumer samples (not engineering samples) of the mask-ROM version. 12 µPD78P4916 2. PIN FUNCTION 2.1 Normal Operation Mode (1) Port Pins Pin Name Input/Output Alternate function P00 - P07 I/O P40 - P47 I/O – 8-bit input/output port (Port4) • Specifiable to input or output mode bitwise. • With software-specifiable on-chip pull-up resistors (P40 - P47). P50 - P57 I/O – 8-bit input/output port (Port5) • Specifiable to input or output mode bitwise. • With software-specifiable on-chip pull-up resistors (P50 - P57). P60 I/O STRB/CLO 8-bit input/output port (Port6) P61 SCK1/BUZ • Specifiable to input or output mode bitwise. P62 SO1 P63 SI1 P64 – P65 HWIN P66 PWM4 P67 PWM5 P70 - P77 P80 Input I/O P82 Real-time output port Description Real-time for Pseudo-V SYNC output 7-bit input/output port (Port8) output port for HASW output • Specifiable to input or output for ROTC output PWM2 P85 PWM3 P86 PTO10 P87 PTO11 P96 (P60 - P67). 8-bit input port (Port7) P84 P91 - P95 • With software-specifiable on-chip pull-up resistors ANI0 - ANI7 P83 P90 8-bit input/output port (Port0) • Specifiable to input or output mode bitwise. • With software-specifiable on-chip pull-up resistors (P00 - P07). I/O ENV KEY0 - KEY4 – mode bitwise. • With software-specifiable on-chip pull-up resistors (P80, P82 - P87) 7-bit input/output port (Port9) • Specifiable to input or output mode bitwise. • With software-specifiable on-chip pull-up resistors (P90 - P96). 13 µPD78P4916 (2) Non-Port Pins (1/2) Pin Name REEL0IN Input/Output Alternate function Input INTP3 Description Reel FG inputs REEL1IN – DFGIN – Drum FG, PFG input (Three-value) DPGIN – Drum PG input CFGIN – Capstan FG input CSYNCIN – Composite SYNC input CFGCPIN – CFG comparator input CFGAMPO Output – CFG amplifier output PTO00 Output – Programmable timer outputs of super timer unit PTO01 – PTO02 – PTO10 P86 PTO11 P87 PWM0 Output – PWM1 – PWM2 P84 PWM3 P85 PWM4 P66 PWM5 P67 PWM outputs of super timer unit HASW Output P82 Head amplifier switch output ROTC Output P83 Chrominance rotate output ENV Input P90 Envelope input SI1 Input P63 Serial data input (Serial interface channel 1) SO1 Output P62 Serial data output (Serial interface channel 1) I/O P61/BUZ SI2 Input BUSY SO2 Output – Serial data output (Serial interface channel 2) SCK2 I/O – Serial clock input/output (Serial interface channel 2) BUSY Input SI2 STRB Output P60/CLO Serial strobe output (Serial interface channel 2) Analog inputs P70 - P77 Analog inputs for A/D converter SCK1 ANI0 - ANI7 ANI8 - ANI11 CTLIN Serial clock input/output (Serial interface channel 1) Serial data input (Serial interface channel 2) Serial busy input (Serial interface channel 2) – – – CTL amplifier input capacitor CTLOUT1 Output – CTL amplifier output CTLOUT2 I/O – Logic input/CTL amplifier output RECCTL+, RECCTL– I/O – RECCTL output/PBCTL input CTLDLY – – External time-constant connection (to rewrite RECCTL) VREFC – – AC ground for VREF amplifier Input – Non-maskable interrupt request input NMI 14 µPD78P4916 (2) Non-Port Pins (2/2) Pin Name Input/Output Alternate function Description INTP0 - INTP2 Input – INTP3 Input REEL0IN KEY0 - KEY4 Input P91 - P95 Key input signal CLO Output P60/STRB Clock output BUZ Output P61/SCK1 Buzzer output HWIN Input P65 RESET Input – Reset input X1 Input – Crystal resonator connection for main system clock oscillation X2 – – Crystal resonator connection for subsystem clock oscillation External interrupt request input Hardware timer external input XT1 Input XT2 – AVDD1, AVDD2 – – Positive power supply for analog unit AVSS1, AVSS2 – – GND for analog unit AVREF – – Reference voltage input to A/D converter VDD – – Positive power supply to digital unit VSS – – GND of digital unit IC – – Internally connected. Connect directly to VSS. Crystal resonator connection for clock oscillation of watch 2.2 PROM Programming Mode (VPP ≥ 5 V, RESET = L) Pin name VPP RESET Input/output – Set PROM programming mode High voltage applied at program write/verify operation Input Low level input for setting PROM programming mode A0 - A16 D0 - D7 PGM Function Address input I/O Input Data input/output Program inhibit input in PROM programming mode CE PROM enable input / programming pulse input OE Read strobe input to PROM VDD VSS – Positive power supply GND potential 15 µPD78P4916 * 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-1 shows the input/output circuit types of the device’s pins and the recommended connection of the pins which are unnecessary to the user’s application. The circuit diagrams for the I/O circuits are shown in Figure 2-1. Table 2-1. Pins P00-P07 P40-P47 P50-P57 P60/STRB/CLO Pin I/O Circuits and Recommended Connection of Unused Pins (1/2) I/O circuit types 5-A P61/SCK1/BUZ P62/SO1 P63/SI1 P64 P65/HWIN P66/PWM4 P67/PWM5 P70/ANI0-P77/ANI7 P80 P82/HASW P83/ROTC P84/PWM2 P85/PWM3 P86/PTO10 P87/PTO11 P90/ENV P91/KEY0-P95/KEY4 P96 SI2/BUSY SO2 8-A SCK2 ANI8-ANI11 RECCTL+, RECCTL– Direction I/O Recommended connection of unused pins Input mode: Connect to V DD. Output mode: Leave unconnected. 5-A 8-A 5-A 8-A 5-A 9 5-A Input I/O 8-A 5-A 2-A 4 Input Output 8-A I/O 7 — Input I/O Connect to VSS. Input mode: Connect to V DD. Output mode: Leave unconnected. Connect to VDD . High-impedance mode: Connect to V SS via a pull-down resistor. Otherwise: Leave unconnected. Input mode: Connect to V DD. Output mode: Leave unconnected. Connect to VSS. When ENCTL = 0 and ENREC = 0: Connect to V SS. Remark ENCTL: Bit 1 of the amplifier control register (AMPC) ENREC: Bit 7 of the amplifier mode register 0 (AMPM0) 16 µPD78P4916 Table 2-1. Pins DFGIN DPGIN Pin I/O Circuits and Recommended Connection of Unused Pins (2/2) I/O circuit types — Direction Input — — Output I/O — — Output — 3 Output 2 Input 2-A — Input — 2 — — — CFGIN, CFGCPIN CSYNCIN REEL0IN/INTP3, REEL1IN CTLOUT1 CTLOUT2 CFGAMPO CTLIN VREFC CTLDLY PWM0, PWM1 PTO00-PTO02 NMI INTP0 INTP1, INTP2 AVDD1 , AVDD2 AVREF , AVSS1, AVSS2 RESET XT1 XT2 IC Remark ENDRUM: Recommended connection of unused pins ENDRUM = 0: Connect to VSS. ENDRUM = 0, or ENDRUM = 1 and SELPGSEPA = 0: Connect to VSS. ENCAP = 0: Connect to V SS. ENCSYN = 0: Connect to VSS . ENREEL = 0: Connect to VSS. Leave unconnected. When ENCTL and ENCOMP = 0 and 0: Connect to V SS. ENCTL = 1: Leave unconnected. Leave unconnected. When ENCTL = 0: Leave unconnected. When ENCTL, ENCAP, and ENCOMP = 0, 0, and 0: Leave unconnected. Leave unconnected. Leave unconnected. Connect to VDD . Connect to VDD or V SS. Connect to VDD . Connect to VDD . Connect to VSS. — Connect to VSS. Leave unconnected. Connect directly to VSS. Bit 2 of the amplifier control register (AMPC) SELPGSEPA: Bit 2 of the amplifier mode register 0 (AMPM0) ENCAP: Bit 3 of the amplifier control register (AMPC) ENCSYN: Bit 5 of the amplifier control register (AMPC) ENREEL: Bit 6 of the amplifier control register (AMPC) ENCTL: Bit 1 of the amplifier control register (AMPC) ENCOMP: Bit 4 of the amplifier control register (AMPC) 17 µPD78P4916 Figure 2-1. Pin I/O Circuit Diagrams (1/2) Type 2 Type 5-A VDD IN Schmitt triggered input with hysteresis characteristics. pullup enable P-ch VDD data P-ch Type 2-A IN/ OUT VDD output disable pullup enable P-ch N-ch input enable IN Schmitt triggered input with hysteresis characteristics. Type 7 Type 3 VDD IN P-ch N-ch Comparator P-ch data OUT VREF (Threshold voltage) N-ch Type 8-A VDD Type 4 pullup enable VDD data P-ch VDD OUT output disable data P-ch IN/ OUT N-ch output disable Push-pull output that can also set the output to the high-impedance state (both P-ch and N-ch transistors are turned off.) 18 P-ch N-ch µPD78P4916 Figure 2-1. Pin I/O Circuit Diagrams (2/2) Type 9 IN P-ch Comparator N-ch VREF (Threshold voltage) input enable 19 µPD78P4916 3. INTERNAL MEMORY CAPACITY SELECT REGISTER (IMS) Internal memory capacity select register (IMS) specifies the effective area of on-chip memory (PROM, RAM) of the µPD78P4916. Setting this register is required when the capacity of the ROM or RAM in the mask version is smaller than that of the µ PD78P4916. If the memory capacity of the µ PD78P4916 is appropriately defined using this register, bugs in application programs due to accessing an address beyond the memory capacity of the actual chip can be avoided. The IMS register is write-only register. To write this register, use the 8-bit manipulation instruction. The register is initialized to FFH by RESET input (ROM: 62 Kbytes, RAM: 2048 bytes). * Figure 3-1. Internal Memory Capacity Select Register (IMS) Format IMS 7 6 1 1 5 4 ROM1 ROM0 3 2 1 1 1 0 RAM1 RAM0 Address State at reset R/W FFH FFFCH RAM1 RAM0 W Specification of internal RAM capacity 0 1 1280 bytes 1 1 2048 bytes Setting prohibited Other ROM1 ROM0 Specification of internal ROM capacity 1 0 48 Kbytes 1 1 62 Kbytes Other Setting prohibited Caution The µPD78P4916 has the IMS and the µPD784915 and 784916A do not have it. However, if a write instruction to IMS is executed in the µPD784915 or 784916A, it does not cause conflicts or malfunctions. 20 µPD78P4916 4. PROM PROGRAMMING The µPD78P4916 has on-chip 62-Kbyte PROM as the program memory. The PROM programming mode is entered by setting VDD, IC/V PP, and RESET pins as specified. For the settings of the unused pins in this mode, refer to the drawing of “(2) PROM Programming Mode” in the section “Pin Configuration (Top View)”. 4.1 Operation Mode The PROM programming mode is entered by applying +5 V or +12 V to the IC/V PP pin, +5 V or +6.5 V to the V DD pins, and low-level voltage to the RESET pin. Table 4-1 shows the operation mode specified by the CE, OE, and PGM pins. It is possible to read the contents of PROM by setting up read operation mode. Table 4-1. Operation Mode of PROM Programming Pins RESET IC/VPP VDD CE OE PGM L +12.5 V +6.5 V H L H Data input Page write H H L High impedance Byte write L H L Data input Program verify L L H Data output Program inhibit × H H High impedance × L L L L H Data output Output disable L H × High impedance Standby H × × High impedance Operation mode Page data latch Read +5 V +5 V D0 - D7 Remark × : Low or high level 21 µPD78P4916 (1) Read mode By setting CE = L and OE = L, the device enters the read mode. (2) Output disable mode By setting OE = H, the device enters the output disable mode, where data output pins go to high impedance state. Therefore it is possible to read data from a specified device by enabling only the OE pin of the device to be read, if two or more µPD78P4916s are connected to a data bus. (3) Standby mode By setting CE = H, the device enters the Standby mode. In this mode, data output pins go to high impedance state regardless of the OE pin condition. (4) Page data latch mode By setting CE = H, PGM = H, and OE = L at the beginning of page programming mode, the device enters the page data latch mode. In this mode, 4-byte data are latched in page units (consisting of 4 bytes) to internal address/data latch circuit. (5) Page programming mode After one-page data (consisting of 4 bytes) and their address are latched in the page data latch mode, the page programming operation is executed by applying 0.1-ms programming pulse (active low) to the PGM pin under CE = H, OE = H conditions. Following that operation, the programming data is verified by setting CE = L and OE = L. When data is not programmed by one programming pulse, the write and verify operations are repeated X times (X ≤ 10). (6) Byte programming mode Applying 0.1-ms programming pulse (active low) to the PGM pin under CE = L and OE = H condition, byte programming operation is executed. Next, the programming data is verified by setting OE = L. When data is not programmed by one programming pulse, the write and verify operations are repeated X times (X ≤ 10). (7) Program verify mode By setting CE = L, PGM = H, and OE = L, the device enters the program verify mode. Check whether data is programmed correctly or not in this mode after write operation. (8) Program inhibit mode When the OE pins, VPP pins, and D0-D7 pins of two or more µ PD78P4916s are connected in parallel, use program inhibit mode to write data to one of those devices. Programming is executed in the page programming mode or byte programming mode as mentioned above. At that time, data is not programmed to a device for which high level voltage is applied to the PGM pin. 22 µPD78P4916 4.2 PROM Write Procedure Figure 4-1. Flowchart in Page Programming Mode Start Address = G VDD = 6.5 V, VPP = 12.5 V X=0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Address = Address + 1 Latch No X = X+1 X = 10? 0.1-ms programming pulse Verify 4 bytes Yes Fail Pass No Address = N ? Yes VDD = 4.5 to 5.5 V, VPP = VDD Pass Verify all bytes Fail All Pass Write operation end Defective Remarks 1. G = Start address 2. N = End address of the program 23 µPD78P4916 Figure 4-2. Operation Timing in Page Programming Mode Page data latch Address input A0, A1 Hi-Z Hi-Z Data input VPP VPP VDD VDD+1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL 24 Program verify Address input A2 - A16 D0 - D7 Page programming Hi-Z Data output µPD78P4916 Figure 4-3. Flowchart in Byte Programming Mode Start Address = G VDD = 6.5 V, VPP = 12.5 V X=0 X = X+1 No X = 10? 0.1-ms programming pulse Address = Address + 1 Verify Yes Fail Pass No Address = N ? Yes VDD = 4.5 to 5.5 V, VPP = VDD Pass Verify all bytes Fail All Pass Write operation end Defective Remarks 1. G = Start address 2. N = End address of the program 25 µPD78P4916 Figure 4-4. Operation Timing in Byte Programming Mode Programming A0 - A16 D0 - D7 Program verify Address input Hi-Z Data input Hi-Z Data output Hi-Z VPP VPP VDD VDD+1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL Cautions 1. Apply voltage to VDD before applying voltage to V PP, and cut off VDD voltage after VPP voltage is cut off. 2. The voltage including overshoot applied to VPP pin must be kept less than +13.5 V. 3. If a device is inserted or removed while +12.5 V is applied to VPP pin, it may be adversely affected in reliability. 26 µPD78P4916 4.3 PROM Read Procedure The contents of PROM can be read onto external data bus (D0-D7) as described below: (1) Fix RESET pin to low and supply +5 V to VPP pin. Connect other unused pins as specified in “(2) PROM Programming Mode” in section “Pin Configuration (Top View)." (2) Supply +5 V to the VDD and V PP pins. (3) Input the address of the data to be read to the A0-A16 pins. (4) Enter the read mode (CE = L, OE = L). (5) Output data to D0-D7 pins. The above operation timing from (2) to (5) is shown in Figure 4-5. Figure 4-5. PROM Read Timing Address input A0 - A16 CE (Input) OE (Input) D0 - D7 Hi-Z Data output Hi-Z 4.4 Screening One-time PROM Versions The one-time PROM version (µPD78P4916GF-3BA) cannot be completely tested by NEC for shipment because of its structure. For screening, it is recommended to verify PROM after storing the necessary data under the following conditions: Storage Temperature Storage Time 125 ˚C 24 hours 27 µPD78P4916 * 5. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 ˚C) Parameter Supply voltage Input voltage Analog input voltage Symbol Ratings Unit VDD VDD – AVDD1 ≤ 0.5 V –0.5 to +7.0 V AVDD1 VDD – AVDD2 ≤ 0.5 V –0.5 to +7.0 V AVDD2 AVDD1 – AVDD2 ≤ 0.5 V –0.5 to +7.0 V AVSS1 –0.5 to +0.5 V AVSS2 –0.5 to +0.5 V VI –0.5 to V DD+0.5 V VDD ≥ AVDD2 –0.5 to AVDD2 +0.5 V VDD < AVDD2 –0.5 to V DD+0.5 V –0.5 to V DD+0.5 V Per pin 15 mA Total of all output pins 100 mA Per pin –10 mA Total of all output pins –50 mA VIAN (ANI0-ANI11) Output voltage VO Output current, low IOL Output current, high Conditions IOH Operating ambient temperature TA –10 to +70 ˚C Storage temperature T stg –65 to +150 ˚C Caution If any of the above parameters exceeds the absolute maximum ratings, even momentarily, device reliability may be impaired. The absolute maximum ratings are values that may physically damage the product. Be sure to use the product within the ratings. Operating Conditions Clock frequency 4 MHz ≤ fXX ≤ 16 MHz 32 kHz ≤ fXT ≤ 35 kHz 28 Operating ambient temperature (TA ) –10 to +70 ˚C Operating condition Supply voltage (VDD ) All functions +4.5 to +5.5 V CPU function only +4.0 to +5.5 V Subclock operation (CPU, watch, and Port functions only) +2.7 to +5.5 V µPD78P4916 Oscillator Characteristics (Main Clock) (TA = –10 to +70 ˚C, VDD = AVDD = 4.0 to 5.5 V, VSS = AVSS = 0 V) Resonator Recommended circuit Crystal resonator Item Oscillation frequency (f XX) X1 MIN. MAX. Unit 4 16 MHz X2 VSS C1 C2 Oscillator Characteristics (Subclock) (TA = –10 to +70 ˚C, VDD = AVDD = 2.7 to 5.5 V, V SS = AV SS = 0 V) Resonator Recommended circuit Crystal resonator Item Oscillation frequency (fXT) XT1 MIN. MAX. Unit 32 35 kHz XT2 VSS C1 C2 Caution When using the main system clock and subsystem clock oscillators, wiring in the area enclosed with the dotted lines should be carried out as follows to avoid an adverse effect from wiring capacitance: • Wiring should be as short as possible. • Wiring should not cross other signal lines. Wiring should not be placed close to a varying high current. • The potential of the oscillator capacitor ground should be the same as VSS. Do not ground wiring to a ground pattern in which high current flows. • Do not fetch a signal from the oscillator. As the amplification degree of the subsystem clock oscillator is low to reduce current consumption, pay particular attention to the wiring method. 29 µPD78P4916 DC Characteristics (TA = –10 to +70 ˚C, VDD = AVDD = 4.5 to 5.5 V, V SS = AVSS = 0 V) Parameter Input voltage, low Symbol Conditions MIN. TYP. MAX. Unit VIL1 Other than pins indicated in Note 1 below 0 0.3V DD V VIL2 Pins indicated in Note 1 below 0 0.2VDD V VIL3 X1, X2 0 0.4 V VIH1 Other than pins indicated in Note 1 below 0.7V DD VDD V VIH2 Pins indicated in Note 1 below 0.8VDD VDD V VIH3 X1, X2 VDD–0.5 VDD V VOL1 IOL = 5.0 mA (Pins listed in Note 2 below) 0.6 V VOL2 IOL = 2.0 mA 0.45 V VOL3 IOL = 100 µA 0.25 V Output voltage, VOH1 IOH = –1.0 mA VDD–1.0 V high VOH2 IOH = –100 µA VDD–0.4 V Input voltage, high Output voltage, low Input leakage current ILI 0 ≤ VI ≤ VDD ±10 µA Output leakage current ILO 0 ≤ VO ≤ VDD ±10 µA VDD power supply current IDD1 Operation mode IDD2 HALT mode fXX = 16 MHz fXX = 8 MHz (Low frequency oscillation mode) Internal main clock operation at 8 MHz 35 55 mA fXT = 32.768 kHz Subclock operation (CPU, Watch, Port) VDD = 2.7 V 0.9 1.2 mA fXX = 16 MHz fXX = 8 MHz (Low frequency oscillation mode) Internal main clock operation at 8 MHz 15 27.5 mA fXT = 32.768 kHz Subclock operation (CPU, Watch, Port) VDD = 2.7 V 30 60 µA Data retention voltage VDDDR STOP mode Data retention current Note 3 IDDDR STOP mode VDDDR = 5.0 V Subclock oscillation 36 75 µA STOP mode VDDDR = 2.7 V Subclock oscillation 3.5 15 µA STOP mode VDDDR = 2.5 V Subclock suspended 1.5 10 µA 55 110 kΩ Pull-up resistor RL VI = 0 V 2.5 25 V Notes 1. RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0-P95/KEY4. 2. P46, P47 3. When subclock is suspended at STOP mode, disconnect feedback resistor and connect XT1 pin to the VDD potential. 30 µPD78P4916 AC Characteristics CPU and peripheral unit operation clocks (TA = –10 to +70 ˚C, VDD = AV DD = 4.5 to 5.5 V, VSS = AV SS = 0 V) Parameter Symbol CPU operation clock cycle time tCLK Conditions fXX = 16 MHz V DD = AVDD = 4.0 to 5.5 V CPU function only TYP. Unit 125 ns 125 ns MAX. Unit fXX = 16 MHz fXX = 8 MHz, Low frequency oscillation mode (CC bit7 = 1) Peripheral unit operation clock tCLK1 fXX = 16 MHz cycle time fXX = 8 MHz, Low frequency oscillation mode (CC bit7 = 1) Serial interface (1) SIOn: n = 1, 2 (TA = –10 to +70 ˚C, VDD = AVDD = 4.5 to 5.5 V, V SS = AVSS = 0 V) Parameter Symbol Serial clock cycle time Serial clock high/low level width tCYSK Conditions MIN. Input External clock 1.0 µs Output fCLK1/8 1.0 µs fCLK1/16 2.0 µs fCLK1/32 4.0 µs fCLK1/64 8.0 µs fCLK1/128 16 µs fCLK1/256 32 µs tWSKH Input External clock 420 ns tWSKL Output Internal clock tCYSK/2–50 ns SIn set-up time (to SCKn ↑) tSSSK 100 ns SIn hold time (from SCKn ↑) tHSSK 400 ns SOn output delay time (from SCKn ↓) tDSSK 0 300 ns MIN. MAX. Unit tWSKH tCYSK Remarks 1. fCLK1: Operation clock for peripheral unit (8 MHz) 2. n = 1, 2 (2) Only SIO2 (TA= –10 to +70 ˚C, V DD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions SCK2(8) ↑ → STRB ↑ tDSTRB Strobe high level width tWSTRB BUSY setup time (to BUSY detection timing) tSBUSY 100 ns BUSY hold time (from BUSY detection timing) tHBUSY 100 ns Busy inactive → SCK2(1) ↓ tLBUSY tCYSK –30 tCYSK+30 ns t CYSK+t WSKH Remarks 1. The value in the parentheses following SCK2 indicates the sequential number of the SCK2. 2. BUSY detection timing is (n + 2) × tCYSK (n = 0, 1,...) after SCK2(8) ↑. 3. BUSY inactive → SCK2(1) ↓ is a value at the time data is already written in SIO2. 31 µPD78P4916 Other Operations (TA = –10 to +70 ˚C, VDD = AVDD = 4.5 to 5.5 V, V SS = AVSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit Timer unit input low level width tWCTL at DFGIN, CFGIN, DPGIN, REEL0IN, REEL1IN logic level input tCLK1 ns Timer unit input high level width tWCTH at DFGIN, CFGIN, DPGIN, REEL0IN, REEL1IN logic level input tCLK1 ns Timer unit input signal valid edge input cycle tPERIN DFGIN, CFGIN and DPGIN input 2 µs CSYNCIN low level width tWCR1L Digital noise eliminator not used 8tCLK1 ns Digital noise eliminator used (INTM2 bit 4 = 0) 108t CLK1 ns Digital noise eliminator used (INTM2 bit 4 = 1) 180t CLK1 ns 8tCLK1 ns Digital noise eliminator used (INTM2 bit 4 = 0) 108t CLK1 ns Digital noise eliminator used 180t CLK1 ns CSYNCIN high level width tWCR1H Digital noise eliminator not used (INTM2 bit 4 = 1) Digital noise Eliminated pulse eliminator tWSEP INTM2 bit 4 = 0 104t CLK1 ns width INTM2 bit 4 = 1 176t CLK1 ns Passed pulse width INTM2 bit 4 = 0 108t CLK1 ns INTM2 bit 4 = 1 180t CLK1 ns NMI low level width tWNIL VDD = AVDD = 2.7 to 5.5 V 10 µs NMI high level width tWNIH VDD = AVDD = 2.7 to 5.5 V 10 µs INTP0 and INTP3 low level width tWIPL0 2tCLK1 ns INTP0 and INTP3 high level width tWIPH0 2tCLK1 ns INTP1, KEY0 - KEY4 low level tWIPL1 2tCLK1 ns 10 µs 2tCLK1 ns 10 µs 2tCLK1 ns width Other than in STOP mode When cancelling STOP mode INTP1, KEY0 - KEY4 high level tWIPH1 width Other than in STOP mode When cancelling STOP mode INTP2 low level width tWIPL2 Main clock operation Sampled at f CLK in normal mode Sampled at fCLK/128 Subclock operation Sampled at f CLK in normal mode Sampled at fCLK/128 When cancelling STOP mode INTP2 high level width tWIPH2 Note 7.9 Note µs ms µs ns 2tCLK1 in normal mode Sampled at fCLK/128 32 Subclock operation Sampled at f CLK in normal mode Sampled at fCLK/128 tWRSL µs 10 Sampled at f CLK Note 61 7.9 Note µs µs ms 10 µs 10 µs If a high level or low level is input two times in succession during the sampling period, high level or low level is detected. Remark tCLK1: Operation clock cycle time for peripheral unit (125 ns). 32 61 Main clock operation When cancelling STOP mode RESET low level width 32 Note µPD78P4916 Clock Output Operation (TA = –10 to +70 ˚C, VDD = AVDD = 4.5 to 5.5 V, V SS = AVSS = 0 V) Parameter Symbol Expression MIN. MAX. Unit 250 2000 ns CLO cycle time tCYCL CLO low level width tCLL tCYCL/2 ± 50 75 1050 ns CLO high level width tCLH tCYCL/2 ± 50 75 1050 ns CLO rising time tCLR 50 ns CLO falling time tCLF 50 ns Data Retention Characteristics (TA = –10 to +70 ˚C, VDD = AVDD = 2.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Input voltage, low VIL Input voltage, high VIH Note Conditions Pins listed in Note below MIN. TYP. MAX. Unit 0 0.1VDDDR V 0.9V DDDR VDDDR V RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0-P95/KEY4 Watch Function (TA = –10 to +70 ˚C, VDD = AVDD = 2.7 to 5.5 V, V SS = AVSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit Subclock oscillation retention voltage V DDXT 2.7 V Hardware watch function operation voltage V DDW 2.7 V Subclock Oscillation Suspension Detection Flag (T A = –10 to +70 ˚C, V DD = AV DD = 4.5 to 5.5 V, V SS = AV SS = 0 V) Parameter Oscillation suspension detection width Symbol Conditions MIN. tOSCF MAX. Unit µs 45 A/D Converter Characteristics (TA = –10 to +70 ˚C, VDD = AVDD = AVREF = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions Resolution MIN. TYP. 8 Total error AVREF = VDD Sampling time tCONV tSAMP 2.0 % ±1/2 LSB ADM bit 4 = 0 160tCLK1 µs ADM bit 4 = 1 80t CLK1 µs ADM bit 4 = 0 32t CLK1 µs ADM bit 4 = 1 16t CLK1 µs Analog input voltage VIAN Analog input impedance ZAN 1000 AI REF 0.4 AVREF current Unit bit Quantization error Conversion time MAX. 0 AVREF V MΩ 1.2 mA 33 µPD78P4916 VREF Amplifier (TA = 25 ˚C, V DD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Reference voltage V REF Charge current ICHG Note Conditions AMPM0.0 is set to 1 for pins listed in Note below. MIN. TYP. MAX. Unit 2.35 2.50 2.65 V µA 300 RECCTL+, RECCTL–, CFGIN, CFGCPIN, DFGIN, DPGIN, CSYNCIN, REEL0IN, REEL1IN CTL Amplifier (TA = 25 ˚C, V DD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit CTL+, – input resistance RICTL 2 5 10 kΩ Feedback resistance RFCTL 20 50 100 kΩ Bias resistance RBCTL 20 50 100 kΩ Minimum voltage gain GCTLMIN 17 20 22 dB Maximum voltage gain G CTLMAX 71 75 dB 1.77 dB 50 dB Gain switching step S GAIN Common mode signal rejection CMR DC, Voltage gain: 20 dB Comparator set voltage for waveform regulation, high VPBCTLHS VREF+0.47 VREF+0.50 VREF+0.53 V Comparator reset voltage for VPBCTLHR VREF+0.27 VREF+0.30 VREF+0.33 V Comparator set voltage for waveform regulation, low VPBCTLLS VREF –0.53 VREF –0.50 VREF –0.47 V Comparator reset voltage for waveform regulation, low VPBCTLLR VREF –0.33 VREF –0.30 VREF –0.27 V Comparator high voltage for CLT flag S V FSH VREF+1.00 VREF+1.05 VREF+1.10 V Comparator low voltage for CLT flag S VFSL VREF –1.10 VREF –1.05 VREF –1.00 V Comparator high voltage for CLT flag L VFLH VREF+1.40 VREF+1.45 VREF+1.50 V Comparator low voltage for CLT flag L VFLL VREF –1.50 VREF –1.45 VREF –1.40 V waveform regulation, high 34 µPD78P4916 CFG Amplifier (AC Coupling) (TA = 25 ˚C, VDD = AVDD = 5 V, V SS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Voltage gain 1 GCFG1 fi = 2 kHz, open loop 50 dB Voltage gain 2 GCFG2 fi = 2 kHz, open loop 34 dB CFGAMPO output current, high IOHCFG DC –1 mA CFGAMPO output current, low IOLCFG DC 0.4 mA Comparator high voltage V CFGH VREF+0.09 VREF+0.12 VREF +0.15 V Comparator low voltage VCFGL VREF –0.15 VREF –0.12 V REF–0.09 V Duty precision P DUTY Note See Note below. 49.7 50.0 50.3 % MAX. Unit The following circuit and input signal conditions are assumed. µPD78P4916 • Input signal: sine wave input (5 mVp-p), f i = 1 kHz 1 kΩ • Voltage gain: 50 dB CFGIN 22 µF 330 kΩ CFGAMPO 0.01 µF CFGCPIN DFG Amplifier (AC Coupling) (TA = 25 ˚C, VDD = AVDD = 5 V, V SS = AVSS = 0 V) Parameter Symbol Conditions fi = 900 Hz, open loop MIN. TYP. Voltage gain G DFG 50 Feedback resistance RFDFG Input protect resistance RIDFG 150 Ω Comparator high voltage V DFGH VREF+0.07 VREF+0.10 VREF+0.14 V Comparator low voltage VDFGL VREF –0.14 VREF –0.10 VREF –0.07 V 160 dB 400 640 kΩ Caution The resistance of the pin to be connected to the DFGIN pin must be below 16 kΩ. If the resistance is higher than the limit, the DFG amplifier may oscillate. DPG Comparator (AC Coupling) (TA = 25 ˚C, V DD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 20 50 100 kΩ Input impedance Z IDPG Comparator high voltage VDPGH VREF+0.02 VREF+0.05 VREF+0.08 V Comparator low voltage V DPGL VREF –0.08 VREF –0.05 VREF –0.02 V 35 µPD78P4916 Three-value divider (TA = 25 ˚C, V DD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 20 50 100 kΩ Input impedance Z IPFG Comparator high voltage VPFGH VREF +0.5 VREF+0.7 VREF+0.9 V Comparator low voltage VPFGL V REF–1.4 VREF–1.2 VREF–1.0 V CSYNC Comparator (AC Coupling) (TA = 25 ˚C, V DD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 20 50 100 kΩ Input impedance ZICSYN Comparator high voltage VCSYNH VREF+0.07 VREF+0.10 VREF+0.13 V Comparator low voltage VCSYNL VREF –0.13 VREF –0.10 VREF –0.07 V Reel FG Comparator (AC Coupling) (TA = 25 ˚C, VDD = AVDD = 5 V, V SS = AV SS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 20 50 100 kΩ Input impedance ZIRLFG Comparator high voltage VRLFGH VREF+0.02 VREF+0.05 VREF+0.08 V Comparator low voltage VRLFGL VREF –0.08 VREF –0.05 VREF –0.02 V RECCTL Driver (TA = 25 ˚C, V DD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol RECCTL+, – high level output voltage VOHREC IOH = –4 mA RECCTL+, – low level output voltage VOLREC IOL = 4 mA CTLDLY on-chip resistor RCTL CTLDLY charge current IOHCTL CTLDLY discharge current IOLCTL 36 Conditions MIN. MAX. VDD –0.8 40 On-chip resistor disabled TYP. Unit V 70 0.8 V 140 kΩ –3 mA –3 mA µPD78P4916 Timing Waveform AC timing test point 0.8 VDD or 2.2 V 0.8 VDD or 2.2 V Test points 0.8 V 0.8 V Serial Transfer Timing (SIOn: n = 1, 2) tWSKH tWSKL SCKn tCYSK tSSSK SIn tHSSK Input data tDSSK SOn Output data 37 µPD78P4916 Serial Transfer Timing (Only SIO2) No busy processing tWSKL SCK2 tWSKH 7 8 9 10 1 2 10 10+n tCYSK BUSY At active-high Invalid busy tDSTRB tWSTRB STRB Continue busy processing tWSKL SCK2 tWSKH 7 8 9 tCYSK BUSY tSBUSY tHBUSY At active-high tDSTRB tWSTRB STRB Terminate busy processing tWSKL SCK2 tWSKH 7 8 tCYSK 9 10+n tHBUSY 11+n 1 tLBUSY At active-high BUSY Caution Do not use busy control and strobe control whenever the external clock is selected as a serial clock. 38 µPD78P4916 Super timer unit input timing tWCTH At DFGIN, CFGIN, DPGIN, REEL0IN and REEL1IN logic level input tWCTL 0.8 VDD 0.8 V tWCR1H tWCR1L 0.8 VDD At CSYNCIN logic level input 0.8 V Interrupt input timing tWNIH tWNIL 0.8 VDD NMI 0.8 V tWIPH0 tWIPL0 0.8 VDD INTP0, INTP3 0.8 V tWIPH1 tWIPL1 0.8 VDD INTP1, KEY0 - KEY4 0.8 V tWIPH2 tWIPL2 0.8 VDD INTP2 0.8 V Reset input timing tWRSL RESET 0.8 V 39 µPD78P4916 Clock output timing tCLH CLO 0.8 VDD 0.8 V tCLR tCLF tCLL tCYCL 40 µPD78P4916 DC Programming Characteristics (TA = +25 ± 5 ˚C, VSS = AVSS = 0 V) Parameter Symbol Symbol Input voltage, high VIH VIH Input voltage, low VIL VIL Note 1 Conditions MIN. TYP. MAX. Unit 2.4 VDDP+0.3 V –0.3 0.8 V ±10 µA Input leakage current ILIP ILI 0 ≤ VI ≤ VDDP Output voltage, high VOH1 VOH1 IOH = –400 µA 2.4 V VOH2 VOH2 IOH = –100 µA VDDP–0.7 V Output voltage, low VOL VOL IOL = 2.1 mA 0.45 V Output leakage current ILO 0 ≤ VO ≤ VDDP, OE = VIH ±10 µA VDD supply voltage VPP supply voltage VDDP VPP VDD VPP Note 2 Program memory write mode 6.25 6.5 6.75 V Program memory read mode 4.50 5.0 5.50 V Program memory write mode 12.2 12.5 12.8 V Program memory read mode VDD supply current VPP supply current IDD IPP IDD IPP VPP = VDDP V Program memory write mode 50 mA Program memory read mode 30 mA Program memory write mode 50 mA 100 µA Program memory read mode 1 Notes 1. Corresponding symbols of the µPD27C1001A. 2. VDDP is a VDD pin during programming. 41 µPD78P4916 AC Programming Characteristics (TA = +25 ± 5 ˚C, VSS = AVSS = 0 V) PROM Write Operation Mode (Page Programming Mode) Parameter Symbol Note 1 Conditions MIN. TYP. MAX. Unit Address setup time tAS 2 µs CE set time tCES 2 µs Input data setup time tDS 2 µs Address hold time tAH 2 µs tAHL 2 µs tAHV 0 µs Input data hold time tDH 2 µs Output data hold time tDF 0 VPP setup time tVPS 2 µs 2 µs VDDP setup time tVDS Note 2 230 Initial programming pulse width tPW 0.095 OE set time tOES 2 OE → valid data delay time tOE OE pulse width during data latch tLW 1 µs PGM set-up time tPGMS 2 µs CE hold time tCEH 2 µs OE hold time tOEH 2 µs Notes 1. Correspond to symbols of the µPD27C1001A (except tVDS ). 2. tVDS corresponds to tVCS of the µ PD27C1001A. 42 0.1 0.105 ns ms µs 1 µs µPD78P4916 PROM Write Mode (Byte Programming Mode) Parameter Symbol Note 1 Conditions MIN. TYP. MAX. Unit Address setup time tAS 2 µs CE set time tCES 2 µs Input data setup time tDS 2 µs Address hold time tAH 2 µs Input data hold time tDH 2 µs Output data hold time tDF 0 VPP setup time tVPS 2 µs 2 µs VDDP setup time tVDS Note 2 Initial programming pulse width tPW 0.095 OE set time tOES 2 OE → valid data delay time tOE 130 0.1 0.105 ns ms µs 150 ns MAX. Unit Notes 1. Correspond to symbols of the µPD27C1001A (except tVDS ). 2. tVDS corresponds to tVCS of the µ PD27C1001A. PROM Read Mode Parameter Symbol Note 1 Conditions MIN. TYP. Address → data output time tACC CE = OE = VIL 200 ns CE ↓ → data output time tCE OE = VIL 200 ns OE ↓ → data output time tOE CE = VIL 75 ns Data hold time (from OE ↑, CE ↑) Note 2 tDF CE = VIL or OE = VIL 0 60 ns Data hold time (from address) tOH CE = OE = VIL 0 ns Notes 1. Correspond to symbols of the µPD27C1001A. 2. tDF is a time after either OE or CE rose to VIH first. 43 µPD78P4916 PROM Write Mode Timing (Page Programming Mode) Page data latch Page programming Program verify A2 - A16 tAS tAHL tDS tDH tAHV A0, A1 D0 - D7 Hi-Z tVPS tDH Hi-Z Data input Hi-Z tOE tPGMS Data output VPP tAH VPP VDDP tVDS VDDP +1.5 VDDP VDDP tCES tOEH VIH CE VIL tCEH tPW VIH PGM VIL VIH OE VIL 44 tLW tOES µPD78P4916 PROM Write Mode Timing (Byte Programming Mode) Programming Program verify A0 - A16 tAS D0 - D7 Hi-Z tDF Hi-Z Data input tDS Hi-Z Data output tDH tAH VPP VPP VDDP tVPS VDD+1.5 VDDP VDDP tVDS VIH CE VIL tCES tPW VIH PGM VIL tOES tOE VIH OE VIL Cautions 1. Apply voltage to VDDP before applying voltage to VPP, and cut off VDDP voltage after V PP voltage is cut off. 2. The voltage, including overshoot, applied to VPP pin must be kept less than +13.5 V. 3. If a device is inserted or removed while +12.5 V is applied to VPP pin, it may be adversely affected in reliability. PROM Read Mode Timing A0 - A16 Valid address CE tCE OE tDFNote 2 tOENote 1 tACCNote 1 D0 - D7 Hi-Z tOH Data output Hi-Z Notes 1. If data need to be read within tACC, the maximum delay time of OE active level input from CE falling should be t ACC – t OE. 2. tDF is the time after either OE or CE first rose to VIH. 45 µPD78P4916 6. PACKAGE DRAWING 100 PIN PLASTIC QFP (14 × 20) A B Q F G H I M 5°±5° 31 30 S 100 1 detail of lead end D 51 50 C 80 81 J M P K N L P100GF-65-3BA1-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. 46 ITEM MILLIMETERS INCHES A 23.6 ± 0.4 0.929 ± 0.016 B 20.0 ± 0.2 0.795 +0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 0.8 0.031 G 0.6 0.024 H 0.30 ± 0.10 0.012+0.004 –0.005 I 0.15 0.006 J 0.65 (T.P.) 0.026 (T.P.) K 1.8 ± 0.2 0.071+0.008 –0.009 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.1 ± 0.1 0.004 ± 0.004 S 3.0 MAX. 0.119 MAX. µPD78P4916 7. RECOMMENDED SOLDERING CONDITIONS * This device should be soldered and mounted under the following conditions. For details about the recommended conditions, refer to the document “Semiconductor Device Mounting Technology Manual” (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 7-1. Surface Mounting Type Soldering Conditions µPD78P4916GF-3BA: 100-pin plastic QFP (14 x 20 mm) Soldering Method Soldering Conditions Symbol Infrared rays reflow Peak package's surface temperature: 235 ˚C, Reflow time: 30 seconds or less (at 210 ˚C or higher), Number of reflow processes: 2 or less <Attention> (1) Wait for the device temperature to come down to room temperature after the first reflow before starting the second reflow. (2) Do not perform flux cleaning of the soldered portion after the first reflow. IR35-00-2 VPS Peak package's surface temperature: 215 ˚C, Reflow time: 40 seconds or less (at 200 ˚C or higher), Number of reflow processes: 2 or less <Attention> (1) Wait for the device temperature to come down to room temperature after the first reflow before starting the second reflow. (2) Do not perform flux cleaning of the soldered portion after the first reflow. VP15-00-2 Wave soldering Solder temperature: 260 ˚C or below, Flow time: 10 seconds or less, Number of flow WS60-00-1 process: 1, Preheating temperature; 120 ˚C max. (package surface temperature) Partial heating Pin temperature: 300 ˚C or below, Time: 3 seconds or less (per pin row) — Caution Do not use different soldering methods together (except for partial heating). 47 µPD78P4916 * APPENDIX A. DEVELOPMENT TOOLS The following development tools are prepared for system development using the µPD78P4916. Language Software RA78K4 Note 1 Assembler package common to the 78K/IV Series CC78K4 Note 1 C compiler package common to the 78K/IV Series CC78K4-L Note 1 C compiler library source file common to the 78K/IV Series PROM Writing Tool PG-1500 PROM programmer PA-78P4916GF Programmer adapter connected to the PG-1500 PG-1500 Controller Note 2 Control program for PG-1500 Debugging Tool IE-784000-R In-circuit emulator common to the 78K/IV Series IE-784000-R-BK Break board common to the 78K/IV Series IE-784000-R-EM Emulation board common to the 78K/IV Series IE-784915-R-EM1 Emulation board for evaluation of the µPD784915 Subseries IE-78000-R-SV3 Interface adapter when using EWS as a host machine IE-70000-98-IF-B Interface adapter when using PC-9800 series (except notebook type) as a host machine IE-70000-98N-IF Interface adapter and cable when using notebook type PC-9800 series as a host machine IE-70000-PC-IF-B Interface adapter when using IBM PC/ATTM as a host machine EP-784915GF-R Emulation probe common to the µPD784915 subseries EV-9200GF-100 Conversion socket for 100-pin plastic QFP to mount a device on a target system SM78K4 ID78K4 Note 3 Note 3 DF784915 * Note 4 System emulator for all 78K/IV series devices Integrated debugger for IE-784000-R Device file common to the µPD784915 subseries Real-time OS RX78K/IV MX78K4 48 Note 4 Note 2 Real-time OS common to the 78K/IV series OS common to the 78K/IV series µPD78P4916 Notes 1. • PC-9800 series (for MS-DOSTM) based * • IBM PC/AT and compatibles (for PC DOSTM , WindowsTM , MS-DOS, and IBM DOSTM) based • HP9000 series • 700TM SPARCstationTM (for (for HP-UXTM) SunOSTM) based based • NEWS TM (NEWS-OSTM) based 2. • PC-9800 series (for MS-DOS) based • IBM PC/AT and its compatibles (for PC DOS, Windows, MS-DOS, and IBM DOS) based 3. • PC-9800 series (for Windows on MS-DOS) based • IBM PC/AT and its compatibles (for PC DOS, Windows, MS-DOS, and IBM DOS) based • HP9000 series 700 (for HP-UX) based • SPARCstation (for SunOS) based 4. • PC-9800 series (for MS-DOS) based • IBM PC/AT and compatibles (for PC DOS, Windows, MS-DOS, and IBM DOS) based • HP9000 series 700 (for HP-UX) based • SPARCstation (for SunOS) based Remark The RA78K4, CC78K4, SM78K4, and ID78K4 should be used in combination with the DF784915. 49 µPD78P4916 APPENDIX B. SOCKET DRAWING AND RECOMMENDED FOOTPRINT Figure B-1. EV-9200GF-100 Drawing (For reference purpose only) A B E M N O L K J S R F D C EV-9200GF-100 1 Q * No.1 pin index P G H I EV-9200GF-100-G0 ITEM 50 MILLIMETERS INCHES A 24.6 0.969 B 21 0.827 C 15 0.591 D 18.6 0.732 E 4-C 2 4-C 0.079 F 0.8 0.031 G 12.0 0.472 H 22.6 0.89 I 25.3 0.996 J 6.0 0.236 K 16.6 0.654 L 19.3 076 M 8.2 0.323 N 8.0 0.315 O 2.5 0.098 P 2.0 0.079 Q 0.35 0.014 R φ 2.3 φ 0.091 S φ 1.5 φ 0.059 µPD78P4916 Figure B-2. Recommended EV-9200GF-100 Footprint (For reference purpose only) G J H D F E K I L C B A EV-9200GF-100-P1 ITEM MILLIMETERS INCHES A 26.3 1.035 B 21.6 0.85 C +0.002 0.65±0.02 × 29=18.85±0.05 0.026 +0.001 –0.002 × 1.142=0.742 –0.002 D +0.003 0.65±0.02 × 19=12.35±0.05 0.026 +0.001 –0.002 × 0.748=0.486 –0.002 E 15.6 0.614 F 20.3 0.799 G 12 ± 0.05 0.472 +0.003 –0.002 H 6 ± 0.05 0.236 +0.003 –0.002 I 0.35 ± 0.02 0.014 +0.001 –0.001 J φ 2.36 ± 0.03 φ 0.093+0.001 –0.002 K φ 2.3 φ 0.091 L φ 1.57 ± 0.03 φ 0.062+0.001 –0.002 Caution Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). 51 µPD78P4916 * APPENDIX C. RELATED DOCUMENTS Document related to device Title Document No. Japanese English µPD784915 Subseries User’s Manual – Hardware U10444J U10444E µPD784915 Subseries Special Function Register Table U10976J — 78K/IV Series User’s Manual – Instructions U10905J U10905E 78K/IV Series Instruction Table U10594J — 78K/IV Series Instruction Set U10595J — 78K/IV Series Application Note – Software Basics U10095J — Development tool documents (User’s Manual) Title Document No. Japanese English Language EEU-809 EEU-1399 Operation EEU-815 EEU-1404 EEU-817 EEU-1402 Language EEU-656 EEU-1280 Operation EEU-655 EEU-1284 CC78K Series Library Source File EEU-777 — PG-1500 PROM Programmer EEU-651 EEU-1335 PG-1500 Controller PC-9800 series – MS-DOS base EEU-704 EEU-1291 PG-1500 Controller IBM PC series – PC DOS base EEU-5008 U10540E EEU-5004 EEU-1534 U10931J — U10440J IEU-1412 RA78K Series Assembler Package RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler IE-784000-R IE-784915-R-EM1 EP-784915GF-R ID78K4 Integrated Debugger – Reference Embedded-software documents (User’s Manual) Title RX78K/IV Series Real-time OS Document No. Japanese English Basics U10604J — Installation U10603J — Debugger U10364J — Caution The contents of the documents listed above are subject to change without prior notice to users. Be sure to use the latest edition when starting design. 52 µPD78P4916 * Other documents Title Document No. Japanese English IEI-635 IEI-1213 C10535J C10535E IEI-620 IEI-1209 NEC Semiconductor Device Reliability/Quality Control System IEM-5068 — Electrostatic Discharge (ESD) Test MEM-539 — Guide to Quality Assurance for Semiconductor Devices MEI-603 MEI-1202 Microcontroller-Related Product Guide - Third Party Products MEI-604 — Semiconductor Device Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices Caution The contents of the documents listed above are subject to change without prior notice to users. Be sure to use the latest edition when starting design. 53 µPD78P4916 [MEMO] 54 µPD78P4916 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 55 µPD78P4916 FIP is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The application circuits and their parameters are for reference only and are not intended for use in actual design-in's. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: “Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11