DATA SHEET MOS INTEGRATED CIRCUIT µPD78P4908 16-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD78P4908, 78K/IV series' product, is a one-time PROM version of the µ PD784907 and µ PD784908 with internal mask ROM. Since user programs can be written to PROM, this microcomputer is best suited for evaluation in system development, manufacture of small quantities of multiple products, and fast start-up of applications. For specific functions and other detailed information, consult the following user's manuals. These manuals are required reading for design work. µPD784908 Subseries User's Manual - Hardware : U11787E 78K/IV Series User's Manual - Instruction : U10905E FEATURES • • • • 78K/IV series Internal PROM: 128 Kbytes Internal RAM: 4,352 bytes Supply voltage: VDD = 4.5 to 5.5 V (At main clock: fXX = 12.58 MHz, internal system clock = fXX : fCYK = 79 ns) VDD = 4.0 to 5.5 V (Other than above: fCYK = 159 ns) ORDERING INFORMATION Part number µPD78P4908GF-3BA Package Internal ROM 100-pin plastic QFP (14 × 20 mm) One-time PROM The information in this document is subject to change without notice. Document No. U11681EJ2V0DS00 (2nd edition) Date Published February 1999 N CP(K) Printed in Japan The mark shows major revised points. © 1996 µ PD78P4908 78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM : Under mass production : Under development I2C bus supported Multimaster I2C bus supported µPD784038Y µPD784225Y µPD784038 Standard models Enhanced internal memory capacity, pin compatible with the µPD784026 µPD784026 Enhanced A/D, 16-bit timer, and power management Multimaster I2C bus supported Multimaster I2C bus supported µPD784216Y µPD784218Y µPD784216 100 pins, enhanced I/O and internal memory capacity µPD784054 µPD784046 ASSP models Equipped with 10-bit A/D µ PD784955 For DC inverter control µ PD784938 µ PD784908 Equipped with IEBus controller TM Enhanced function of the µPD784908, enhanced internal memory capacity, added ROM correction Multimaster I2C bus supported µ PD784928Y µ PD784928 µPD784915 Enhanced function of the µPD784915 For software servo control, equipped with analog circuit for VCR, enhanced timer 2 µPD784225 80 pins, added ROM correction Data Sheet U11681EJ2V0DS00 µPD784218 Enhanced internal memory capacity, added ROM correction µ PD78P4908 FUNCTIONS (1/2) Item Function Number of basic instructions (mnemonics) 113 General-purpose register 8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping) Minimum instruction execution time • 320 ns/636 ns/1.27 µ s/2.54 µs (at 6.29 MHz) • 160 ns/320 ns/636 ns/1.27 µs (at 12.58 MHz) Internal memory ROM 128 Kbytes RAM 4,352 bytes Program and data: 1 Mbyte Memory space I/O ports Additional function pinsNote Total 80 Input 8 Input/output 72 LED direct drive outputs 24 Transistor direct drive 8 N-ch open drain 4 Real-time output ports 4 bits × 2, or 8 bits × 1 IEBus controller Incorporated (simple version) Timer/counter Timer/counter 0: (16 bits) Timer register × 1 Capture register × 1 Compare register × 2 Pulse output capability • Toggle output • PWM/PPG output • One-shot pulse output Timer/counter 1: (16 bits) Timer register × 1 Capture register × 1 Capture/compare register × 1 Compare register × 1 Real-time output port Timer/counter 2: (16 bits) Timer register × 1 Capture register × 1 Capture/compare register × 1 Compare register × 1 Pulse output capability • Toggle output • PWM/PPG output Timer 3: (16 bits) Timer register × 1 Compare register × 1 Clock timer Interrupt requests are generated at 0.5-second intervals. (A clock timer oscillator is incorporated.) Either the main clock (6.29 MHz/12.58 MHz) or real-time clock (32.768 kHz) can be selected as the input clock. Clock output Selected from f CLK, fCLK/2, f CLK/4, fCLK/8, or fCLK/16 (can be used as a 1-bit output port) PWM outputs 12-bit resolution × 2 channels Serial interface UART/IOE (3-wire serial I/O) : 2 channels (incorporating baud rate generator) CSI (3-wire serial I/O) : 2 channels Note Additional function pins are included in the I/O pins. Data Sheet U11681EJ2V0DS00 3 µ PD78P4908 (2/2) Item Function A/D converter 8-bit resolution × 8 channels Watchdog timer 1 channel Standby HALT/STOP/IDLE mode Interrupt Hardware source 27 (20 internal, 7 external (sampling clock variable input: 1)) Software source BRK or BRKCS instruction, operand error Nonmaskable 1 internal, 1 external Maskable 19 internal, 6 external • 4-level programmable priority • 3 operation statuses: vectored interrupt, macro service, context switching Power supply voltage • VDD = 4.5 to 5.5 V (At main clock: fXX = 12.58 MHz, internal system clock = fXX: fCYK = 79 ns) • VDD = 4.0 to 5.5 V (Other than above: fCYK = 159 ns) Package 4 100-pin plastic QFP (14 × 20 mm) Data Sheet U11681EJ2V0DS00 µ PD78P4908 CONTENTS 1. DIFFERENCES BETWEEN µPD78P4908 AND MASK ROM PRODUCTS ............................ 6 2. PIN CONFIGURATION (TOP VIEW) ......................................................................................... 7 3. BLOCK DIAGRAM ..................................................................................................................... 10 4. PIN FUNCTIONS ........................................................................................................................ 11 4.1 PINS FOR NORMAL OPERATING MODE .................................................................................... 11 4.2 PINS FOR PROM PROGRAMMING MODE (V PP ≥ +5 V or +12.5 V, RESET = L) .................... 14 4.2.1 Pin Functions ................................................................................................................. 14 4.2.2 Pin Functions ................................................................................................................. 15 I/O CIRCUITS FOR PINS AND HANDLING OF UNUSED PINS ................................................. 16 5. INTERNAL MEMORY SIZE SELECT REGISTER (IMS) .......................................................... 19 6. PROM PROGRAMMING ............................................................................................................ 20 4.3 6.1 OPERATION MODE ........................................................................................................................ 20 6.2 PROM WRITE SEQUENCE ............................................................................................................ 22 6.3 PROM READ SEQUENCE ............................................................................................................. 26 7. SCREENING ONE-TIME PROM PRODUCTS .......................................................................... 26 8. ELECTRICAL CHARACTERISTICS ......................................................................................... 27 9. PACKAGE DRAWING ................................................................................................................ 51 10. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 52 APPENDIX A DEVELOPMENT TOOLS.......................................................................................... 53 APPENDIX B CONVERSION SOCKET (EV-9200GF-100) PACKAGE DRAWING ..................... 56 APPENDIX C RELATED DOCUMENTS ......................................................................................... 58 Data Sheet U11681EJ2V0DS00 5 µ PD78P4908 1. DIFFERENCES BETWEEN µPD78P4908 AND MASK ROM PRODUCTS The µPD78P4908 is produced by replacing the mask ROM in the µ PD784907 or µ PD784908 with PROM to which data can be written. The functions of the µPD78P4908 are the same as those of the µ PD784907 or µPD784908 except for the PROM specification such as writing and verification, except that the PROM size can be changed to 96 or 128 Kbytes, and except that the internal RAM size can be changed to 3,584 or 4,352 bytes. Table 1-1 shows the differences between these products. Table 1-1. Differences Between the µPD78P4908 and Mask ROM Products Product name Item Internal program memory µ PD784907 µPD78P4908 • 128-Kbyte PROM • Can be changed to 96 µ PD784908 • 96-Kbyte mask ROM • 128-Kbyte mask ROM • 3,584-byte internal RAM • 4,352-byte internal RAM Kbytes by IMS Internal RAM • 4,352-byte internal RAM • Can be changed to 3,584 bytes by IMS Pin connection Pin functions related to writing or reading of PROM have been added to the µPD78P4908. Power supply voltage • VDD = 4.5 to 5.5 V • VDD = 4.0 to 5.5 V (At main clock: fXX = 12.58 MHz, internal system clock = f XX: fCYK = 79 ns • VDD = 4.0 to 5.5 V (Other than above: fCYK = 159 ns) (At main clock: fXX = 12.58 MHz, internal system clock = fXX : fCYK = 79 ns) • VDD = 3.5 to 5.5 V (Other than above: fCYK = 159 ns) Electrical characteristics 6 Partially differs between these products. Data Sheet U11681EJ2V0DS00 µ PD78P4908 2. PIN CONFIGURATION (TOP VIEW) (1) Normal operation mode • 100-pin plastic QFP (14 × 20 mm) P30/RxD/SI1 P27/SI0 P26/INTP5 P25/INTP4/ASCK/SCK1 P24/INTP3 P23/INTP2/CI P22/INTP1 P21/INTP0 P20/NMI TX RX AVSS AVREF1 AVDD P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 TESTNote 1 PWM1 PWM0 P17 P16 P15 P14/TxD2/SO2 P13/RxD2/SI2 P12/ASCK2/SCK2 P11 P10 ASTB/CLKOUT P90 P91 P92 P93 P94 P95 P96 P97 P40/AD0 P41/AD1 P42/AD2 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 74 7 73 8 9 72 71 10 70 11 12 69 13 68 14 67 15 66 65 16 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P64/RD P63/A19 P62/A18 P61/A17 P60/A16 P57/A15 P56/A14 P55/A13 P54/A12 VSS VDD P53/A11 P36/TO2 P37/TO3 P100 P101 P102 P103 P104 P105/SCK3 P106/SI3 P107/SO3 RESET XT2 XT1 VSS X2 X1 REGOFFNote 2 REGCNote 3 VDD P00 P01 P02 P03 P04 P05 P06 P07 P67/REFRQ/HLDAK P66/WAIT/HLDRQ P65/WR P34/TO0 P33/SO0 P32/SCK0 P31/TxD/SO1 P35/TO1 µPD78P4908GF-3BA Notes 1. Connect the TEST pin to VSS directly. 2. Connect the REGOFF pin to V SS directly (select regulator operation) 3. Connect the REGC pin to VSS through a 1-µ F capacitor. Data Sheet U11681EJ2V0DS00 7 µ PD78P4908 8 A8-A19 : Address bus PWM0, PWM1 : Pulse width modulation output AD0-AD7 : Address/data bus RD : Read strobe ANI0-ANI7 : Analog input REFRQ : Refresh request ASCK, ASCK2 : Asynchronous serial clock REGC : Regulator capacitance ASTB : Address strobe REGOFF : Regulator off AVDD : Analog power supply RESET : Reset AVREF1 : Reference voltage RX : IEBus receive data AVSS : Analog ground RxD, RxD2 : Receive data CI : Clock input SCK0-SCK3 : Serial clock CLKOUT : Clock output SI0-SI3 : Serial input HLDAK : Hold acknowledge SO0-SO3 : Serial output HLDRQ : Hold request TEST : Test INTP0-INTP5 : Interrupt from peripherals TO0-TO3 : Timer output NMI : Non-maskable interrupt TX : IEBus transmit data P00-P07 : Port 0 TxD, TxD2 : Transmit data P10-P17 : Port 1 VDD : Power supply P20-P27 : Port 2 VSS : Ground P30-P37 : Port 3 WAIT : Wait P40-P47 : Port 4 WR : Write strobe P50-P57 : Port 5 X1, X2 : Crystal (main system clock) P60-P67 : Port 6 XT1, XT2 : Crystal (watch) P70-P77 : Port 7 P90-P97 : Port 9 P100-P107 : Port 10 Data Sheet U11681EJ2V0DS00 µ PD78P4908 (2) PROM programming mode • 100-pin plastic QFP (14 × 20 mm) RESET OPEN VSS VSS OPEN VSS VDD D0 D1 D2 D3 D4 D5 D6 D7 (L) PGM CE OPEN VPP OPEN A0 A1 A2 A4 A3 A6 A5 VDD A11 A10 A16 A8 A7 A15 A14 A13 A12 VSS (L) 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 OE VSS (L) A9 VSS OPEN OPEN VSS VSS VDD OPEN 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 OPEN Caution L VSS OPEN µPD78P4908GF-3BA : Connect these pins separately to the VSS pins through 10-kΩ pull-down resistors. : To be connected to the ground. Open : Nothing should be connected on these pins. RESET: Set a low-level input. A0-A16 : Address bus RESET : Reset CE : Chip enable VDD : Power supply D0-D7 : Data bus VPP : Programming power supply OE : Output enable VSS : Ground PGM : Program Data Sheet U11681EJ2V0DS00 9 µ PD78P4908 3. BLOCK DIAGRAM NMI INTP0-INTP5 INTP3 TO0 TO1 INTP0 INTP1 INTP2/CI TO2 TO3 UART/IOE2 Programmable interrupt controller Baud-rate generator UART/IOE1 Timer/counter 0 (16 bits) Baud-rate generator Timer/counter 1 (16 bits) RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SCK0 Clocked serial interface SO0 SI0 Timer/counter 2 (16 bits) 78K /IV CPU core (RAM 512 bytes) ROM (128 Kbytes) Timer 3 (16 bits) SCK3 Clocked serial interface 3 Clock output SO3 SI3 ASTB /CLKOUT AD0-AD7 A8-A15 P00-P03 Real-time output port P04-P07 Bus interface PWM0 PWM PWM1 RAM (3,840 bytes) ANI0-ANI7 AVDD AVREF1 A /D converter AVSS INTP5 TX IEBus controller RX RESET TEST X1 X2 REGC REGOFF VPPNote VDD VSS System control (regulator) Port 0 P00-P07 Port 1 P10-P17 Port 2 P20-P27 Port 3 P30-P37 Port 4 P40-P47 Port 5 P50-P57 Port 6 P60-P67 Port 7 P70-P77 Port 9 P90-P97 Watchdog timer Port 10 XT1 Watch timer XT2 Note In the PROM programming mode. 10 A16-A19 RD WR WAIT/HLDRQ REFRQ/HLDAK D0-D7Note A0-A16Note CENote OENote PGMNote Data Sheet U11681EJ2V0DS00 P100-P107 µ PD78P4908 4. PIN FUNCTIONS 4.1 PINS FOR NORMAL OPERATING MODE (1) Port pins (1/2) I/O Pin Function Also used as P00-P07 I/O — Port 0 (P0): • 8-bit I/O port. • Functions as a real-time output port (4 bits × 2). • Inputs and outputs can be specified bit by bit. • The use of built-in pull-up resistors can be simultaneously specified by software for all pins in input mode. • Can drive a transistor. P10 I/O — Port 1 (P1): • 8-bit I/O port. • Inputs and outputs can be specified bit by bit. • The use of built-in pull-up resistors can be simultaneously specified by software for all pins in input mode. • Can drive LED. — P11 P12 ASCK2/SCK2 P13 RxD2/SI2 P14 TxD2/SO2 — P15-P17 P20 Input NMI P21 INTP0 P22 INTP1 P23 INTP2/CI P24 INTP3 P25 INTP4/ASCK/SCK1 P26 INTP5 P27 SI0 P30 I/O RxD/SI1 P31 TxD/SO1 P32 SCK0 P33 SO0 P34-P37 TO0-TO3 P40-P47 I/O AD0-AD7 Port 2 (P2): • 8-bit input-only port. • P20 does not function as a general-purpose port (nonmaskable interrupt). However, the input level can be checked by an interrupt service routine. • The use of built-in pull-up resistors can be specified by software for pins P22 to P27 (in units of 6 bits). • The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 input/output pin by CSIM1. Port 3 (P3): • 8-bit I/O port. • Inputs and outputs can be specified bit by bit. • The use of built-in pull-up resistors can be simultaneously specified by software for all pins in input mode. • P32 and P33 can be set as the N-ch open-drain pin. Port 4 (P4): • 8-bit I/O port. • Inputs and outputs can be specified bit by bit. • The use of built-in pull-up resistors can be simultaneously specified by software for all pins in input mode. • Can drive LED. Data Sheet U11681EJ2V0DS00 11 µ PD78P4908 (1) Port pins (2/2) Pin I/O Also used as Function P50-P57 I/O A8-A15 Port 5 (P5): • 8-bit I/O port. • Inputs and outputs can be specified bit by bit. • The use of built-in pull-up resistors can be simultaneously specified by software for all pins in input mode. • Can drive LED. P60-P63 I/O A16-A19 Port 6 (P6): • 8-bit I/O port. • Inputs and outputs can be specified bit by bit. • The use of built-in pull-up resistors can be simultaneously specified by software for all pins in input mode. P64 RD P65 WR P66 WAIT/HLDRQ P67 REFRQ/HLDAK P70-P77 I/O ANI0-ANI7 P90-P97 I/O — Port 9 (P9): • 8-bit I/O port. • Inputs and outputs can be specified bit by bit. • The use of built-in pull-up resistors can be simultaneously specified by software for all pins in input mode. P100-P104 I/O — Port 10 (P10): • 8-bit I/O port. • Inputs and outputs can be specified bit by bit. • The use of built-in pull-up resistors can be simultaneously specified by software for all pins in input mode. • P105 and P107 can be set as the N-ch open-drain pin. P105 SCK3 P106 SI3 P107 SO3 12 Port 7 (P7): • 8-bit I/O port. • Inputs and outputs can be specified bit by bit. Data Sheet U11681EJ2V0DS00 µ PD78P4908 (2) Non-port pins (1/2) Pin I/O TO0-TO3 Output P34-P37 Timer output CI Input P23/INTP2 Input of a count clock for timer/counter 2 RxD Input P30/SI1 Serial data input (UART0) P13/SI2 Serial data input (UART2) P31/SO1 Serial data output (UART0) P14/SO2 Serial data output (UART2) P25/INTP4/SCK1 Baud rate clock input (UART0) P12/SCK2 Baud rate clock input (UART2) P27 Serial data input (3-wire serial I/O 0) SI1 P30/RxD Serial data input (3-wire serial I/O 1) SI2 P13/RxD2 Serial data input (3-wire serial I/O 2) SI3 P106 Serial data input (3-wire serial I/O 3) P33 Serial data output (3-wire serial I/O 0) SO1 P31/TxD Serial data output (3-wire serial I/O 1) SO2 P14/TxD2 Serial data output (3-wire serial I/O 2) SO3 P107 Serial data output (3-wire serial I/O 3) P32 Serial clock I/O (3-wire serial I/O 0) SCK1 P25/INTP4/ASCK Serial clock I/O (3-wire serial I/O 1) SCK2 P12/ASCK2 Serial clock I/O (3-wire serial I/O 2) SCK3 P105 Serial clock I/O (3-wire serial I/O 3) P20 External interrupt request RxD2 TxD Output TxD2 ASCK Input ASCK2 SI0 SO0 SCK0 NMI Input Output I/O Input Function Also used as — INTP0 P21 • Input of a count clock for timer/counter 1 • Capture/trigger signal for CR11 or CR12 INTP1 P22 • Input of a count clock for timer/counter 2 • Capture/trigger signal for CR22 INTP2 P23/CI • Input of a count clock for timer/counter 2 • Capture/trigger signal for CR21 INTP3 P24 • Input of a count clock for timer/counter 0 • Capture/trigger signal for CR02 INTP4 P25/ASCK/SCK1 INTP5 P26 — Input of a conversion start trigger for A/D converter AD0-AD7 I/O P40-P47 Time multiplexing address/data bus (for connecting external memory) A8-A15 Output P50-P57 High-order address bus (for connecting external memory) A16-A19 Output P60-P63 High-order address during address expansion (for connecting external memory) RD Output P64 Strobe signal output for reading the contents of external memory WR Output P65 Strobe signal output for writing on external memory WAIT Input P66/HLDRQ Wait signal insertion REFRQ Output P67/HLDAK Refresh pulse output to external pseudo static memory HLDRQ Input P66/WAIT Input of bus hold request HLDAK Output P67/REFRQ Output of bus hold response ASTB Output CLKOUT Latch timing output of time multiplexing address (A0-A7) (for connecting external memory) Data Sheet U11681EJ2V0DS00 13 µ PD78P4908 (2) Non-port pins (2/2) Pin I/O Function CLKOUT Output PWM0 Output — PWM output 0 PWM1 Output — PWM output 1 RX Input — Data input (IEBus) TX Output — Data output (IEBus) Also used as Clock output ASTB REGC — — Capacitor connection for stabilizing the regulator output/Power supply when the regulator is stopped. Connect to VSS via a 1-µF capacitor. REGOFF — — Signal for specifying regulator operation. Directly connect to V SS (regulator selected). RESET Input — Chip reset X1 Input — Crystal input for system clock oscillation (A clock pulse can also be input to the X1 pin.) — Real-time clock connection X2 — XT1 Input XT2 — ANI0-ANI7 Input AVREF1 — P70-P77 — Analog voltage inputs for the A/D converter — Application of A/D converter reference voltage AVDD Positive power supply for the A/D converter AVSS Ground for the A/D converter VDD Positive power supply VSS Ground TEST Input Directly connect to V SS . (The TEST pin is for the IC test.) PINS FOR PROM PROGRAMMING MODE (V PP ≥ +5 V or +12.5 V, RESET = L) 4.2 4.2.1 Pin Functions I/O Pin name VPP RESET — Input Function PROM programming mode selection High voltage input during program write or verification PROM programming mode selection Address bus A0-A16 D0-D7 I/O Data bus CE Input PROM enable input/program pulse input OE Read strobe input to PROM PGM Program/program inhibit input during PROM programming mode VDD — Positive power supply VSS — GND 14 Data Sheet U11681EJ2V0DS00 µ PD78P4908 4.2.2 Pin Functions (1) VPP (Programming power supply): Input Input pin for setting the µ PD78P4908 to the PROM programming mode. When the input voltage on this pin is +6.5 V or more and when RESET input goes low, the µ PD78P4908 enters the PROM programming mode. When CE is made low for VPP = +12.5 V and OE = high, program data on D0 to D7 can be written into the internal PROM cell selected by A0 to A16. (2) RESET (Reset): Input Input pin for setting the µ PD78P4908 to the PROM programming mode. When input on this pin is low, and when the input voltage on the V PP pin goes +5 V or more, the µPD78P4908 enters the PROM programming mode. (3) A0 to A16 (Address bus): Input Address bus that selects an internal PROM address (0000H to 1FFFFH) (4) D0 to D7 (Data bus): I/O Data bus through which a program is written on or read from internal PROM (5) CE (Chip enable): Input This pin inputs the enable signal from internal PROM. When this signal is active, a program can be written or read. (6) OE (Output enable): Input This pin inputs the read strobe signal to internal PROM. When this signal is made active for CE = low, a onebyte program in the internal PROM cell selected by A0 to A16 can be read onto D0 to D7. (7) PGM (Program): Input The input pin for the operation mode control signal of the internal PROM. Upon activation, writing to the internal PROM is enabled. Upon inactivation, reading from the internal PROM is enabled. (8) VDD Positive power supply pin (9) VSS Ground potential pin Data Sheet U11681EJ2V0DS00 15 µ PD78P4908 4.3 I/O CIRCUITS FOR PINS AND HANDLING OF UNUSED PINS Table 4-1 describes the types of I/O circuits for pins and the handling of unused pins. Figure 4-1 shows the configuration of these various types of I/O circuits. Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (1/2) I/O circuit type Pin P00-P07 5-A I/O I/O Input state: To be connected to VDD Output state: To be left open Input To be connected to V DD or V SS P10, P11 P12/ASCK2/SCK2 8-A P13/R XD2/SI2 5-A Recommended connection method for unused pins P14/TXD2/SO2 P15-P17 P20/NMI 2 P21/INTP0 P22/INTP1 2-A To be connected to V DD P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 8-A I/O Input state: To be connected to V DD Output state: To be left open P26/INTP5 2-A Input To be connected to V DD 5-A I/O Input state: To be connected to V DD Output state: To be left open I/O Input state: Output To be left open P27/SI0 P30/R XD/SI1 P31/TXD/SO1 P32/SCK0 10-A P33/SO0 P34/TO0-P37/TO3 5-A P40/AD0-P47/AD7 P50/A8-P57/A15 P60/A16-P63/A19 P64/RD P65/WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK P70/ANI0-P77/ANI7 20 P90-P97 5-A To be connected to VDD or VSS Output state : To be left open P100-P104 P105/SCK3 10-A P106/SI3 8-A P107/SO3 10-A ASTB/CLKOUT 4 16 Data Sheet U11681EJ2V0DS00 µ PD78P4908 Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (2/2) Pin I/O I/O circuit type RESET 2 TEST 1 XT2 Recommended connection method for unused pins Input — To be connected to V SS directly — — To be left open XT1 Input To be connected to V SS PWM0, PWM1 3 Output To be left open 1 Input To be connected to V DD or V SS 3 Output To be left open RX TX AVREF1 — — To be connected to V SS AVSS To be connected to V DD AVDD Caution When the I/O mode of an I/O dual-function pin is unpredictable, connect the pin to VDD through a resistor of 10 to 100 kΩ (particularly when the voltage of the reset input pin becomes higher than that of the low level input at power-on or when I/O is switched by software). Remark Since type numbers are consistent in the 78K series, those numbers are not always serial in each product. (Some circuits are not included.) Data Sheet U11681EJ2V0DS00 17 µ PD78P4908 Figure 4-1. I/O Circuits for Pins Type 1 Type 2-A VDD VDD P Pull-up enable P IN N IN Type 2 Schmitt trigger input with hysteresis characteristics IN Type 5-A Schmitt trigger input with hysteresis characteristics Type 3 VDD Pull-up enable VDD P VDD P Data P-ch Data IN/OUT OUT Output disable N-ch N Input enable Type 4 VDD Data Type 8-A P OUT Output disable N VDD Pull-up enable P VDD P Data Push-pull output which can output high impedance (both the positive and negative channels are off.) IN/OUT Output disable Type 10-A N VDD Pull-up enable P Type 20 VDD VDD P Data Data P IN/OUT Open drain Output disable IN/OUT N Output disable N Comparator + – Type 12 Analog output voltage OUT N 18 VREF (Threshold voltage) P Input enable Data Sheet U11681EJ2V0DS00 P N µ PD78P4908 5. INTERNAL MEMORY SIZE SELECT REGISTER (IMS) This register enables the software to avoid using part of the internal memory. The IMS can be set to establish the same memory mapping as used in mask ROM products that have different internal memory (ROM and RAM) configurations. The IMS is set using 8-bit memory operation instructions. A RESET input sets the IMS to FFH. Figure 5-1. Internal Memory Size Select Register (IMS) IMS 7 6 5 4 3 2 1 0 Address Reset value R/W IMS7 IMS6 IMS5 IMS4 IMS3 IMS2 IMS1 IMS0 0FFFCH FFH W IMS0-7 Memory size FFH Same as the µPD784908 EEH Same as the µPD784907 Other than the above Not to be set The IMS is not contained in a mask ROM product (µ PD784907 or µ PD784908). But the action is not affected if the write command to the IMS is executed to the mask ROM product. Data Sheet U11681EJ2V0DS00 19 µ PD78P4908 6. PROM PROGRAMMING The µ PD78P4908 has an on-chip 128-KB PROM device for use as program memory. When programming, set the VPP and RESET pins for PROM programming mode. See 2. PIN CONFIGURATION (TOP VIEW) (2) PROM programming mode with regard to handling of other, unused pins. 6.1 OPERATION MODE PROM programming mode is selected when +6.5 V is added to the VDD pin, +12.5 V is added to the VPP pin, or low-level input is added to the RESET pin. This mode can be set to operation mode by setting the CE pin, OE pin, and PGM pin as shown in Table 6-1 below. In addition, the PROM contents can be read by setting read mode. Table 6-1. PROM Programming Operation Mode Pin RESET V PP VDD CE OE PGM D0-D7 Operation mode Page data latch H L H Data input Page write H H L High impedance Byte write L H L Data input Program verify L L H Data output Program inhibit × H H High impedance × L L L L H Data output Output disable L H × High impedance Standby H × × High impedance Read L +12.5 V +5 V +6.5 V +5 V Remark × = L or H 20 Data Sheet U11681EJ2V0DS00 µ PD78P4908 (1) Read mode Set CE to L and OE to L to set read mode. (2) Output disable mode Set OE to H to set high impedance for data output and output disable mode. Consequently, if several µ PD78P4908 devices are connected to a data bus, the OE pins can be controlled to select data output from any of the devices. (3) Standby mode Set CE to H to set standby mode. In this mode, data output is set to high impedance regardless of the OE setting. (4) Page data latch mode At the beginning of page write mode, set CE to H, PGM to H, and OE to L to set page data latch mode. In this mode, 1 page (4 bytes) of data are latched to the internal address/data latch circuit. (5) Page write mode After latching the address and data for one page (4 bytes) using page data latch mode, adding a 0.1 ms program pulse (active, low) to the PGM pin with both CE and OE set to H causes page write to be executed. Later, setting both CE and OE to L causes program verification to be executed. If programming is not completed after one program pulse, the write and verify operations may be repeated X times (where X ≤ 10). (6) Byte write mode Adding a 0.1 ms program pulse (active, low) to the PGM pin with setting CE to L and OE to H causes byte write to be executed. Later, setting OE to L causes program verification to be executed. If programming is not completed after one program pulse, the write and verify operations may be repeated X times (where X ≤ 10). (7) Program verify mode Set CE to L, PGM to H, and OE to L to set program verify mode. Use verify mode for verification following each write operation. (8) Program inhibit mode Program inhibit mode is used to write to a single device when several µPD78P4908 devices are connected in parallel to OE , V PP, and D0 to D7 pins. Use the page write mode or byte write mode described above for each write operation. Write operations cannot be done for devices in which the PGM pin has been set to H. Data Sheet U11681EJ2V0DS00 21 µ PD78P4908 6.2 PROM WRITE SEQUENCE Figure 6-1. Page Program Mode Flowchart Start Address = G VDD = +6.5 V, VPP = +12.5 V X=0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Address = Address + 1 Latch No X=X+1 X = 10 ? Yes 0.1 ms program pulse Verify 4 bytes Fail Pass No Address = N ? Yes VDD = 4.0 to 5.5 V, VPP = VDD Pass Verify all bytes Fail All pass Write end Remark G = Start address N = Program end address 22 Data Sheet U11681EJ2V0DS00 Defective µ PD78P4908 Figure 6-2. Page Program Mode Timing Page data latch Page program Program verify A2-A16 A0, A1 Hi-Z Hi-Z D0-D7 Data input Data output VPP VPP VDD VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL Data Sheet U11681EJ2V0DS00 23 µ PD78P4908 Figure 6-3. Byte Program Mode Flowchart Start Address = G VDD = +6.5 V, VPP = +12.5 V X= 0 No X= X + 1 X = 10 ? Yes 0.1 ms program pulse Address = Address + 1 Verify Fail Pass No Address = N ? Yes VDD = 4.0 to 5.5 V, VPP = VDD Pass Verify all bytes Fail All pass Write end Remark G = Start address N = Program end address 24 Data Sheet U11681EJ2V0DS00 Defective µ PD78P4908 Figure 6-4. Byte Program Mode Timing Program Program verify A0-A16 D0-D7 Hi-Z Data input Hi-Z Data output Hi-Z VPP VPP VDD VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL Cautions 1. Add VDD before VPP , and turn off the VDD after V PP. 2. Do not allow VPP to exceed 13.5 V including overshoot. 3. Reliability problems may result if the device is inserted or pulled out while 12.5 V is applied at VPP. Data Sheet U11681EJ2V0DS00 25 µ PD78P4908 6.3 PROM READ SEQUENCE Follow this sequence to read the PROM contents to an external data bus (D0 to D7). (1) Set the RESET pin to low level and add 5 V to the VPP pin. See 2. PIN CONFIGURATION (TOP VIEW) (2) PROM programming mode with regard to handling of other, unused pins. (2) Add 5 V to the VDD and VPP pins. (3) Input the data address to be read to pins A0 to A16. (4) Set read mode. (5) Output the data to pins D0 to D7. Figure 6-5 shows the timing of steps (2) to (5) above. Figure 6-5. PROM Read Timing A0-A16 Address input CE (input) OE (input) D0-D7 Hi-Z Data output Hi-Z 7. SCREENING ONE-TIME PROM PRODUCTS NEC cannot execute a complete test of one-time PROM products ( µPD78P4908GF-3BA) due to their structure before shipment. It is recommended that you screen (verify) PROM products after writing necessary data into them and storing them at 125°C for 24 hours. 26 Data Sheet U11681EJ2V0DS00 µ PD78P4908 8. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (T A = 25 °C) Parameter Supply voltage Input voltage Symbol Conditions Rating Unit –0.3 to +7.0 V AVDD –0.3 to VDD + 0.3 V AVSS –0.3 to +0.3 V –0.3 to VDD + 0.3 V –0.3 to +13.5 V VDD VI1 For pins other than V PP, A9 VI2 VPP, A9 Analog input voltage VAN AVSS – 0.3 to AVREF1 + 0.3 V Output voltage VO –0.3 to VDD + 0.3 V Output low current I OL One pin 10 mA Total for the P00-P07, P30P37, P54-P57, P60-P67, and P100-P107 pins 50 mA Total for the P10-P17, P40P47, P50-P53, P70-P77, P90-P97, PWM0, PWM1, and TX pins 50 mA One pin –6 mA Total for the P00-P07, P30P37, P54-P57, P60-P67, and P100-P107 pins –30 mA Total for the P10-P17, P40P47, P50-P53, P70-P77, P90-P97, PWM0, PWM1, and TX pins –30 mA –0.3 to VDD + 0.3 V Output high current I OH A/D converter reference input voltage AVREF1 Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. Always use the product within its rated values. Remark Unless otherwise stated, the characteristics of a dual-function pin are the same as those of a port pin. Data Sheet U11681EJ2V0DS00 27 µ PD78P4908 OPERATING CONDITIONS • Operating ambient temperature (T A): –40 °C to +85 °C • Power supply voltage and clock cycle time: See Figure 8-1. • Internal regulator operation selected (REGOFF pin: low level) Figure 8-1. Power Supply Voltage and Clock Cycle Time 10,000 Clock cycle time tCYK [ns] 4,000 1,000 Guaranteed operating range 159 100 79 10 0 1 2 3 4 5 Power supply voltage [V] 6 7 CAPACITANCE (TA = 25 °C, VDD = VSS = 0 V) Parameter Symbol Input capacitance CI Output capacitance CO I/O capacitance CIO 28 Conditions f = 1 MHz 0 V on pins other than measured pins Data Sheet U11681EJ2V0DS00 MIN. TYP. MAX. Unit 15 pF 15 pF 15 pF µ PD78P4908 MAIN OSCILLATOR CHARACTERISTICS (T A = –40 °C to +85 °C, VDD = 4.0 to 5.5 V, V SS = 0 V) Parameter Oscillator frequency Symbol Conditions fXX Ceramic or crystal resonator MIN. MAX. Unit 2 12.58 MHz Caution When using the clock generator, run wires according to the following rules to avoid effects such as stray capacitance: • Minimize the wiring length. • Never cause the wires to cross other signal lines. • Never cause the wires to run near a line carrying a large varying current. • The grounding point of the capacitor of the oscillator circuit must always be the same potential as VSS1. Never connect the capacitor to a ground pattern carrying a large current. • Never extract a signal from the oscillator. Remark Connect a 12.582912 or 6.291456 MHz oscillator to operate the internal clock timer with the main clock. CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 °C to +85 °C, VDD = 4.0 to 5.5 V, VSS = 0 V) Parameter Symbol Conditions Oscillator frequency f XT Ceramic or crystal resonator Oscillation settling time t SXT VDD = 4.5 to 5.5 V MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s 10 s Oscillation hold voltage VDDXT 4.0 5.5 V Watch timer operating voltage VDDW 4.0 5.5 V Data Sheet U11681EJ2V0DS00 29 µ PD78P4908 DC CHARACTERISTICS (TA = –40 °C to +85 °C, VDD = AV DD = 4.0 to 5.5 V, V SS = AVSS = 0 V) (1/2) Parameter Input low voltageNote 5 Input high voltage Output low voltage Output high voltage Symbol Conditions MIN. TYP. MAX. Unit VIL1 For pins other than those described in Notes 1 and 2 –0.3 0.3 VDD V VIL2 For pins described in Note 1 –0.3 0.2 VDD V VIL3 VDD = 4.5 to 5.5 V For pins described in Note 2 –0.3 +0.8 V VIH1 For pins other than those described in Notes 1 and 2 0.7 VDD VDD + 0.3 V VIH2 For pins described in Note 1 0.8 VDD VDD + 0.3 V VIH3 VDD = 4.5 to 5.5 V For pins described in Note 2 2.2 VDD + 0.3 V VOL1 I OL = 20 µ A 0.1 V I OL = 100 µ A 0.2 V I OL = 2 mA 0.4 V VOL2 I OL = 8 mA For pins described in Note 4 VDD = 4.5 to 5.5 V 1.0 V VOH1 I OH = -20 µ A VDD – 0.1 V I OH = -100 µA VDD – 0.2 V I OH = -2 mA VDD – 1.0 V VDD = 4.5 to 5.5 V I OH = -5 mA For pins described in Note 3 VDD – 2.4 V VOH2 Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, P33/SO0, P105/SCK3, P106/SI3, P107/SO3, XT1, XT2 2. P40/AD0-P47/AD7, P50/A8-P57/A15, P60/A16-P67/REFRQ/HLDAK, P00-P07 3. P00-P07 4. P10-P17, P40/AD0-P47/AD7, P50/A8-P57/A15 5. Other than pull-up resistors 30 Data Sheet U11681EJ2V0DS00 µ PD78P4908 DC CHARACTERISTICS (TA = –40 °C to +85 °C, VDD = AVDD = 4.0 to 5.5 V, VSS = AVSS = 0 V) (2/2) Parameter Input leakage current Conditions Symbol I LI1 0 V ≤ V I ≤ VDD I LI2 Output leakage current VDD supply current Note I LO 0 V ≤ V O ≤ VDD I DD1 Operation mode I DD2 I DD3 Pull-up resistor RL HALT mode IDLE mode MIN. TYP. MAX. Unit For pins other than X1 and XT1 ±10 µA X1, XT1 ±20 µA ±10 µA f XX = 12.58 MHz VDD = 4.5 to 5.5 V f XX = 6.29 MHz VDD = 4.0 to 5.5 V 20 40 mA 10 20 mA f XX = 12.58 MHz VDD = 4.5 to 5.5 V f CLK = fXX/8 (STBC = B1H) Peripheral operation stops. 5.2 10.4 mA f XX = 6.29 MHz VDD = 4.0 to 5.5 V f CLK = fXX/8 (STBC = 31H) Peripheral operation stops. 2.6 5.2 mA f XX = 12.58 MHz VDD = 4.5 to 5.5 V f XX = 6.29 MHz VDD = 4.0 to 5.5 V 2.4 4.8 mA 1.8 3.6 mA 80 kΩ 15 VI = 0 V Note These values are valid when the internal regulator is ON (REGOFF pin = low level). They do not include the AV DD and AVREF1 currents. Data Sheet U11681EJ2V0DS00 31 µ PD78P4908 AC CHARACTERISTICS (TA = –40 °C to +85°C, VDD = AV DD = 4.0 to 5.5 V, AVSS = VSS = 0 V) (1) Read/write operation Parameter Symbol Conditions MIN. MAX. Unit Address setup time (to ASTB↓) t SAST VDD = 5.0 V (0.5 + a)T – 11 29 ns ASTB high-level width t WSTH VDD = 5.0 V (0.5 + a)T – 17 23 ns Address hold time (to ASTB↓) t HSTLA VDD = 5.0 V 0.5T – 19 21 ns Address hold time (to RD↑) t HRA VDD = 5.0 V 0.5T – 14 26 ns Delay from address to RD↓ t DAR VDD = 5.0 V (1 + a)T – 5 74 ns Address float time (to RD↓) t FRA 0 ns Delay from address to data input t DAID VDD = 5.0 V (2.5 + a + n)T – 37 400 ns Delay from ASTB↓ to data input t DSTID VDD = 5.0 V (2 + n)T – 35 283 ns Delay from RD↓ to data input t DRID VDD = 5.0 V (1.5 + n)T – 40 238 ns Delay from ASTB↓ to RD↓ t DSTR VDD = 5.0 V 0.5T – 9 Data hold time (to RD↑) t HRID Delay from RD↑ to address active t DRA VDD = 5.0 V Delay from RD↑ to ASTB↑ t DRST RD low-level width 31 ns 0 ns 0.5T – 2 38 ns VDD = 5.0 V 0.5T – 9 31 ns t WRL VDD = 5.0 V (1.5 + n)T – 25 94 ns Delay from address↓ to WR↓ t DAW VDD = 5.0 V (1 + a)T – 5 74 ns Address hold time (to WR↑) t HWA VDD = 5.0 V 0.5T – 14 26 ns Delay from ASTB↓ to data output t DSTOD VDD = 5.0 V 0.5T + 15 Delay from WR↓ to data output t DWOD 55 ns 15 ns Delay from ASTB↓ to WR↓ t DSTW VDD = 5.0 V 0.5T – 9 31 ns Data setup time (to WR↑) t SODWR VDD = 5.0 V (1.5 + n)T – 20 99 ns Data hold time (to WR↑) t HWOD VDD = 5.0 V 0.5T – 14 26 ns Delay from WR↑ to ASTB↑ t DWST VDD = 5.0 V 0.5T – 9 31 ns WR low-level width t WWL VDD = 5.0 V (1.5 + n)T – 25 94 ns Remark T: 32 tCYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.) a: 1 during address wait, otherwise, 0 n: Number of wait states (n ≥ 0) Data Sheet U11681EJ2V0DS00 µ PD78P4908 (2) External wait timing Parameter Symbol Conditions Delay from address to WAIT↓ t DAWT input VDD = 5.0 V (2 + a)T – 40 Delay from ASTB↓ to WAIT↓ input t DSTWT VDD = 5.0 V 1.5T – 40 Hold time from ASTB↓ to WAIT t HSTWT VDD = 5.0 V (0.5 + n)T + 5 Delay from ASTB↓ to WAIT↑ t DSTWTH VDD = 5.0 V (1.5 + n)T – 40 Delay from RD↓ to WAIT↓ input t DRWTL VDD = 5.0 V T – 40 Hold time from RD↓ to WAIT t HRWT VDD = 5.0 V nT + 5 Delay from RD↓ to WAIT↑ MIN. MAX. Unit 198 ns 79 ns ns 124 238 ns 39 ns ns 84 198 ns 35 ns t DRWTH VDD = 5.0 V (1 + n)T – 40 Delay from WAIT↑ to data input t DWTID VDD = 5.0 V 0.5T – 5 Delay from WAIT↑ to RD↑ t DWTR VDD = 5.0 V 0.5T 40 ns Delay from WAIT↑ to WR↑ t DWTW VDD = 5.0 V 0.5T 40 ns Delay from WR↓ to WAIT↓ input t DWWTL VDD = 5.0 V T – 40 Hold time from WR↓ to WAIT t HWWT VDD = 5.0 V nT + 5 Delay from WR↓ to WAIT↑ t DWWTH VDD = 5.0 V (1 + n)T – 40 Remark T: 39 ns ns 84 198 ns tCYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.) a: 1 during address wait, otherwise, 0 n: Number of wait states (n ≥ 0) Data Sheet U11681EJ2V0DS00 33 µ PD78P4908 (3) Bus hold timing Parameter Delay from HLDRQ↑ to float Symbol Conditions MIN. MAX. Unit VDD = 5.0 V (2 + 4 + a + n)T + 50 765 ns Delay from HLDRQ↑ to HLDAK↑ t DHQHHAH VDD = 5.0 V (3 + 4 + a + n)T + 30 825 ns Delay from float to HLDAK↑ VDD = 5.0 V T + 30 109 ns Delay from HLDRQ↓ to HLDAK↓ t DHQLHAL VDD = 5.0 V 2T + 40 199 ns Delay from HLDRQ↓ to active VDD = 5.0 V T – 20 Remark T: t FHQC t DCFHA t DHAC ns 59 tCYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.) a: 1 during address wait, otherwise, 0 n: Number of wait states (n ≥ 0) (4) Refresh timing Parameter Symbol Conditions Random read/write cycle time t RC VDD = 5.0 V 3T REFRQ low-level pulse width t WRFQL VDD = 5.0 V Delay from ASTB↓ to REFRQ t DSTRFQ Delay from RD↑ to REFRQ MIN. MAX. Unit 238 ns 1.5T – 25 94 ns VDD = 5.0 V 0.5T – 9 31 ns t DRRFQ VDD = 5.0 V 1.5T – 9 110 ns Delay from WR↑ to REFRQ t DWRFQ VDD = 5.0 V 1.5T – 9 110 ns Delay from REFRQ↑ to ASTB t DRFQST VDD = 5.0 V 0.5T – 9 31 ns REFRQ high-level pulse width t WRFQH VDD = 5.0 V 1.5T – 25 94 ns Remark T: tCYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.) 34 Data Sheet U11681EJ2V0DS00 µ PD78P4908 SERIAL OPERATION (TA = –40 °C to +85 °C, VDD = 4.0 to 5.5 V, AVSS = VSS = 0 V) (1) CSI, CSI3 Parameter Symbol Serial clock cycle time (SCK0, SCK3) t CYSK0 Conditions Input Output Serial clock low-level width (SCK0, SCK3) t WSKL0 Input Output Serial clock high-level width (SCK0, SCK3) t WSKH0 Input Output Setup time for SI0, SI3 (to SCK0, SCK3↑) t SSSK0 Hold time for SI0, SI3 (to SCK0, SCK3↑) t HSSK0 Output delay time for SO0, SO3 (to SCK0, SCK3↓) t DSBSK1 t DSBSK2 Output hold time for SO0, SO3 (to SCK0, SCK3↑) t HSBSK MIN. MAX. Unit f CLK = fXX 8/f XX ns Other than f CLK = fXX 4/f CLK ns Other than f CLK = fXX/8 8/f XX ns f CLK = fXX/8 16/fXX ns f CLK = fXX 4/f XX – 40 ns Other than f CLK = fXX 2/f CLK – 40 Other than f CLK = fXX/8 4/f XX – 40 f CLK = fXX/8 8/f XX – 40 f CLK = fXX 4/f XX – 40 Other than f CLK = fXX 2/f CLK – 40 Other than f CLK = fXX/8 4/f XX – 40 f CLK = fXX/8 8/f XX – 40 µs ns µs 80 ns External clock 1/fCLK + 80 ns Internal clock 80 External clock 0 1/fCLK + 150 ns Internal clock 0 150 ns Open-drain output External clock 0 1/fCLK + 400 ns R L = 1 kΩ Internal clock 0 400 ns CMOS push-pull output When data is transferred 0.5tCYSK0 – 40 ns Remarks 1. The values in this table are those when fXX = 12.58 MHz, CL is 100 pF. 2. fCLK : System clock frequency (selectable from fXX , fXX/2, fXX /4, and fXX/8 by the standby control 3. fXX : Oscillation frequency (f XX = 12.58 MHz or f XX = 6.29 MHz) register (STBC)) Data Sheet U11681EJ2V0DS00 35 µ PD78P4908 (2) IOE1, IOE2 (TA = –40 °C to +85 °C, VDD = AV DD = 4.0 to 5.5 V, AVSS = VSS = 0 V) Parameter Serial clock cycle time (SCK1, SCK2) Serial clock low-level width (SCK1, SCK2) Serial clock high-level width (SCK1, SCK2) Symbol t CYSK1 t WSKL1 t WSKH1 Conditions Input VDD = 4.5 to 5.5 V Output Internal, divided by 8 Input VDD = 4.5 to 5.5 V Output Internal, divided by 8 Input VDD = 4.5 to 5.5 V Output Internal, divided by 8 MIN. MAX. Unit 640 ns 1,280 ns T ns 280 ns 600 ns 0.5T – 40 ns 280 ns 600 ns 0.5T – 40 ns Setup time for SI1 and SI2 (to SCK1, SCK2↑) t SSSK1 40 ns Hold time for SI1 and SI2 (to SCK1, SCK2↑) t HSSK1 40 ns Output delay time for SO1 and t DSOSK SO2 (to SCK1, SCK2↓) 0 Output hold time for SO1 and SO2 (to SCK1, SCK2↑) t HSOSK When data is transferred 50 ns ns 0.5t CYSK1 – 40 Remarks 1. The values in this table are those when CL is 100 pF. 2. T: Serial clock cycle set by software. The minimum value is 8/fXX . (3) UART, UART2 (TA = –40 °C to +85 °C, VDD = AVDD = 4.0 to 5.5 V, AVSS = VSS = 0 V) Parameter ASCK clock input cycle time ASCK clock low-level width ASCK clock high-level width 36 Symbol t CYASK t WASKL t WASKH Conditions VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V Data Sheet U11681EJ2V0DS00 MIN. MAX. Unit 160 ns 320 ns 65 ns 120 ns 65 ns 120 ns µ PD78P4908 CLOCK OUTPUT OPERATION (TA = –40 °C to +85°C, VDD = AVDD = 4.0 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit 32,000 ns CLKOUT cycle time t CYCL nT 79 CLKOUT low-level width t CLL VDD = 4.5 to 5.5 V, 0.5T – 10 30 ns 0.5T – 20 20 ns VDD = 4.5 to 5.5 V, 0.5T – 10 30 ns 0.5T – 20 20 ns CLKOUT high-level width CLKOUT rise time t CLR CLKOUT fall time Remark n: T: t CLH t CLF 4.5 V ≤ VDD < 5.5 V 10 ns 4.0 V ≤ VDD < 4.5 V 20 ns 4.5 V ≤ VDD < 5.5 V 10 ns 4.0 V ≤ VDD < 4.5 V 20 ns MAX. Unit Dividing ratio set by software in the CPU (n = 1, 2, 4, 8, and 16) tCYK (system clock cycle time) OTHER OPERATIONS (TA = –40 °C to +85 °C, VDD = AVDD = 4.0 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. NMI low-level width t WNIL 10 µs NMI high-level width t WNIH 10 µs INTP0 low-level width t WIT0L 4 tCYSMP ns INTP0 high-level width t WIT0H 4 tCYSMP ns Low-level width for INTP1INTP3 and CI t WIT1L 4 t CYCPU ns High-level width for INTP1INTP3 and CI t WIT1H 4 t CYCPU ns Low-level width for INTP4 and t WIT2L INTP5 10 µs High-level width for INTP4 and t WIT2H INTP5 10 µs RESET low-level widthNote t WRSL 10 µs RESET high-level width t WRSH 10 µs Note Use the RESET low-level width to ensure the lapse of the oscillation settling time when the power is applied. Remark tCYSMP : Sampling clock set by software tCYCPU: CPU operation clock set by software in the CPU Data Sheet U11681EJ2V0DS00 37 µ PD78P4908 A/D CONVERTER CHARACTERISTICS (TA = –40 °C to +85 °C, VDD = AVDD = AVREF1 = 4.0 to 5.5 V, AV SS = VSS = 0 V) Symbol Parameter Conditions Resolution MIN. TYP. MAX. 8 Total errorNote IEAD = 00H IEAD = 01H bit FR = 0 0.6 % FR = 1 1.5 % 2.2 % ±1/2 LSB VDD = 4.5 to 5.5 V 1 Quantization error Conversion time tCONV Sampling time tSAMP Unit FR = 1 120/f CLK 9.5 480 µs FR = 0 240/f CLK 19.1 960 µs FR = 1 18/f CLK 1.4 72 µs FR = 0 36/f CLK 2.9 144 µs Analog input impedance RAN AVREF1 impedance RREF1 AVDD power supply voltage AIDD1 CS = 1 2.0 5.0 mA AIDD2 CS = 0, STOP mode 1.0 20 µA 3 1,000 MΩ 10 kΩ Note Quantization error is not included. This parameter is indicated as the ratio to the full-scale value. Caution To execute the conversion by the A/D converter set port 7, multiplexed with the A/D input lines, to output mode to prevent data from being inverted. Remark fCLK: System clock frequency (selectable from fXX , fXX/2, fXX/4, and f XX/8 by the standby control register (STBC)) IEBus CONTROLLER CHARACTERISTICS (TA = –40°C to +85°C, VDD = AVDD = AVREF1 = 4.5 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 6.20 6.29 6.39 MHz 1.5 µs IEBus standard frequencyNote 1 fS Transfer speed: mode 1 Driver delay time (delay from TX output to bus line)Note 2 tDTX CL = 50 pFNote 3 Receiver delay time (delay from bus line to RX output)Note 2 tDRX 0.7 µs Transmission delay on busNote 2 tDBUS 0.85 µs Notes 1. The value conforms to the IEBus standard. The IEBus controller is operable within the range of the oscillator frequency of oscillator characteristics. 2. The value is measured when IEBus system clock: fX = 6.29 MHz. 3. CL is the load capacitance of TX output line. 38 Data Sheet U11681EJ2V0DS00 µ PD78P4908 DATA RETENTION CHARACTERISTICS (TA = –40 °C to +85 °C) Parameter Symbol Conditions Data retention voltage VDDDR STOP mode Data retention current I DDDR STOP mode MIN. TYP. 2.5 MAX. Unit 5.5 V VDDDR = 2.5 V, AVREF = 0 V Note 1 2 10 µA VDDDR = 4.0 to 5.5 V, AVREF1 = 0 V Note 1 10 50 µA VDD rise time t RVD 200 µs VDD fall time t FVD 200 µs VDD hold time (to STOP mode setting) t HVD 0 ms STOP clear signal input time t DREL 0 ms Oscillation settling time t WAIT Crystal resonator 30 ms Ceramic resonator 5 0.1 VDDDR ms pins Note 2 0 VDDDR V Input low voltage VIL Input high voltage VIH Specific 0.9 V DDDR V Notes 1. Valid when input voltages to the pins described in Note 2 satisfy VIL or VIH in the above table. 2. RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, P33/SO0, P105/SCK3, P106/SI3, and P107/SO3 pins AC TIMING TEST POINTS VDD – 1 V 0.8 VDD or 2.2 V 0.8 VDD or 2.2 V Test points 0.45 V 0.8 V 0.8 V Data Sheet U11681EJ2V0DS00 39 µ PD78P4908 TIMING WAVEFORM (1) Read operation tWSTH ASTB tSAST tDRST tDSTID tHSTLA A8-A19 tDAID tHRA AD0-AD7 tDSTR tFRA tDAR tHRID tDRID tDRA RD tWRL (2) Write operation tWSTH ASTB tSAST tDWST tDSTOD tHSTLA A8-A19 tHWA AD0-AD7 tDSTW tDAW tHWOD tDWOD tSODWR WR tWWL 40 Data Sheet U11681EJ2V0DS00 µ PD78P4908 HOLD TIMING ASTB, A8-A19, AD0-AD7, RD, WR tFHQC tDCFHA tDHAC HLDRQ tDHQLHAL tDHQHHAH HLDAK EXTERNAL WAIT SIGNAL INPUT TIMING (1) Read operation ASTB tDSTWT tDSTWTH tHSTWTH A8-A19 AD0-AD7 tDAWT tDWTID RD tDWTR tDRWTL WAIT tHRWT tDRWTH (2) Write operation ASTB tDSTWT tDSTWTH tHSTWTH A8-A19 AD0-AD7 tDAWT WR tDWTW tDWWTL WAIT tHWWT tDWWTH Data Sheet U11681EJ2V0DS00 41 µ PD78P4908 REFRESH TIMING WAVEFORM (1) Random read/write cycle tRC ASTB WR tRC tRC tRC tRC RD (2) When refresh memory is accessed for a read and write at the same time ASTB RD, WR tDSTRFQ tDRFQST tWRFQH REFRQ tWRFQL (3) Refresh after a read ASTB tDRFQST RD tDRRFQ REFRQ tWRFQL (4) Refresh after a write ASTB tDRFQST WR tDWRFQ REFRQ tWRFQL 42 Data Sheet U11681EJ2V0DS00 µ PD78P4908 SERIAL OPERATION (CSI, CSI3) tWSKL0 tWSKH0 SCK0, SCK3 tSSSK0 tHSSK0 tCYSK0 SI0, SI3 Input data tDSBSK1 SO0, SO3 tHSBSK1 Output data SERIAL OPERATION (IOE1, IOE2) tWSKL1 tWSKH1 SCK1, SCK2 tSSSK1 tCYSK1 SI1, SI2 tHSSK1 Input data tHSOSK tDSOSK SO1, SO2 Output data SERIAL OPERATION (UART, UART2) tWASKH tWASKL ASCK, ASCK2 tCYASK CLOCK OUTPUT TIMING tCLH tCLL CLKOUT tCLR tCLF tCYCL Data Sheet U11681EJ2V0DS00 43 µ PD78P4908 INTERRUPT REQUEST INPUT TIMING tWNIH tWNIL tWIT0H tWIT0L tWIT1H tWIT1L tWIT2H tWIT2L tWRSH tWRSL NMI INTP0 CI, INTP1-INTP3 INTP4, INTP5 RESET INPUT TIMING RESET 44 Data Sheet U11681EJ2V0DS00 µ PD78P4908 EXTERNAL CLOCK TIMING tWXH tWXL X1 tXR tXF tCYX DATA RETENTION CHARACTERISTICS STOP mode setting VDD VDDDR tHVD tFVD tRVD tDREL tWAIT RESET NMI (Clearing by falling edge) NMI (Clearing by rising edge) Data Sheet U11681EJ2V0DS00 45 µ PD78P4908 DC PROGRAMMING CHARACTERISTICS (TA = 25 °C ±5°C, VSS = 0 V) Symbol SymbolNote 1 High-level input voltage VIH VIH Low-level input voltage VIL VIL Input leakage current I LIP I LI Parameter Conditions MIN. TYP. MAX. Unit 2.2 VDDP + 0.3 V –0.3 +0.8 V ±10 µA 0 ≤ V I ≤ VDDP Note 2 High-level output voltage V OH VOH I OH = –400 µA Low-level output voltage VOL VOL I OL = 2.1 mA 0.45 V Output leakage current I LO – 0 ≤ V O ≤ VDDP , OE = V IH ±10 µA VDDP VCC VDDP supply voltage VPP supply voltage VPP VPP 2.4 Program memory write mode 6.25 6.5 6.75 V Program memory read mode 4.5 5.0 5.5 V Program memory write mode 12.2 12.5 12.8 V Program memory read mode VDDP supply current VPP supply current I DD I PP I DD I PP VPP = VDDP V Program memory write mode 10 40 mA Program memory read mode 10 40 mA Program memory write mode 5 50 mA Program memory read mode 1.0 100 µA Notes 1. Symbols for the corresponding µPD27C1001A 2. The VDDP represents the VDD pin as viewed in the programming mode. 46 V Data Sheet U11681EJ2V0DS00 µ PD78P4908 AC PROGRAMMING CHARACTERISTICS (TA = 25°C ±5°C, VSS = 0 V) PROM Write Mode (Page Program Mode) Parameter SymbolNote 1 Conditions MIN. TYP. MAX. Unit Address setup time t AS 2 µs CE set time t CES 2 µs Input data setup time t DS 2 µs Address hold time t AH 2 µs t AHL 2 µs t AHV 0 µs Input data hold time tDH 2 µs Output data hold time t DF 0 VPP setup time tVPS 2 µs VDDP setup time t VDSNote 2 2 µs Initial program pulse width tPW 0.095 OE set time t OES 2 Valid data delay time from OE tOE OE pulse width in the data latch t LW 1 µs PGM setup time t PGMS 2 µs CE hold time t CEH 2 µs OE hold time t OEH 2 µs 130 0.1 0.105 ns ms µs 1 2 ns Notes 1. These symbols (except tVDS) correspond to those of the corresponding µ PD27C1001A. 2. For µPD27C1001A, read tVDS as tVCS . Data Sheet U11681EJ2V0DS00 47 µ PD78P4908 PROM Write Mode (Byte Program Mode) Parameter Symbol Note 1 Conditions MIN. TYP. MAX. Unit Address setup time tAS 2 µs CE set time t CES 2 µs Input data setup time t DS 2 µs Address hold time t AH 2 µs Input data hold time t DH 2 µs Output data hold time tDF 0 VPP setup time t VPS 2 µs VDDP setup time tVDSNote 2 2 µs Initial program pulse width t PW 0.095 OE set time tOES 2 Valid data delay time from OE t OE 130 0.1 0.105 ns ms µs 1 2 ns Notes 1. These symbols (except tVDS) correspond to those of the corresponding µ PD27C1001A. 2. For µPD27C1001A, read tVDS as tVCS . PROM Read Mode Parameter Symbol Note 1 Conditions MIN. TYP. MAX. Unit 200 ns Data output time from address t ACC CE = OE = V IL Delay from CE ↓ to data output tCE OE = VIL 1 2 µs Delay from OE ↓ to data output t OE CE = VIL 1 2 µs Data hold time to OE↑ or CE↑ Note 2 t DF CE = VIL or OE = V IL 0 60 ns Data hold time to address t OH CE = OE = V IL 0 Notes 1. These symbols correspond to those of the corresponding µ PD27C1001A. 2. tDF is the time measured from when either OE or CE reaches VIH, whichever is faster. 48 Data Sheet U11681EJ2V0DS00 ns µ PD78P4908 PROM Write Mode Timing (Page Program Mode) Page data latch Page program Program verify A2-A16 tAS tAHL tDS tDH tAHV A0, A1 D0-D7 Hi-Z tDF Hi-Z tVPS Data input Hi-Z tPGMS tOE Data output tAH VPP VPP VDDP tVDS VDDP + 1.5 VDDP VDDP tCES tOEH VIH CE VIL tCEH tPW VIH PGM VIL VIH tOES tLW OE VIL Data Sheet U11681EJ2V0DS00 49 µ PD78P4908 PROM Write Mode Timing (Byte Program Mode) Program Program verify A0-A16 tAS D0-D7 Hi-Z tDS tDF Hi-Z Data input tDS Hi-Z Data output tDH tAH VPP VPP VDDP tVPS VDDP + 1.5 VDDP VDDP tVDS VIH CE VIL tCES tPW VIH PGM VIL tOES tOE VIH OE VIL Cautions 1. V DDP must be applied before VPP, and must be cut after VPP. 2. VPP including overshoot must not exceed 13.5 V. 3. Plugging in or out the board with the VPP pin supplied with 12.5 V may adversely affect its reliability. PROM Read Mode Timing Valid address A0-A16 CE tCE OE tDFNote 2 tACCNote 1 D0-D7 Hi-Z tOENote 1 tOH Data output Hi-Z Notes 1. For reading within tACC, the delay of the OE input from falling edge of CE must be within t ACC-tOE. 2. tDF is the time measured from when either OE or CE reaches VIH, whichever is faster. 50 Data Sheet U11681EJ2V0DS00 µ PD78P4908 9. PACKAGE DRAWING 100PIN PLASTIC QFP (14x20) A B 51 50 80 81 detail of lead end C D S R Q 31 30 100 1 F J G H I P M K M N L NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. Remark The shape and material of the ES version are the same as those of the corresponding mass-produced product. ITEM A MILLIMETERS 23.6±0.4 INCHES 0.929±0.016 B 20.0±0.2 0.795 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.6±0.4 0.693±0.016 F 0.8 0.031 G 0.6 0.024 H 0.30±0.10 0.012 +0.004 –0.005 I 0.15 0.006 J 0.65 (T.P.) 0.026 (T.P.) K 1.8±0.2 0.071 +0.008 –0.009 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P 2.7±0.1 0.106 +0.005 –0.004 Q 0.1±0.1 0.004±0.004 R 5°±5° 5°±5° S 3.0 MAX. 0.119 MAX. P100GF-65-3BA1-3 Data Sheet U11681EJ2V0DS00 51 µ PD78P4908 10. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the µPD78P4908. For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. Table 10-1. Soldering Conditions for Surface-Mount Devices µ PD78P4908GF-3BA: 100-pin plastic QFP (14 × 20 mm) Soldering process Soldering conditions Symbol Infrared ray reflow Peak package's surface temperature: 235°C Reflow time: 30 seconds or less (210°C or more) Maximum allowable number of reflow processes: 2 Exposure limit: 7 days Note (20 hours of pre-baking is required at 125°C afterward) IR35-207-2 VPS Peak package's surface temperature: 215°C Reflow time: 40 seconds or less (200°C or more) Maximum allowable number of reflow processes: 2 Exposure limit: 7 days Note (20 hours of pre-baking is required at 125°C afterward) VP15-207-2 Wave soldering Solder temperature: 260°C or less Flow time: 10 seconds or less Number of flow processes: 1 WS60-207-1 Preheating temperature: 120°C MAX. (measured on the package surface) Exposure limit: 7 days Note (20 hours of pre-baking is required at 125°C afterward) Partial heating method Terminal temperature: 300°C or less Heat time: 3 seconds or less (for one side of a device) – Note Maximum number of days during which the product can be stored at a temperature of 25°C and a relative humidity of 65% or less after dry-pack package is opened. Caution Do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections). 52 Data Sheet U11681EJ2V0DS00 µ PD78P4908 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for system development using the µ PD78P4908. See also (5) Notes on using development tools. (1) Language processing software RA78K4 Assembler package for all 78K/IV series models CC78K4 C compiler package for all 78K/IV series models DF784908 Device file for µPD784908 subseries models CC78K4-L C compiler library source file for all 78K/IV series models (2) PROM write tools PG-1500 PROM programmer PA-78P4908GF Programmer adapter, connects to PG-1500 PG-1500 controller Control program for PG-1500 (3) Debugging tools • When using the in-circuit emulator IE-78K4-NS IE-78K4-NS In-circuit emulator for all 78K/IV series models IE-70000-MC-PS-B Power supply unit for IE-78K4-NS IE-70000-98-IF-C Interface adapter when the PC-9800 series computer (other than a notebook) is used as the host machine (C bus compatible) IE-70000-CD-IF-A PC card and interface cable when a notebook is used as the host machine (PCMCIA socket compatible) IE-70000-PC-IF-C Interface adapter when the IBM PC/ATTM compatible is used as the host machine (ISA compatible) IE-7000-PCI-IF Adapter when a computer with a PCI bus as the host machine IE-784908-NS-EM1Note Emulation board for evaluating µPD784908 subseries models NP-100GFNote Emulation probe for 100-pin plastic QFP (GF-3BA type) EV-9200GF-100 Socket for mounting on target system board made for 100-pin plastic QFP (GF-3BA type). Used in LCC mode. ID78K4-NS Integrated debugger for IE-78K4-NS SM78K4 System simulator for all 78K/IV series models DF784908 Device file for µPD784908 subseries models Note Under development Data Sheet U11681EJ2V0DS00 53 µ PD78P4908 • When using the in-circuit emulator IE-784000-R IE-784000-R In-circuit emulator for all 78K/IV series models IE-70000-98-IF-C Interface adapter when the PC-9800 series computer (other than a notebook) is used as the host machine (C bus compatible) IE-70000-PC-IF-C Interface adapter when the IBM PC/AT compatible is used as the host machine (ISA bus compatible) IE-7000-PCI-IF Adapter when a computer with a PCI bus as the host machine IE-78000-R-SV3 Interface adapter and cable when the EWS is used as the host machine IE-784908-NS-EM1 IE-784908-R-EM1 Emulation board for evaluating µPD784908 subseries models IE-784000-R-EM Emulation board for all 78K/IV series models IE-78K4-R-EX2 Conversion board for emulation probes required to use the IE-784908-NSEM1 on the IE-784000-R. The board is not needed when the conventional product IE-784908-R-EM1 is used. EP-78064-GF-R Emulation probe for 100-pin plastic QFP (GF-3BA type) EV-9200GF-100 Socket for mounting on target system board made for 100-pin plastic QFP (GF-3BA type) ID78K4 Integrated debugger for IE-784000-R SM78K4 System simulator for all 78K/IV series models DF784908 Device file for µPD784908 subseries models (4) Real-time OS RX78K/IV Real-time OS for 78K/IV series models MX78K4 OS for 78K/IV series models 54 Data Sheet U11681EJ2V0DS00 µ PD78P4908 (5) Notes when using development tools • The ID78K4-NS, ID78K4, and SM78K4 can be used in combination with the DF784908. • The CC78K4 and RX78K/IV can be used in combination with the RA78K4 and DF784908. • The NP-100GF is a product from Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Consult the NEC sales representative for purchasing. • The host machines and operating systems corresponding to each software are shown below. Host machine [OS] PC PC-9800 series [WindowsTM] IBM PC/AT compatibles [Windows] Software RA78K4 Note CC78K4 Note PG-1500 controller Note EWS HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM, Solaris TM] NEWSTM (RISC) [NEWS-OSTM] ID78K4-NS – – ID78K4 SM78K4 – RX78K/IV Note MX78K4 Note Note Software under MS-DOS Data Sheet U11681EJ2V0DS00 55 µ PD78P4908 APPENDIX B CONVERSION SOCKET (EV-9200GF-100) PACKAGE DRAWING Connect the µ PD78P4908GF-3BA (100-pin plastic QFP (14 × 20 mm)) to the circuit board in combination with the EV-9200GF-100. Figure B-1. Package Drawings of EV-9200GF-100 (Reference) A B E M N O L K S J D C R F EV-9200GF-100 Q 1 No.1 pin index P G H I EV-9200GF-100-G0 ITEM 56 MILLIMETERS INCHES A 24.6 0.969 B 21 0.827 C 15 0.591 D 18.6 0.732 E 4-C 2 4-C 0.079 F 0.8 0.031 G 12.0 0.472 H 22.6 0.89 I 25.3 0.996 J 6.0 0.236 K 16.6 0.654 L 19.3 076 M 8.2 0.323 N 8.0 0.315 O 2.5 0.098 0.079 P 2.0 Q 0.35 0.014 R φ 2.3 φ 0.091 S φ 1.5 φ 0.059 Data Sheet U11681EJ2V0DS00 µ PD78P4908 Figure B-2. Recommended Pattern to Mount EV-9200GF-100 on a Substrate (Reference) G J H D F E K I L C B A EV-9200GF-100-P1E ITEM MILLIMETERS INCHES A 26.3 1.035 B 21.6 0.85 C +0.002 0.65±0.02 × 29=18.85±0.05 0.026 +0.001 –0.002 × 1.142=0.742 –0.002 D +0.003 0.65±0.02 × 19=12.35±0.05 0.026 +0.001 –0.002 × 0.748=0.486 –0.002 E 15.6 0.614 F 20.3 0.799 G 12 ± 0.05 0.472 +0.003 –0.002 H 6 ± 0.05 0.236 +0.003 –0.002 I 0.35 ± 0.02 0.014 +0.001 –0.001 J φ 2.36 ± 0.03 φ 0.093+0.001 –0.002 K φ 2.3 φ 0.091 L φ 1.57 ± 0.03 φ 0.062+0.001 –0.002 Caution Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Data Sheet U11681EJ2V0DS00 57 µ PD78P4908 APPENDIX C RELATED DOCUMENTS Documents Related to Devices Document No. Document name Japanese English µ PD784907, 784908 Data Sheet U11680J U11680E µ PD78P4908 Data Sheet U11681J This document µ PD784908 Subseries User's Manual – Hardware U11787J U11787E µ PD784908 Subseries Special Function Registers U11589J — 78K/IV Series User's Manual – Instruction U10905J U10905E 78K/IV Series Instruction Table U10594J — 78K/IV Series Instruction Set U10595J — U10095J U10095E 78K/IV Series Application Note Software Basic Documents Related to Development Tools (User's Manual) Document No. Document name Japanese English Operation U11334J U11334E Language U11162J U11162E U11743J U11743E Operation U11572J U11572E Language U11571J U11571E PG-1500 PROM Programmer U11940J U11940E PG-1500 Controller PC-9800 Series (MS-DOSTM) Base EEU-704 EEU-1291 PG-1500 Controller IBM PC Series (PC DOS TM) Base EEU-5008 U10540E IE-78K4-NS U13356J U13356E IE-784000-R U12903J U12903E IE-784908-R-EM1 U11876J — IE-784908-NS-EM1 U13743J On preparation EP-78064 EEU-934 EEU-1469 RA78K4 Assembler Package RA78K Series Structured Assembler Preprocessor CC78K4 C Compiler SM78K4 System Simulator Windows Base Reference U10093J U10093E SM78K Series System Simulator External Part User Open Interface Specifications U10092J U10092E ID78K4-NS Integrated Debugger PC Base Reference U12796J U12796E ID78K4 Integrated Debugger Windows Base Reference U10440J U10440E ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Base Reference U11960J U11960E Caution The above documents may be revised without notice. Use the latest versions when you design application systems. 58 Data Sheet U11681EJ2V0DS00 µ PD78P4908 Documents Related to Software to Be Incorporated into the Product (User's Manual) Document No. Document name 78K/IV Series Real-Time OS OS for 78K/IV Series MX78K4 Japanese English Fundamental U10603J U10603E Installation U10604J U10604E Debugger U10364J — Fundamental U11779J — Other Documents Document No. Document name Japanese English – C13388E Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Device C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J C11892E — MEI-1202 U11416J — NEC IC Package Manual (CD-ROM) Guide to Quality Assurance for Semiconductor Devices Guide for Products Related to Microcomputer: Other Companies Caution The above documents may be revised without notice. Use the latest versions when you design application systems. Data Sheet U11681EJ2V0DS00 59 µ PD78P4908 [MEMO] 60 Data Sheet U11681EJ2V0DS00 µ PD78P4908 [MEMO] Data Sheet U11681EJ2V0DS00 61 µ PD78P4908 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 62 Data Sheet U11681EJ2V0DS00 µ PD78P4908 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U11681EJ2V0DS00 63 µ PD78P4908 IEBus is a trademark of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of SONY Corporation. Some related documents may be preliminary versions. Note that, however, what documents are preliminary is not indicated in this document. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5