E2U0032-28-82
¡ Semiconductor
MSM7581
¡ Semiconductor
This version: Aug.
1998
MSM7581
Previous version: Nov. 1996
ITU-T G.721 4ch ADPCM TRANSCODER
GENERAL DESCRIPTION
The MSM7581 is an ADPCM transcoder which is used by the new digital cordless system.
It converts 64 kbps voice PCM serial data to 32 kbps ITU-T G.721 ADPCM serial data, and vice
versa.
This device is consists of four systems with full-duplex voice data channels and a data-through
mode.
The MSM7581 provides cost effective solutions for digital cordless office telephone systems
which are incorporated into PABXs, and for the public base stations which are connected to the
Central Office through digital PSTNs.
FEATURES
• Conforms to ITU-T G.721
• Built-in Full-duplex Transcoder with Four Data Channels
• PCM companding Law: A-law/µ-law selectable
• Serial PCM Data Transmission Speed: 64 kbps to 2048 kbps
• Serial ADPCM Data Transmission Speed: 32 kbps to 2048 kbps
• Hardware Reset – ITU-T G.721 Optional Reset – for each channel
• Power Down Control for each channel
• Decoder (ADPCM Æ PCM ) Mute Mode and PAD Mode for each channel
• ADPCM Data-through Mode
• Capable of time slot conversion
• Special ADPCM Input Data Code (”0000”) Detector for each channel
• Master Clock Signal : Not necessary
• Power supply voltage/Consumption current :
+2.7 V to +5.5 V, 2 mA/channel (max)
• Package :
100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name : MSM7581TS-K)
1/18
¡ Semiconductor
MSM7581
BLOCK DIAGRAM
VDD
GND LAW
+2.7 V to 5.5 V
PAD11
PAD10
SYXP1
BCKP1
PLCKEN
0V
THR1
PLCK1
SYXA1
BCKA1
PLL
MCK
SIP1
CODER
S→P
SOP1
DECODER
S←P
CODER
P→S
CODER
PAD/
MUTE
DECODER
"0000"
DETECT
DECODER
P←S
SYRP1
DET1
PDN1
PAD21
PAD20
SYXP2
BCKP2
THR2
PLCK2
SYXA2
BCKA2
PLL
MCK
SIP2
CODER
S→P
SOP2
DECODER
S←P
CODER
P→S
CODER
PAD/
MUTE
DECODER
"0000"
DETECT
DECODER
P←S
SYRP2
SOA2
SIA2
DET2
SYRA2
RES2
PDN2
PAD31
PAD30
SYXP3
BCKP3
THR3
PLCK3
SYXA3
BCKA3
PLL
MCK
SIP3
CODER
S→P
SOP3
DECODER
S←P
CODER
P→S
CODER
PAD/
MUTE
DECODER
"0000"
DETECT
DECODER
P←S
SYRP3
SOA3
SIA3
DET3
SYRA3
RES3
PDN3
PAD41
PAD40
SYXP4
BCKP4
THR4
PLCK4
SYXA4
BCKA4
PLL
MCK
SIP4
CODER
S→P
SOP4
DECODER
S←P
RES4
SIA1
SYRA1
RES1
SYRP4
SOA1
CODER
P→S
CODER
PAD/
MUTE
DECODER
"0000"
DETECT
DECODER
P←S
SOA4
SIA4
DET4
SYRA4
PDN4
2/18
¡ Semiconductor
MSM7581
RES1
SYRP1
SIP1
SOP1
BCKP1
NC
SYXP1
PAD10
PAD11
NC
GND
VDD
PLCKEN
NC
PAD41
PAD40
SYXP4
NC
BCKP4
SOP4
SIP4
SYRP4
RES4
NC
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
100 NC
PIN CONFIGURATION (TOP VIEW)
NC
1
75
NC
THR1
2
74
THR4
PLCK1
3
73
PLCK4
SYXA1
4
72
SYXA4
SOA1
5
71
SOA4
SIA1
6
70
SIA4
NC
7
69
NC
DET1
8
68
DET4
SYRA1
9
67
SYRA4
BCKA1
10
66
BCKA4
NC
11
65
NC
PDN1
12
64
PDN4
44
45
46
47
48
49
50
NC
BCKP3
SOP3
SIP3
SYRP3
RES3
NC
NC
43
THR3
51
SYXP3
52
25
42
24
NC
PAD30
THR2
41
PLCK3
PAD31
53
40
23
39
SYXA3
PLCK2
NC
54
LAW
22
38
SOA3
SYXA2
GND
55
37
21
VDD
SIA3
SOA2
36
56
NC
20
35
NC
SIA2
PAD21
57
34
19
PAD20
DET3
NC
33
58
SYXP2
18
32
SYRA3
DET2
NC
59
31
17
BCKP2
BCKA3
SYRA2
30
60
SOP2
16
29
NC
BCKA2
28
61
SIP2
15
SYRP2
PDN3
NC
27
NC
62
26
63
14
NC
13
RES2
NC
PDN2
NC : No connect pin
100-Pin Plastic TQFP
3/18
¡ Semiconductor
MSM7581
PIN AND FUNCTIONAL DESCRIPTIONS
GND
Ground, 0 V.
SIP1, SOP1
PCM serial data input (SIP1) and output (SOP1) for Channel 1.
SOP1 is an open-drain output, which goes into a high impedance state after a continuous 8-bit
serial data output.
SIP2, SOP2
PCM serial data input (SIP2) and output (SOP2) for Channel 2.
SOP2 is an open-drain output, which goes into a high impedance state after a continuous 8-bit
serial data output.
SIP3, SOP3
PCM serial data input (SIP3) and output (SOP3) for Channel 3.
SOP3 is an open-drain output, which goes into a high impedance state after a continuous 8-bit
serial data output.
SIP4, SOP4
PCM serial data input (SIP4) and output (SOP4) Channel 4.
SOP4 is an open-drain output, which goes into a high impedance state after a continuous 8-bit
serial data output.
PAD10 - PAD40, PAD11 - PAD41
PAD mode control.
The PCM output can be attenuated by 12 dB or 6 dB and set to an out-of-service pattern (idle
pattern) by controlling these pins. Set these pins to digital "0" level during normal operation.The
control sequences are as follows:
PAD11 - PAD41
PAD10 - PAD40
0
0
Normal
0
1
6 dB Loss
1
0
12 dB Loss
1
1
Out-of-service Pattern
4/18
¡ Semiconductor
MSM7581
THR1, THR2, THR3, THR4
Control pins for the data-through modes.
THR (1 - 4) are for Channel (1 - 4), respectively. The data-through mode is selected when digital
“1” is applied to THR (1 - 4). In this mode, 8-bit serial input data applied to SIA (1 - 4) (ADPCM
data input) is passed to the PCM serial data output pins, SOP (1 - 4), without any data
modification. SOP (1 - 4) go to the high impedance state after the output of 8-bit data has been
applied to SIA (1 - 4).
Conversely 8-bit serial input data applied to SIP (1 - 4) (PCM data input) is passed to ADPCM
serial data output pins, SOA (1 - 4), without any data modification.
SOA (1 - 4) go to the high impedance state after the output of 8-bit serial data has been applied
to SIP (1 - 4).
ADPCM and PCM data interfaces have the mutually independent signal input pins for
synchronizing signals. The time slots for data input and output can be exchanged between them.
Some timing at which data may be deleted or duplicated as described in "Note on Usage" should
not be used.
SYXP1 - 4, SYRP1 - 4
Synchronous signal input pins to define PCM data input and output timing for Channel 1 (SIP1,
SOP1), Channel 2 (SIP2, SOP2), Channnel 3 (SIP3, SOP3), and Channel 4 (SIP4, SOP4).
The synchronous signals SYXA1 and SYRAI (Channel 1), SYXA2 and SYRA2 (Channel 2),
SYXA3 and SYRA3 (Channel 3), and SYXA4 and SYRA4 (Channel 4), which define ADPCM data
input and output timing are provided.
PCM and ADPCM data interfaces can be used at a mutually independent timing except some
timing.
Note: When PCM and ADPCM data interfaces are used at a mutually independent timing, the
timing described in "Note on Usage" should not be used.
SYXP signals must be input for PAD signal input processing.
BCKP1 - 4
Bit clock input.
These signals define the PCM data transmission speed at the PCM data input/output terminals.
BCKP (1 - 4) are used for Channel (1 - 4). Since BCKA (1 - 4) defines the data rate of the ADPCM
data interface, the PCM and ADPCM data can be input or output at different speeds.
LAW
PCM data companding law selection.
Digital “1” and “0” correspond to A-law and µ-law, respectively.
PDN1, PDN2, PDN3, PDN4
Power down mode selection.
PDN1 - 4 can be independently set to power down mode. When digital “0” is applied, these pins
are in the power-down mode.
5/18
¡ Semiconductor
MSM7581
SIA1, SOA1
ADPCM serial data input (SIA1) and output (SOA1) pins for Channel 1.
SOA1 is an open-drain pin and enters to the high impedance state after outputting a continuous
4-bit serial data stream. When the data-through mode is selected, SOA1 enters to the high
impedance state after outputting an 8-bit serial data stream.
SIA2, SOA2
ADPCM serial data input (SIA2) and output (SOA2) pins for Channel 2.
These pins function the same as SIA1 and SOA1.
SIA3, SOA3
ADPCM serial data input (SIA3) and output (SOA3) pins for Channel 3.
These pins function the same as SIA1 and SOA1.
SIA4, SOA4
ADPCM serial data input (SIA4) and output (SOA4) pins for Channel 4.
These pins function the same as SIA1 and SOA1.
SYXA1 - 4 , SYRA1 - 4
SYXA1, SYXA2, SYXA3, and SYXA4 are synchronous signal input pins to define ADPCM data
input and output timings for Channel 1 (SIA1, SOA1), Channel 2 (SIA2, SOA2), Channel 3 (SIA3,
SOA3), and Channel 4 (SIA4, SOA4), respectively.
Therefore, PCM data interfaces can be used at a mutually independent timing except some
timing.
Since master clocks are generated by the internal PLL using SYXA1 to SYXA4, a synchronous
signal should be input to these pins.
Note: When PCM and ADPCM data interfaces are used at a mutually independent timing, the
timing described in "Note on Usage" should not be used.
DET1, DET2, DET3, DET4
Special ADPCM input data pattern detect pins.
When detecting a 4-bit continuous "0" pattern at the ADPCM input pins Channel 1 (SIA1),
Channel 2 (SIA2), Channel 3 (SIA3), and Channel 4 (SIA4), DET (1 - 4) goes from a digital "0" to
a digital "1" state.
A digital "1" is output at the rising edge of the clock. The fourth data bit (LSB) is clocked into the
register by the bit clock (BCKA 1 - 4) and held there until the rising edge in the next time frame.
When detecting the special data pattern in the next time frame, the digital "1" on the pins DET
(1 - 4) is remains.
6/18
¡ Semiconductor
MSM7581
RES1, RES2, RES3, RES4
Algorithm reset signal input pins for each Channel (1 - 4) .
When digital “0” is applied, the entire transcoder goes to the initial state.
This reset is defined by ITU-T G.721 and is an optional reset.
The reset width (during "L") should be 125 ms or more.
BCKA1 - 4
Bit clock input pins used to define the data transmission speed at the ADPCM interface.
Using these pins, the ADPCM data interface can be defined at a speed other than the PCM data
interface.
VDD
Power supply.
The device must operate between +2.7 V and +5.5 V.
PLCKEN
Input pin which enables the output of an 8 kHz clock from the PLLs.
This pin generates the internal master clocks. The 8 kHz clocks from the internal PLLs
synchronized with external signals applied to SYXA 1 - 4 are output to PLCK 1 - 4.
Set this pin at digital "0" during normal operation since it is used as the control pin for testing the
IC.
PLCK1 - 4
Output pins of the 8 kHz clock from PLLs.
When PLCKEN = "1", the 8 kHz clock pulses synchronized with external signals are applied to
SYXA1 - 4 outputs. When PLCKEN = "0", "0" level is output to these pins.
7/18
¡ Semiconductor
MSM7581
ABSOLUTE MAXIMUM RATINGS
Symbol
Condition
Rating
Unit
Power Supply Voltage
Parameter
VDD
—
0 to 7
V
Digital Input Voltage
VDIN
—
–0.3 to VDD + 0.3
V
Storage Temperature
TSTG
—
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Min.
Typ.
Max.
Unit
Symbol
Condition
Power Supply Voltage
VDD
—
2.7
—
5.5
V
Operating Temperature
Ta
—
–30
+25
+80
°C
Digital Input High Voltage
VIH
0.45 ¥ VDD
—
VDD
V
Digital Input Low Voltage
VIL
0
—
0.16 ¥ VDD
V
Bit Clock Frequency
Synchronous
signal Frequency
All digital input pins
FBCLKA
BCKA1 - 4
32
—
2048
kHz
FBCLKP
BCKP1 - 4
64
—
2048
kHz
—
8.0
—
kHz
30
50
70
%
—
—
50
ns
FSYNC
Clock Duty Ratio
DC
Digital Input Rise Time
tIr
Digital Input Fall Time
Synchronous signal Timing
tIf
tXS
SYXP1 - 4, SYRP1 - 4
SYXA1 - 4, SYRA1 - 4
BCKA1 - 4, BCKP1 - 4
All Digital Input Pins
—
—
50
ns
BCKP1 - 4 to SYXP1 - 4
100
—
—
ns
CODER
tSX
SYXA1 - 4 to BCKA1 - 4
100
—
—
ns
Synchronous signal Timing
tRS
BCKA1 - 4 to SYRA1 - 4
100
—
—
ns
DECODER
tSR
SYRP1 - 4 to BCKP1 - 4
100
—
—
ns
1 BCLK
—
100
ms
100
—
—
ns
100
—
—
ns
500
—
—
W
—
—
100
pF
Synchronous
signal Width
Data Set-up Time
Data Hold Time
tWS
tDS
tDH
RDL
Digital Output Load
CDL
SYXP1 - 4, SYRP1 - 4
SYXA1 - 4, SYRA1 - 4
—
—
SOP1 - 4, SOA1 - 4
(Pull-up Resistor)
SOP1 - 4, SOA1 - 4
DET1 - 4, PLCK1 - 4
8/18
¡ Semiconductor
MSM7581
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
Power Supply Current
(VDD = 2.7 V to 5.5 V, Ta = –30°C to +80°C)
Symbol
IDD1
IDD2
Condition
Min.
Typ.
Max.
Unit
Power On Mode: 4 Channels
—
5
8
10
50
VDD
mA
mA
—
Power Down Mode: 4 Channels
All Digital Input Pins
0.45 ¥ VDD
All Digital Input Pins
0.0
Digital Input High Voltage
VIH
Digital Input Low Voltage
VIL
Input Leakage
IIH
VI = VDD
—
Current
IIL
VI = 0 V
—
Digital
—
—
0.16 ¥ VDD
V
V
—
—
2.0
mA
0.5
mA
VOH
DET1 - 4, PLCK1 - 4 : IOH = –0.4 mA 0.5 ¥ VDD
—
VDD
V
Digital
VOL1
SOA1 - 4, SOP1 - 4, Pull-up ≥ 500 W
0.0
0.2
0.4
V
Output Low Voltage
VOL2
DET1 - 4, PLCK1 - 4 : IOL = 2 mA
0.0
0.2
0.4
V
Output Leakage Current
IOL
SOP1 - 4, SOA1 - 4
—
—
10
mA
Input Capacitance
CIN
All Digital Input Pins
—
5
—
pF
Output High Voltage
AC Characteristics
Parameter
Digital Output Delay Time
(VDD = 2.7 V to 5.5 V, Ta = –30°C to +80°C)
Min.
Typ.
Max.
Unit
tSDX
0
—
200
ns
tSDR
0
—
200
ns
tXD1, tRD1
0
—
200
ns
0
—
200
ns
0
—
200
ns
tDD1
0
—
200
ns
tDD2
0
—
200
ns
Symbol
tXD2, tRD2
tXD3, tRD3
Condition
1 LSTTL + 100 pF
Pull-up: 500 W
9/18
¡ Semiconductor
MSM7581
TIMING DIAGRAM
CODER
BCKP1 - 4
0
tXS
1
tSX
2
SYXP1 - 4
4
5
6
7
8
9
10
8
9
10
tDS tDH
,,
,,
,,
MSB
SIP1 - 4
BCKA1 - 4
3
,,
,
,,
0
tXS
1
,,
,,
,,
tSX
SYXA1 - 4
,
tXD1
SOA1 - 4
2
,,
,,
3
,,
4
,,
,,
,
5
,
LSB
,,
,,
,
6
7
5
6
7
8
9
10
5
6
7
8
9
10
,,
,
tXD2
,,
,,
,,
,,
,,
,,
tXD3
MSB
tSDX
,,
,,
,,
LSB
DECODER
BCKA1 - 4
0
tRS
1
tSR
2
SYRA1 - 4
3
4
tDS tDH
,,
MSB
SIA1 - 4
,,
,,
,,
LSB
,,
BCKP1 - 4
0
tRS
1
,,
,2,
3
,,
tSR
,,
4
,,
,
SYRP1 - 4
tRD1
SOP1 - 4
tRD2
tRD3
LSB
MSB
tSDR
DET ("0000" detection) Output Timing
BCKA1 - 4
SYRA1 - 4
Note)
SIA1 - 4
"0000"
"0000"
DET1 - 4
tDD1
tDD2
Note: 4 bit data pattern except "0000"
10/18
¡ Semiconductor
MSM7581
PAD Processing Timing
SYXA
BCKA
SIA
MSB
LSB
78.125ms
78.125ms
Internal 12dBPAD processing Timing
121.09ms
78.125ms
Internal MUTE processing Timing
PAD10 to PAD40, PAD11 to PAD41 Timings
SYXP
PAD10, 11
ts
th
ts=100ns or more
th=100ns or more
Internal PAD
Signal
BCKP
SOP
MSB
LSB
0dB transmit data
PAD processing transmit data
0dB transmit data
As mentioned above, PAD and MUTE processings are performed according to the rising edge
of SYXA. Even if BLOCK is not 128 kHz, these processings are performed in the absolute time
counted from the rising edge of SYXA.
The PAD pin must be controlled so as to cover these processings.
The PAD signal is input in the device at the rising edge of SYXP. Therefore, the PAD signal should
be input at ts and th for the rise of SYXP.
11/18
¡ Semiconductor
MSM7581
THR Processing Timing
Timing Block Diagrams, when CODER and DECODER output data, are shown in the following
figures.
The parallel to serial conversion of the output unit employs a load format and the load point is
at the rising edge of a synchronous signal.
Therefore, input THR signal with respect to SYXA for CODER with timing of satisfying ts and
th conditions shown in the figure.
For DECODER, THR signal should be input even of through-data is input.
The input timing should satisfy the conditions shown in the following figures.
CODER
Through-data
8b
SYXP
Serial
SIP
BCKP
8
Latch
Parallel
ADPCM
CODER
Parallel
S
E
L
SYNCA
SOA
Serial
4b
BCLKA
Latch timing=A
THR
PCM side SYNC (SYXP)
PCM Input (SIP)
MSB
LSB
Internal Latch timing (A)
Internal Input Data
Through-data
ADPCM side SYNC (SYXA)
MSB
Through-data Output (SOA)
BCKA
THR
ts
th
ts=100ns or more
th=100ns or more
Note: That data-ship may occur when the rising edge (data load point) of SYXA and input of
the internal latch timing overlap each other.
12/18
¡ Semiconductor
MSM7581
DECODER
Through-data
8b
SYNCA
Serial
SIA
BCLKA
8
Latch
Parallel
ADPCM
DECODER
S
E
L
Parallel
SYNCP
SOP
Serial
8b
BCLKP
Latch timing=A
THR
ADPCM side SYNC (SYXA)
ADPCM Input (SIA)
MSB
LSB
Internal Latch timing (A)
Internal Input Data
Through-data
This data is output here.
PCM side SYNC (SYXP)
MSB
Throgh-data output (SOP)
BCLKP
THR
Less than are BCLKP cycle
100ns or more
from the rising edge of SYXA signal.
13/18
¡ Semiconductor
MSM7581
CODER 3 Side
ADPCM Output
DECODER 3 Side
ADPCM Intput
DECODER 4 Side
ADPCM Intput
CODER 4 Side
ADPCM Output
APPLICATION CIRCUIT
VDD
VDD
8 kHz Synchronous Signal
(Channel 4)
52
53
54
51
NC
THR3
PLCK3
SOA3
SYXA3
55
57
58
59
60
61
62
63
64
65
66
67
56
SIA3
NC
DET3
SYRA3
BCKA3
NC
PDN3
NC
PDN4
NC
BCKA4
68
DET4
SYRA4
70
69
NC
SIA4
72
73
74
71
SOA4
SYXA4
PLCK4
PAD20
SYXP1
SYXP2
NC
NC
BCKP1
BCKP2
SOP1
SOP2
SIP2
SIP1
SYRP2
SYRP1
8 kHz Synchronous Signal
(Channel 1)
VDD
VDD
48
CODER 3 Side
PCM Intput
47
46
DECODER 3 Side
PCM Output
45
44
43
42
41
40
VDD
39
38
37
36
35
34
33
32
VDD
31
30
29
28
DECODER 2 Side
PCM Output
CODER 2 Side
PCM Intput
27
26
8 kHz Synchronous Signal
(Channel 2)
Shift Clock
(Channel 1 - 4)
64 kHz to 2048 kHz
CODER 2 Side
ADPCM Output
DECODER 2 Side
ADPCM Intput
DECODER 1 Side
ADPCM Intput
CODER 1 Side
ADPCM Output
VDD
VDD
49
NC
NC
50
25
PLCK2
THR2
24
23
SOA2
SYXA2
22
21
SIA2
20
NC
19
18
DET2
SYRA2
17
BCKA2
16
2
1
NC
NC
NC
RES2
RES1
15
99
100
PAD10
PDN2
98
PAD21
14
97
PAD11
NC
CODER 1 Side
PCM Intput
96
NC
13
95
DECODER 1 Side
PCM Output
VDD
NC
PDN1
94
GND
GND
12
93
MSM7581
VDD
NC
VDD
LAW
PLCKEN
11
92
NC
NC
BCKA1
GND
PAD31
10
91
PAD41
SYRA1
90
PAD30
DET1
89
PAD40
9
88
SYXP3
8
87
SYXP4
NC
86
NC
NC
SIA1
85
BCKP3
7
84
SOP3
BCKP4
6
83
SOP4
SOA1
82
SIP3
5
81
SYRP3
SIP4
SYXA1
80
DECODER 4 Side
PCM Output
NC
RES3
SYRP4
4
79
RES4
PLCK1
78
CODER 4 Side
PCM Intput
NC
3
77
NC
76
THR1
VDD
THR4
75
8 kHz Synchronous Signal
(Channel 3)
+
0.1 mF
-
10 mF
GND
14/18
¡ Semiconductor
MSM7581
NOTES ON USAGE
(1) Through Mode (CODER Side)
t0
BCLK
1
t1
2
3
4
5
6
7
8
PCM side SYNC (SYXP)
PCM Input (SIP)
PCMDATA1
PCMDATA2
PCMDATA3
ADPCMDATA0
ADPCMDATA1
ADPCMDATA2
Internal Latch Timing
(A)
ADPCM side SYNC (SYXA)
Through-Data Output (SOA)
(B)
ADPCM side SYNC (SYXA)
Through-Data Output (SOA)
ADPCMDATA0
ADPCMDATA1
*t1 is the falling edge of the 8th BCLK counted from t0.
(A) When SYXA rises after t1, PCMDATA1 is output to ADPCMDATA1.
(B) When SYXA rises before t1, PCMDATA1 is output to ADPCMDATA1.
If SYXA rises near the t1 and jitter occurs, data slip may occur. Therefore SYXA should not rise in the range of ±500ns from t1.
The data slip means that data is deleted or the same data is output twice.
(2) Through Mode (DECODER Side)
t0
BCLK
1
t1
2
3
4
5
6
7
8
ADPCM side SYNC (SYRA)
ADPCM Input (SIA)
ADPCMDATA1
ADPCMDATA2
ADPCMDATA3
PCMDATA0
PCMDATA1
PCMDATA2
Internal Latch Timing
(A)
PCM side SYNC (SYRP)
Through-Data Output (SOP)
(B)
PCM side SYNC (SYRP)
Through-Data Output (SOP)
PCMDATA0
PCMDATA1
*t1 is the falling edge of the 8th BCLK counted from t0.
(A) When SYRP rises after t1, ADPCMDATA1 is output to PCMDATA1.
(B) When SYRP rises before t1, ADPCMDATA1 is output to PCMDATA1.
If SYRP rises near the t1 and jitter occurs, data slip may occur. Therefore SYRP should not rise in the range of ±500ns from t1.
The data slip means that data is deleted or the same data is output twice.
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¡ Semiconductor
MSM7581
(3) PCMÆADPCM, ADPCMÆPCM during Transcode
(a) CODER Timing Diagram
t0
SYXA
SYXP
BCKP
1
SIP
MSB
2
3
4
5
6
7
8
LSB
Internal (1)
Tsip
Timing (2)
104.2ms
Timing (3)
t1
119.8ms
SOA
LSB
MSB
* t4 is the falling edge of the 8th BCLK
counted from the rising edge of SYXP.
PCM Input Data
A
t4
t2
LSB
MSB
* t5 is the rising edge of SYXA.
t5
Tsoa
(b) DECODER Timing Diagram
SYRA
1
BCKA
SIA
MSB
2
3
4
MSB
LSB
Internal (6)
LSB
* t6 is the falling edge of the 4th BCLK
counted from the rising edge of SYRA.
MSB
ADPCM Input Data
t6
Tsia
SYRP
Tsop
t7
65.2ms
t3
* t7 is the rising edge of SYRP.
B
Timing (4)
Timing (5)
119.8ms
t2
PCM Output Data
SOP
(c) Internal Circuit Configuration
SIP
SYXP
S
/
P
(1)
8bit
Latch
(2)
(5)
BCKP
SYRP
SOP
To CODER
P
/
S
8bit
Latch
From
DECODER
From CODER
PLL
Latch
8bit
P
/
S
(3)
(4)
To
DECODER
SYXA
SOA
SYXA
BCKA
Latch
(6)
8bit
S
/
P
SYRA
SIA
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¡ Semiconductor
MSM7581
In this device, internal operating signals are generated according to the ADPCM side SYNC
(SYXA) signal.
The timings are shouwn in the figures (a) and (b);
The arithmetic operation of CODER is performed at "A" in the figure (a).
The arithmetic operation of DECODER is performed at "B" in the figure (b).
Therefore, when the conversion delay time Tsip of the CODER is less than t1, ADPCM is output
at the timing of Tsoa.
When Tsip is more than t1, ADPCM is output at the timing of Tsoa + 125ms.
For DECODER, when Tsia<t3 and Tsop<t2, the conversion delay time is Tsop-Tsia.
As mentioned above, a data ship may occur at Tsip=t1 in CODER, and at Tsia=t3 and Tsop=t2
in DECODER.
Therefore, the timings of SYNC signals of both PCM and ADPCM sides should not be set up in
the range about ±500nsec of Tsip=t1, Tsia=t3 and Tsop=t2.
For normal operation, SYNC clocks for ADPCM and PCM sides should be continuous at 8 kHz
and synchronized with each other even if their phases are different.
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¡ Semiconductor
MSM7581
PACKAGE DIMENSIONS
(Unit : mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.55 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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