SL4029B Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS The SL4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consists of a single CLOCK, CARRY IN,(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY IN and PRESET ENABLE signals are low. Advancement is inhibited when the CARRY IN or PRESET ENABLE signals are high. The CARRY OUT signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY IN signal is low. The CARRY IN signal in the low state can thus be considered a CLOCK ENABLE. The CARRY IN terminal must be connected to GND when not in use. Binary counting is accomplished when the BINARY/DECADE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low. Parallel clocking provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION SL4029BN Plastic SL4029BDW SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 16=VCC PIN 8= GND SLS System Logic Semiconductor SL4029B MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +20 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT IIN DC Input Current, per Pin ±10 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW PD Power Dissipation per Output Transistor 100 mW -65 to +150 °C 260 °C Tstg Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC DC Supply Voltage (Referenced to GND) VIN, VOUT TA Parameter DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min Max Unit 3.0 18 V 0 VCC V -55 +125 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL4029B DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions Guaranteed Limit V ≥-55°C 25°C ≤125 °C Unit VIH Minimum High-Level Input Voltage VOUT= 0.5 V or VCC - 0.5V VOUT= 1.0 V or VCC - 1.0 V VOUT= 1.5 V or VCC - 1.5V 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 V VIL Maximum Low -Level Input Voltage VOUT= 0.5 V or VCC - 0.5V VOUT= 1.0 V or VCC - 1.0 V VOUT= 1.5 V or VCC - 1.5V 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 V VOH Minimum High-Level Output Voltage VIN=GND or VCC 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 V VOL Maximum Low-Level Output Voltage VIN=GND or VCC 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 V IIN Maximum Input Leakage Current VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN= GND or VCC 5.0 10 15 20 5 10 20 100 5 10 20 100 150 300 600 3000 µA IOL Minimum Output Low (Sink) Current VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 Minimum Output High VIN= GND or VCC (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V 5.0 5.0 10 15 -2 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 IOH mA mA SLS System Logic Semiconductor SL4029B AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200kΩ, Input t r=t f=20 ns) VCC Guaranteed Limit V ≥-55°C 25°C ≤125°C Unit Maximum Clock Frequency (Figure 1) 5.0 10 15 2 4 5.5 2 4 5.5 1 2 2.75 MHz tPHL, t PLH Maximum Propagation Delay, Clock to Q (Figure 1) 5.0 10 15 500 240 180 500 240 180 1000 480 360 ns tPHL, t PLH Maximum Propagation Delay, Clock to Carry Output (Figure 1) 5.0 10 15 560 260 190 560 260 190 1120 520 380 ns tPHL, t PLH Maximum Propagation Delay, Preset Enable to Q (Figure 1) 5.0 10 15 470 200 160 470 200 160 940 400 320 ns tPHL, t PLH Maximum Propagation Delay, Preset Enable to Carry Output (Figure 1) 5.0 10 15 640 290 210 640 290 210 1280 580 420 ns tPHL, t PLH Maximum Propagation Delay, Carry Input to Carry Output (Figure 1) 5.0 10 15 340 140 100 340 140 100 680 280 200 ns tTHL, t TLH Maximum Output Transition Time, Any Output (Figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns Symbol tmax CIN Parameter Maximum Input Capacitance - 7.5 FUNCTION TABLE CONTROL INPUT LOGIC LEVEL ACTION BIN/DEC (B/D) H L BINARY COUNT DECADE COUNT UP/DOWN (U/D) H L UP COUNT DOWN COUNT PRESET ENABLE (PE) H L JAM IN NO JAM H NO COUNTER ADVANCE AT POS. CLOCK TRANSITION ADVANCE COUNTER AT POS. CLOCK TRANSITION CARRY IN (CI) (CLOCK ENABLE) SLS System Logic Semiconductor L pF SL4029B TIMING REQUIREMENTS (CL=50pF, RL=200 kΩ, Input t r=t f=20 ns) VCC Symbol ** V ≥-55°C 25°C ≤125°C Unit tw Minimum Pulse Width, Clock (Figure 1) 5.0 10 15 180 90 60 180 90 60 360 180 120 ns tw Minimum Pulse Width, Preset Enable (Figure 1) 5.0 10 15 130 70 50 130 70 50 260 140 100 ns tsu* Minimum Setup Time, Clock to B/D or U/D (Figure 1) 5.0 10 15 340 140 100 340 140 100 680 280 200 ns trem * Minimum Removal Time, Preset Enable (Figure 1) 5.0 10 15 200 110 80 200 110 80 400 220 160 ns th** Minimum Hold Time, Clock to Carry In (Figure 2) 5.0 10 15 50 30 25 50 30 25 100 60 50 ns tsu Minimum Setup Time, Carry In to Clock (Figure 1) 5.0 10 15 200 70 60 200 70 60 400 140 120 ns Maximum Input Rise and Fall Times,Clock (Figure 2) 5.0 10 15 15 15 15 15 15 15 30 30 30 µs tr, t f** * Parameter Guaranteed Limit From Up/Down, Binary/Decode, Carry In, or Preset Enable Control Inputs to Clock Edge. From Carry In to Clock Edge SLS System Logic Semiconductor SL4029B Figure 1. Switching Waveforms Figure 2. Switching Waveforms SLS System Logic Semiconductor SL4029B TIMING DIAGRAM; binary mode; J1=HIGH; J2=LOW; BIN/DEC=HIGH TIMING DIAGRAM; decade mode; J1=LOW; J4=LOW; BIN/DEC=LOW SLS System Logic Semiconductor SL4029B EXPANDED LOGIC DIAGRAM TRUTH TABLE CLOCK TE PE X X SLS System Logic Semiconductor J Q Q X L L L H L H X Q Q X L H H L H H X Q Q NC X H X Q Q NC