SLS SL74HC154N

SL74HC154
1- of-16 Decoder/Demultiplexer
High-Performance Silicon-Gate CMOS
The SL74HC154 is identical in pinout to the LS/ALS154. The
device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LS/ALSTTL outputs.
This device, when enabled, selects one of 16 active-low outputs.
Two active-low Chip Selects are provided to facilitate the chip-select,
demultiplexing, and cascading functions. When either Chip Select is
high, all outputs are high. The demultiplexing function is
accomplished by using the Address inputs to select the desired
device output.
The SL74HC154 is primarily used for memory address decoding
and data routing applications.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC154N Plastic
SL74HC154D SOIC
TA = -55° to 125° C for all
packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 24 =VCC
PIN 12 = GND
SLS
System Logic
Semiconductor
SL74HC154
MAXIMUM RATINGS *
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
IOUT
Tstg
Storage Temperature
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
VIN, VOUT
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, t f
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
Min
Max
Unit
2.0
6.0
V
0
VCC
V
-55
+125
°C
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL74HC154
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Guaranteed Limit
Test Conditions
V
25 °C
to
-55°C
≤85
°C
≤125
°C
Unit
Minimum High-Level
Input Voltage
VOUT=0.1 V or VCC-0.1 V
IOUT≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low -Level
Input Voltage
VOUT=0.1 V or VCC-0.1 V
IOUT ≤ 20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH
Minimum High-Level
Output Voltage
VIN=VIH or VIL
IOUT ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VIN=VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤.5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
Symbol
Parameter
VIH
VIN=VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
VOL
Maximum Low-Level
Output Voltage
VIN=VIH or VIL
IOUT ≤ 20 µA
V
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0
±1.0
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA
6.0
8.0
80
160
µA
SLS
System Logic
Semiconductor
SL74HC154
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns)
VCC
Symbol
Parameter
Guaranteed Limit
V
25 °C to
-55°C
≤85°C
≤125°C
Unit
tPLH, t PHL
Maximum Propagation Delay, Input A to
Output Y (Figures 1and 3)
2.0
4.5
6.0
190
38
32
240
48
41
285
57
48
ns
tPLH, t PHL
Maximum Propagation Delay , CS to
Output Y (Figures 2 and 3)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tTLH, t THL
Maximum Output Transition Time, Any Output
(Figures 2 and 3)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
-
10
10
10
pF
CIN
Maximum Input Capacitance
CPD
Power Dissipation Capacitance (Per Package)
Typical @25°C,VCC=5.0 V
Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
80
pF
FUNCTION TABLE
Inputs
Outputs
CS1 CS2 A3 A2 A1 A0 Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9 Y10 Y11 Y12 Y13 Y14 Y15
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SLS
System Logic
Semiconductor
SL74HC154
X = Don’t Care
SLS
System Logic
Semiconductor
SL74HC154
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Test Circuit
SLS
System Logic
Semiconductor
SL74HC154
EXPANDED LOGIC DIAGRAM
SLS
System Logic
Semiconductor