SONY CXA2094

CXA2094Q
US Audio Multiplexing Decoder
Description
The CXA2094Q is an IC designed as a decoder for
the Zenith TV Multi-channel System and also
corresponds with I2C BUS. Functions include stereo
demodulation, SAP (Separate Audio Program)
demodulation, dbx noise reduction. Various kinds of
filters are built in while adjustment and mode control
are all executed through I2C BUS.
48 pin QFP (Plastic)
Features
• Adjustment free of VCO and filter.
• Audio multiplexing decoder and dbx noise
reduction decoder are all included in a single chip.
Almost any sort of signal processing is possible
through this IC.
• All adjustments are possible through I2C BUS to
allow for automatic adjustment.
• Various built-in filter circuits greatly reduce external
parts.
• There are two systems for external inputs.
• There is an additional SAP output.
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VCC
11
• Operating temperature Topr –20 to +75
• Storage temperature
Tstg –65 to +150
• Allowable power dissipation
PD
0.6
100mVrms
245mVrms (Selected by INSW)
AUX1-L/R (Pins 42 and 41)
490mVrms
AUX2-L/R (Pins 45 and 44)
490mVrms
• Output level
TVOUT-L/R (Pins 47 and 46)
490mVrms
Applications
TV, VCR and other decoding systems for US audio
multiplexing TV broadcasting
Structure
Bipolar silicon monolithic IC
SAPOUT
NC
VE
SAPIN
NC
NC
NC
VEWGT
VEOUT
VETC
V
∗ A license of the dbx-TV noise reduction system is
required for the use of this device.
Pin Configuration (Top View)
VCAIN
W
Range of Operating Supply Voltage
9 ± 0.5
Standard I/O Level
• Input level
COMPIN (Pin 12)
VCATC
V
°C
°C
36 35 34 33 32 31 30 29 28 27 26 25
VCAWGT 37
24 NOISETC
23 STIN
SOUT 38
ESAPIN 39
22 SUBOUT
TVOUT-S 40
21 NC
AUX1-R 41
20 VCC
AUX1-L 42
19
NC
18 SAPTC
NC 43
AUX2-R 44
17 GND
AUX2-L 45
16 NC
TVOUT-R 46
15
TVOUT-L 47
14 VGR
IREF
13 NC
4
5
6
7
8
9 10 11 12
SCL
MANIN
MAINOUT
NC
NC
NC
PCINT1
PCINT2
PLINT
3
COMPIN
2
NC
1
DGND
SDA 48
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97725A86
33
32
28
23
27
25
48
1
2
SPECTRAL
15
SW
LPF
14
"PONRES"
LPF
RMSDET
VGR
I2C BUS I/F
AMP
(+4dB)
HPF
VE
IREF
IREF
SAPIND
DeEm
LOGIC
NRSW/FOMO/SAPC
DGND
SAPTC 18
"SAP"
"NOISE"
LPF
(+6dB)
LPF
WIDEBAND
SCL
NOISETC
NOISE
DET
SAPVCO
DeEm
VCA
SDA
24
BPF
STIND
"STEREO"
LPF
1/2
4
SAPOUT
GND 17
LPF
FLT
1/4
22
SAPIN
VCC 20
ATT/INSW
VCO
9
PCINT1
LFLT
11
PCINT2
STIN
COMPIN 12
VCA
STLPF
PLINT
8
36
37
35
34
RMSDET
VCA
MATRIX
3
VEOUT
SUBOUT
VE
MAININ
VCAIN
MAINOUT
VETC
VEWGT
FEXT1
TVSW/EXT/M1
VCAWGT
–2–
VCATC
41
AUX1-L
42
LPF
TVSW
AUX1-R
Block Diagram
FEXT2
AUX2-R
38 SOUT
39 ESAPIN
40 TVOUT-S
46 TVOUT-R
47 TVOUT-L
44
45 AUX2-L
CXA2094Q
CXA2094Q
Pin Description
Pin
No.
Symbol
(Ta = 25°C, VCC = 9V)
Pin
voltage
Equivalent circuit
Description
VCC
7.5k
↓ 35µ
2.1V
4k
1
SCL
—
×4
10.5k
3k
Serial clock input pin.
VIH > 3.0V
VIL < 1.5V
1
2
DGND
2
—
Digital block GND.
VCC
10k
VCC
3
MAININ
Input the (L + R) signal from
MAINOUT (Pin 4).
4.0V
147
3
53k
4V
VCC
15k
×4
VCC
4
MAINOUT
4.0V
147
(L + R) signal output pin.
4
↓
200µ
1k
5
NC
—
5
—
6
NC
—
6
—
7
NC
—
7
—
–3–
CXA2094Q
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
147
8
8
PCINT1
30k
4.0V
22k
Stereo block PLL loop filter
integrating pin.
VCC
147
9
9
PCINT2
10k
4.0V
10k
2k
×2
4k
10
NC
—
—
10
VCC
20k
20k
Pilot cancel circuit loop filter
integrating pin.
(Connect a 1µF capacitor
between this pin and GND.)
147
11
PLINT
11
5.1V
20k
20k
↓
26µ
20k
24k
24k
↓
50µ
10k
VCC
14k 147
12
12
COMPIN
4.0V
Audio multiplexing signal
input pin.
34k
4V
24k
13
NC
—
—
13
–4–
CXA2094Q
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
3k
14
VGR
1.3V
9.7k
11k
147
VCC
19.4k
×4
Description
11k
11k
15k
30k
Band gap reference output
pin.
(Connect a 10µF capacitor
between this pin and GND.)
14
2.06k
VCC
40k
40k
30k
30k
×2
VCC
15
IREF
1.3V
30p 1.8k
15
147
6.3k
16
NC
—
17
GND
—
Set the filter and VCO
reference current. The
reference current is adjusted
with the BUS DATA based
on the current which flows to
this pin.
(Connect a 62kΩ (±1%)
resistor between this pin and
GND.)
16k
—
16
17
Analog block GND.
VCC
8k
10k
1k
3k
18
SAPTC
4.5V
VCC
4k
↓ 50µ
Set the time constant for the
SAP carrier detection circuit.
(Connect a 4.7µF capacitor
between this pin and GND.)
18
19
NC
—
19
20
VCC
—
20
21
NC
—
21
—
Supply voltage pin.
—
–5–
CXA2094Q
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
Vcc
2k
2k
10P
4k
580
22
SUBOUT
4.0V
(L-R) signal output pin.
22
14.4k
2k
580 147
2k
4k
2k
1k
VCC
23
STIN
23k
4.0V
23k
Input the (L-R) signal from
SUBOUT (Pin 22).
11.7k
147
147
23
27
SAPIN
4.0V
27
18k
Input the (SAP) signal from
SAPOUT (Pin 25).
18k
4V
4V
20k
Vcc
8k
3.3k
10k
1k
24
NOISETC
3.0V
2k
4k
×2
4V
Vcc
3k
Set the time constant for the
noise detection circuit.
(Connect a 4.7µF capacitor
between this pin and GND.)
3k
200k
24
Vcc
5P
580
25
SAPOUT
580
4.0V
10k
SAP FM detector output pin.
25
147
24k
↓ 10µ
4k
↓ 50µ
–6–
CXA2094Q
Pin
No.
26
Symbol
NC
Pin
voltage
Equivalent circuit
—
Description
—
26
VCC
7.5k
Variable de-emphasis
integrating pin.
(Connect a 2700pF capacitor
and a 3.3kΩ resistor in series
between this pin and GND.)
147
28
VE
4.0V
29
NC
—
29
—
30
NC
—
30
—
31
NC
—
31
—
28
Vcc
2.9V
580
32
VEWGT
4.0V
4V
32
36k
147
580
30k
↓ 8µ
8k
Weight the variable
de-emphasis control effective
value detection circuit.
(Connect a 0.047µF capacitor
and a 3kΩ resistor in series
between this pin and GND.)
4k
↓ 50µ
Vcc
33
VETC
1.7V
×4
33
×4
20k
↓ 7.5µ
4k
↓ 50µ
–7–
Determine the restoration
time constant of the variable
de-emphasis control effective
value detection circuit.
(The specified restoration
time constant can be obtained
by connecting a 3.3µF
capacitor between this pin
and GND.)
CXA2094Q
Pin
No.
Symbol
Pin
voltage
Description
Equivalent circuit
Vcc
5P
Variable de-emphasis output
pin.
(Connect a 4.7µF non-polar
capacitor between Pins 34
and 35.)
580
34
VEOUT
4.0V
34
10k
580
VCC
47k
35
VCAIN
20k
4.0V
47k
VCA input pin.
Input the variable
de-emphasis output signal
from Pin 34 via a coupling
capacitor.
VCC
35
VCC
×4
36
VCATC
Determine the restoration
time constant of the VCA
control effective value
detection circuit.
(The specified restoration
time constant can be
obtained by connecting a
10µF capacitor between this
pin and GND.)
36
×4
1.7V
4k
↓
50µ
20k
↓
7.5µ
VCC
40k
40k 3p
580
37
VCAWGT
4.0V
37
2.9V
580 147
36k
↓
50µ
4k ↓
8µ
30k
8k
–8–
Weight the VCA control
effective value detection
circuit.
(Connect a 1µF capacitor
and a 3.9kΩ resistor in series
between this pin and GND.)
CXA2094Q
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
VCC
15k
×4
38
SOUT
Additional SAP output pin.
4.0V
38
↓
200µ
1k
VCC
10k
147
39
ESAPIN
Input the signal from SOUT
(Pin 38).
39
4.0V
47k
4V
41
AUX1-R
4.0V
VCC
10k
42
AUX1-L
4.0V
41
27.5k
44
AUX2-R
42
4.0V
44
47k
AUX2-L
VCC
TVOUT-S
4.0V
46
TVOUT-R
4.0V
3k
580
40
46
Right channel external input
2 pin.
Left channel external input
2 pin.
4.0V
40
Left channel external input
1 pin.
45
4V
45
Right channel external input
1 pin.
Optional output pin.
From this pin monaural or
additional SAP is output.
TVOUT right channel output
pin.
580
47
47
TVOUT-L
43
NC
TVOUT left channel output
pin.
4.0V
—
—
43
–9–
CXA2094Q
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
7.5k
↓ 35µ
2.1V
4k
×2
48
SDA
—
7.5k
×5
4.5k
3k
48
– 10 –
Serial data I/O pin.
VIH > 3.0V
VIL < 1.5V
FCdeem
FCmain
Vsub
FCsub
Main de-emphasis
frequency characteristic
Main LPF frequency
characteristic
Main distortion
Main overload distortion
Main S/N
Sub output level
Sub LPF frequency
characteristic
Sub distortion
Sub overload distortion
Sub S/N
ST → SAP
Crosstalk
3
4
5
6
– 11 –
7
8
9
10
11
12
13
CTst
SNsub
THDsmax
THDsub
SNmain
THDmmax
THDm
Vmain
Main output level
2
Icc
Signal
Current consumption
Item
SAP
ST
ST
ST
ST
ST
MONO
MONO
MONO
MONO
MONO
MONO
Mode
12
12
12
12
12
12
12
12
12
12
12
12
—
Input pin
Min.
15kLPF
Mono 1kHz,
Pre-em. ON
15kLPF
15kLPF
20 log
('100%'/ '0%')
20 log
('NRSW = 0'/
'NRSW = 1')
SUB (L-R) 1kHz,
200% mod., NR OFF
SUB (L-R) 1kHz,
NR OFF
SUB (L-R) 1kHz,
100% mod., NR ON,
SAP Carrier (5fH)
1kBPF
15kLPF
20 log
('12k'/ '1k')
SUB (L-R) 1kHz,
100% mod., NR OFF
SUB (L-R) 12kHz,
30% mod., NR OFF
SUB (L-R) 1kHz,
100% mod., NR OFF
15kLPF
Mono 1kHz 200% mod.
Pre-em. OFF
20 log
('100%'/ '0%')
46/47
15kLPF
Mono 1kHz 100% mod.
Pre-em. ON
47
22
22
22
22
22
46/47
46/47
46/47
46/47
Mono 12kHz 30% mod. 20 log
Pre-em. ON
('12k'/ '1k')
Mono 5kHz 30% mod.
Pre-em. ON
60
56
–
–
–3.0
150
61
–
–
–3.0
–1.2
440
46/47
Output
pin
Mono 1kHz 100% mod.
Pre-em. ON
Filter
22
20 log
('5k'/ '1k')
Measurement
conditions
No signal
Input signal
= 147mVrms = 60mVrms
SAP Carrier
fH = 15.734kHz
= 49mVrms
Pilot
= 20mVrms
= 490mVrms = 200mVrms
SUB (L – R) (dbx-TV : OFF)
INSW = 1
= 245mVrms = 100mVrms
INSW = 0
Main (L + R)
(Pre-Emphasis : OFF)
1
No.
Electrical Characteristics
COMPIN input level
(100% modulation level)
70
64
0.2
0.1
–0.5
190
69
0.15
0.1
–1.0
0
490
32
Typ.
–
–
2.0
1.0
1.0
230
–
0.5
0.5
1.0
1.0
540
42
Max.
dB
dB
%
%
dB
mVrms
dB
%
%
dB
dB
mVrms
mA
Unit
(Ta = 25°C, VCC = 9V)
CXA2094Q
– 12 –
41/42
44/45
EXT
INT
THDsap
SNsap
CTsap
HYsap
STLsep1
STRsep1
STLsep2
STRsep2
Vtv
CTtv1
SAP distortion
SAP S/N
SAP → ST
Cross talk
SAP ON level
SAP ON/OFF hysteresis
ST separation 1 L → R
ST separation 1 R → L
ST separation 2 L → R
ST separation 2 R → L
TVOUT output level
19
20
21
22
23
24
25
26
27
28
32
MUtv2
EXT
INT
MUtv1
31
TVOUT
muted amount
EXT
CTtv2
ST
ST
ST
SAP
ST
SAP
SAP
30
TVOUT cross talk
Sine wave 1kHz,
490mVrms
41/42
44/45
ST
FCsap
SAP LPF frequency
characteristic
18
29
ST-R 3kHz 30% mod.
NR ON
Sine wave 1kHz,
490mVrms
12
SAP
Vsap
SAP output level
17
THsap
SAP
HYst
41/42
44/45
12
12
12
12
12
12
12
12
12
12
12
20 log
('100%'/ '0%')
20 log
('10k'/ '1k')
20 log (‘on
level'/ 'off level')
0dB = 49mVrms
0dB = 49mVrms
Measurement
conditions
MONO 1kHz 100% mod. 0dB = 490mVrms
Pre-em. ON
INT → EXT
MONO 1kHz 100% mod. 20 log (M1 =
Pre-em. ON
"0"/M1 = "1")
Sine wave 1kHz,
20 log (M1 =
490mVrms
"0"/M1 = "1")
0dB = 490mVrms
EXT → INT
15kLPF
ST-L 3kHz 30% mod.
NR ON
0dB = 490mVrms
15kLPF
ST-R 300Hz 30% mod.
NR ON
1kBPF
1kBPF
1kBPF
15kLPF
15kLPF
20 log (‘on
level’/’off level’)
0dB = 147mVrms
1kBPF
15kLPF
15kLPF
fH BPF
Filter
ST-L 300Hz 30% mod.
NR ON
Change
SAP Carrier (5fH)
Level
SAP 1kHz 100% mod. 20 log ('NRSW
NR ON, Pilot (fH)
= 1'/ 'NRSW = 0')
SAP 1kHz, NR OFF
SAP 1kHz 100% mod.
NR OFF
SAP 10kHz 30% mod.
NR OFF
SAP 1kHz 100% mod.
NR OFF
Change
PILOT (fH) Level
Stereo ON/OFF
hysteresis
12
16
ST
THst
PILOT (fH) 0dB
Input signal
Stereo ON level
12
Input pin
15
ST
Mode
PCsub
Symbol
Sub pilot leak
Item
14
No.
46/47
46/47
46/47
46/47
46/47
46/47
46/47
46/47
BUS
RETURN
47
25
25
25
25
BUS
RETURN
22
Output
pin
–90
–85
–
–
–90
–75
0
35
35
35
35
4.0
–9.0
70
55
2.5
0
190
6.0
–6.0
–42
Typ.
–
–
–0.5
23
23
23
23
2.0
–12.0
60
46
–
–3.0
150
2.0
–9.0
–
Min.
–75
–70
–80
–60
0.5
–
–
–
–
6.0
–6.5
–
–
6.0
2.5
230
10.0
–3.0
–30
Max.
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
%
dB
mVrms
dB
dB
dB
Unit
CXA2094Q
THDtv
SNtv
TVOUT distortion
TVOUT S/N
TVOUT overload distortion
34
35
36
THDtvmax
OStv
Symbol
TVOUT DC offset
Item
33
No.
Sine wave 1kHz,
490mVrms
Sine wave 1kHz,
2Vrms
41/42
44/45
41/42
44/45
EXT
EXT
Sine wave 1kHz,
490mVrms
41/42
44/45
EXT
No signal
—
INT
EXT
Input signal
Input pin
Mode
20 log
('490mVrms'/
'No signal')
Mute (M1 = 0)/
DC difference
when there is
no signal
Measurement
conditions
15kLPF
15kLPF
15kLPF
Filter
46/47
46/47
46/47
46/47
Output
pin
–
75
–
–25
Min.
0.1
88
0.01
0
Typ.
1.0
–
0.5
25
Max.
%
dB
%
mV
Unit
CXA2094Q
– 13 –
SIGNAL
GENERATOR
C3
4.7µ
V3
AC
C8
4.7µ
C7
4.7µ
V2
AC
V1
AC
SIGNAL
GENERATOR
C4
4.7µ
C2
1µ
V4
AC
C1
4.7µ
R1
3.9k
R2
220
C5
4.7µ
C6
SIGNAL
GENERATOR 4.7µ
SIGNAL
GENERATOR
VCAWGT
1
2
DGND
R3
220
I2C BUS DATA
48 SDA
47 TVOUT-L
46 TVOUT-R
45 AUX2-L
44 AUX2-R
43 NC
42 AUX1-L
41 AUX1-R
40 TVOUT-S
39 ESAPIN
38 SOUT
37
3
C11
4.7µ
33
34
C12
3.3µ
35
C18
4.7µ
36
TANTALUM
VCATC
DGND
VCAIN
MAININ
C9
10µ
4
FILTERS
29
30
VEWGT
5
6
R6
1MEG
C14
5600p
7
9
10
C18
1µ
11
24
STIN 23
NOISETC
25
SAPOUT
GND
12
C20
10µ
METAL
± 1%
R8
62k
C21
4.7µ
C22
100µ
C24
4.7µ
C23
4.7µ
V5 SIGNAL
AC GENERATOR
NC 13
VGR 14
IREF 15
NC 16
GND 17
SAPTC 18
NC 19
VCC 20
NC 21
SUBOUT 22
C19
4.7µ
C17
4.7µ
26
MEASURES
C16
2700p
27
28
R5
C15
100k 0.012µ
8
R7
3.3k
15kHz LPF
fH BPF
1kHz BPF
R4
3k
C13
0.047µ
32
31
NC
NC
NC
NC
PCINT1
NC
NC
VEOUT
MAINOUT
BUFF
PCINT2
S5
S4
S3
S2
S1
NC
PLINT
VE
SAPIN
NC
VETC
SCL
– 14 –
COMPIN
Electrical Characteristics Measurement Circuit
GND
GND
VCC
V6
9V
CXA2094Q
TANTALUM
CXA2094Q
Adjustment Method (Input signal level is the case when standard input signal is 245mVrms)
1. ATT adjustment
1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.
2) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the TVOUT-L output level. Then,
adjust the “ATT” data for ATT adjustment so that the TVOUT-L output goes to the standard value
(490mVrms).
3) Adjustment range: ±30%
Adjustment bits:
4 bits
2. Separation adjustment
1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.
2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300Hz
NR-ON) to COMPIN. At this time, adjust the “WIDEBAND” adjustment data to reduce TVOUT-R output
to the minimum.
3) Next, set the frequency only of the input signal to 3kHz and adjust the “SPECTRAL” adjustment data to
reduce TVOUT-R output to the minimum.
4) The adjustments in 2 and 3 above are performed to optimize the separation.
5) “WIDEBAND”
“SPECTRAL”
Adjustment range: ±30%
Adjustment range: ±15%
Adjustment bits:
6 bits
Adjustment bits: 6 bits
∗ Adjust this through Tuner and IF when this IC is mounted on the set.
– 15 –
CXA2094Q
Description of Operation
The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.
PEAK DEV
kHz
50
AM-DSB-SC
50
L-R
dbx-TV
NR
25
PILOT
25
15
SAP
dbx-TV NR
FM 10kHz
50 – 10kHz
L+R
5
50 – 15kHz
2fH
fH
3fH
4fH
TELEMETRY
FM 3kHz
3
5fH
6fH
6.5fH
f
fH = 15.734kHz
Fig. 1. Base band spectrum
2fHL0°
fHL90°
fHL0°
PLL
(VCO 8fH)
STEREO LPF
(COMPIN)
12
I2C BUS
DECODER
MODE
CONTROL
PILOT
DET
MAIN LPF DE.EM
(MAIN OUT)
PILOT
CANCEL
MVCA
3
4.7µ
L+R
SUB LPF
L-R (DSB)
DET
WIDEBAND
(SUBOUT) (ST IN)
SUBVCA
SAP BPF
MATRIX
23
22
L–R
SAP(FM)
DET
(MAIN IN)
4
(Lch)
4.7µ
NR SW
A
SAP LPF
INJ.
LOCK
(SAP OUT)
(SAP IN)
25
27
dbx-TV
BLOCK
B
40
I 2C BUS
DECODER
LPF
2
I C BUS
DECODER
MODE
CONTROL
SAP
DET
(SOUT)
MODE
CONTROL
(ESAPIN)
38
39
4.7µ
Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)
FIXED
VARIABLE
DEEMPHASIS DEEMPHASIS
(ST IN)
23
NR SW
A
(VE OUT) (VCA IN)
35
34
(SAP IN)
4.7µ
27
HPF
RMS
DET
LPF
LPF
RMS
DET
Fig 3. dbx-TV block
– 16 –
to
TVSW
(TVOUT-S)
4.7µ
NOISE
DET
(Rch)
B
VCA
to
MATRIX
CXA2094Q
(AUX2-L) (AUX2-R)
44
45
(TVOUT-L)
(AUX1-L)
47
42
TVSW
41
46
(TVOUT-R)
(AUX1-R)
(Lch)
(Rch)
from MATRIX
Fig. 4. Switch block
(1) L + R (MAIN)
After the audio multiplexing signal input from COMPIN (Pin 12) passes through MVCA, the SAP signal
and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the
L – R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened
(de-emphasized) and input to the matrix.
(2) L – R (SUB)
The L – R signal follows the same course as L + R before the pilot signal is canceled. L – R has no
carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM
modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave)
to be used for the demodulation of the L – R signal. In the last stage, the residual high frequency
components are removed by SUB LPF and the L – R signal is input to the dbx-TV block via the NRSW
circuit after passing through SUBVCA.
(3) SAP
SAP is an FM signal using 5fH as a carrier as shown in the Fig. 1. First, the SAP signal only is
extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency
components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal
is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 25 output is
soft muted.
(4) Mode discrimination
Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is
performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the
noise near 25kHz after FM detection of SAP signal.
(5) dbx-TV block
Either the L – R signal or SAP signal input respectively from ST IN (Pin 23) or SAP IN (Pin 27) is
selected by the mode control and input to the dbx-TV block.
The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external
capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a
current to a voltage using an operational amplifier and then input to the matrix.
– 17 –
CXA2094Q
The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of
effective value detection circuits. Each of the effective value detection circuits passes the input signal
through a predetermined filter for weighting before the effective value of the weighted signal is
detected to provide the control signal.
(6) Matrix, TVSW
The signals (L + R, L – R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and
SAP signals according to the mode control and whether there is ST / SAP discrimination.
“TVSW” switches the “MATRIX” output signal, external input signal (input to AUX1-L, R (Pins 42 and
41)), external input signal (input to AUX2-L, R (Pins 45 and 44)) and external forced MONO.
(7) Others
“MVCA” is a VCA which adjusts the input signal level to the standard level of this IC.
“Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to
the resistor connecting IREF (Pin 15) with GND become the reference current.
– 18 –
CXA2094Q
Register Specifications
Slave address
SLAVE RECEIVER SLAVE TRANSMITTER
84H (1000 0100)
85H (1000 0101)
Register table
DATA
SUB ADDRESS
MSB
LSB
BIT7
BIT6
BIT5
BIT4
BIT3
TEST-DA
TEST1
BIT2
BIT1
BIT0
∗∗∗∗0000
∗
∗∗∗∗0001
∗
SPECTRAL (6)
∗∗∗∗0010
∗
WIDEBAND (6)
∗∗∗∗0011
∗
TVSW
EXT
NRSW
FOMO
SAPC
M1
∗∗∗∗0100
∗
INSW
SMD
ATTSW
FST
FEXT1
FEXT2
ATT (4)
∗ : Don't Care
Status Registers
STA1
STA2
STA3
STA4
STA5
STA6
STA7
STA8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
SAP
NOISE
—
—
—
—
POWER
STEREO
ON RESET
– 19 –
CXA2094Q
Description of Registers
Control registers
Number
of bits
Classification∗1
Standard
setting
ATT
4
A
9
SPECTRAL
6
A
1F
Adjustment of stereo separation (3kHz)
WIDEBAND
6
A
1F
Adjustment of stereo separation (300Hz)
TEST-DA
1
T
0
Turn to DAC test mode and VCO adjustment mode by means
of TEST-DA = 1.
TEST1
1
T
0
Turn to test mode by means of TEST = 1.
(Adjustment of FILTER)
FST
1
T
0
Turn to forced stereo by means of FST = 1.
NRSW
1
U
—
Selection of the output signal (Stereo mode, SAP mode)
FOMO
1
U
—
Turn to forced MONO by means of FOMO = 1.
(Left channel only is MONO during SAP output.)
TVSW
1
U
0
Selection of TV mode or external input mode for TVOUT
output
FEXT1
1
U
0
External input 1 forced MONO (1: forced MONO ON)
FEXT2
1
U
0
External input 2 forced MONO (1: forced MONO ON)
EXT
1
U
0
Selection of external input 1 mode or external input 2 mode
for TVOUT output. (TVSW = 1)
M1
1
U
1
Selection of TVOUT mute ON/OFF
(0: mute ON, 1: mute OFF)
SMD
1
U
0
Selection of L + R or additional SAP
ATTSW
1
S
—
Turn the input stage MVCA off when ATTSW = 1.
INSW
1
S
—
Selection of standard input level
SAPC
1
S
—
Selection of SAP mode or L + R mode according to the
presence of SAP broadcasting
Register
Contents
Input level adjustment
∗1 Classification U: User control
A: Adjustment
S: Proper to set
T: Test
Status registers
Register
Number of bits
Contents
PONRES
1
POWER ON RESET detection;
1: RESET
STEREO
1
Stereo discrimination of the COMPIN input signal;
1: Stereo
SAP
1
SAP discrimination of the COMPIN input signal;
1: SAP
NOISE
1
Noise level discrimination of the SAP signal;
1: Noise
– 20 –
CXA2094Q
Description of Control Registers
ATT (4):
Adjust the signal level input to COMPIN (Pin 12) to the standard input level.
Variable range of the input signal: standard input level –5.0dB to +3.0dB
0 = Level min.
F = Level max.
SPECTRAL (6): Perform high frequency (fs = 3kHz) separation adjustment.
0 = Level max.
3F = Level min.
WIDEBAND (6): Perform low frequency (fs = 300Hz) separation adjustment.
0 = Level min.
3F = Level max.
TEST-DA (1): Set DAC output test mode.
0 = Normal mode
1 = DAC output test mode
In addition, the following output are present at Pin 47.
TVOUT-L (Pin 47): DA control DC level
TEST1 (1):
Monitor SAP BPF and NR BPF output.
0 = Normal mode
1 = SAP BPF and NR BPF output
In addition, the following outputs are present at Pins 47 and 46.
TVOUT-L (Pin 47): SAP BPF OUT
TVOUT-R (Pin 46): NR BPF OUT
FST (1):
Select forced STEREO mode
0 = Normal mode
1 = Forced stereo mode
NRSW (1):
Select stereo mode or SAP mode
0 = Stereo mode
1 = SAP mode
– 21 –
CXA2094Q
FOMO (1):
Select forced MONO mode
0 = Normal mode
1 = Forced MONO mode
FEXT1 (1):
Turn external input [1] to forced MONO.
0 = Normal mode
1 = External input [1] is forced MONO.
Input the same signal to both AUX1-L and AUX1-R.
FEXT2 (1):
Turn external input [2] to forced MONO
0 = Normal mode
1 = External input [2] is forced MONO
Input the same signal to both AUX2-L and AUX2-R.
TVSW (1):
Select TV mode or external input mode for TVOUT output.
0 = TV mode
1 = External input mode
EXT (1):
Select external input [1] mode or external input [2] mode for TVOUT output. (TVSW = 1)
0 = External input [1] mode
1 = External input [2] mode
M1 (1):
Mute the TVOUT-L and TVOUT-R output.
0 = Mute ON
1 = Mute OFF
SMD (1):
Select L + R or additional SAP signal
0 = L + R output is selected
1 = additional SAP output is selected
ATTSW (1): Select BYPASS SW of MVCA
0 = Normal mode
1 = MVCA is passed
INSW (1):
Select standard input level of COMPIN (Pin 12)
0 = 245mVrms
1 = 100mVrms
SAPC (1):
Select the SAP signal output mode
When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC.
0 = L + R output is selected
1 = SAP output is selected
– 22 –
CXA2094Q
Description of Mode Control
Priority ranking: M1 > TVSW/EXT > (NRSW & FOMO & SAPC)
Mode control
NRSW
SAPC = 0
SAPC = 1
“Select dbx input and TV decoder output”
Conditions: FOMO = 0
NRSW = 0 (MONO or ST output)
“Select dbx input and TV decoder output”
Conditions: FOMO = 0
NRSW = 0 (MONO or ST output)
• During ST input:
left channel: L,
right channel: R
• During other input: left channel: L + R,
right channel: L + R
As on the left
NRSW = 1 (SAP output)
• When there is “SAP” during SAP
discrimination
– left channel: SAP, right channel: SAP
• When there is “No SAP”, output is the
same as when NRSW = 0.
NRSW = 1 (SAP output)
• Regardless of the presence of SAP
discrimination,
dbx input: “SAP”
left channel: SAP, right channel: SAP
However, when there is no SAP, SAPOUT
output is soft muted (–7dB)
“Forced MONO”
FOMO
SAPC
M1
TVSW/EXT
FOMO = 1
• During SAP output: left channel: L + R, right channel: SAP
• During ST or MONO output: left channel: L + R, right channel: L + R
Change the selection conditions for “MONO or ST output” and “SAP output”.
SAPC = 0: Switch to SAP output when there is SAP discrimination.
Do not switch to SAP output when there is no SAP discrimination.
SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination.
“MUTE”
M1 = 0: TVOUT-L, R, S output is muted.
“TV mode/external input mode selection”
TVSW = 0: Set TVOUT-L, R output to TV mode.
TVSW = 1: Set TVOUT-L, R output to external input mode.
EXT = 0: Set TVOUT-L, R output to external input [1] mode. (TVSW = 1)
EXT = 1: Set TVOUT-L, R output to external input [2] mode. (TVSW = 1)
– 23 –
CXA2094Q
Decoder Output and Mode Control Table 1 (SAPC = 1)
MONO ∗1
STEREO ∗1
MONO & SAP
STEREO & SAP
Mode control
Mode detection
Output
ST
SAP
NOISE
NRSW
FOMO
SAPC
dbx
input
0
0
0
0
∗
1
MUTE
L+R
L+R
0
0
0
1
0
1
SAP
SAP
SAP
0
0
0
1
1
1
SAP
L+R
SAP
0
∗
1
0
∗
1
MUTE
L+R
L+R
0
∗
1
1
0
1
(SAP)
(SAP)
(SAP)
0
∗
1
1
1
1
(SAP)
L+R
(SAP)
1
0
∗
0
0
1
L–R
L
R
1
0
∗
0
1
1
MUTE
L+R
L+R
1
1
1
0
0
1
L–R
L
R
1
1
1
0
1
1
MUTE
L+R
L+R
1
0
0
1
0
1
SAP
SAP
SAP
1
0
0
1
1
1
SAP
L+R
SAP
1
∗
1
1
0
1
(SAP)
(SAP)
(SAP)
1
∗
1
1
1
1
(SAP)
L+R
(SAP)
0
1
∗
0
0
1
MUTE
L+R
L+R
0
1
∗
0
1
1
MUTE
L+R
L+R
0
1
0
1
0
1
SAP
SAP
SAP
0
1
0
1
1
1
SAP
L+R
SAP
0
1
1
1
0
1
(SAP)
(SAP)
(SAP)
0
1
1
1
1
1
(SAP)
L+R
(SAP)
1
1
∗
0
0
1
L–R
L
R
1
1
∗
0
1
1
MUTE
L+R
L+R
1
1
0
1
0
1
SAP
SAP
SAP
1
1
0
1
1
1
SAP
L+R
SAP
1
1
1
1
0
1
(SAP)
(SAP)
(SAP)
1
1
1
1
1
1
(SAP)
L+R
(SAP)
Input signal mode
Lch
Rch
Note
(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).
The signal is soft muted when NOISE = 1.
∗ : Don’t care.
∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
inputted in the weak electric field.
Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
– 24 –
CXA2094Q
Decoder Output and Mode Control Table 2 (SAPC = 0)
Mode control
Mode detection
MONO ∗1
STEREO ∗1
MONO & SAP
STEREO & SAP
Output
ST
SAP
NOISE
NRSW
FOMO
SAPC
dbx
input
0
0
∗
∗
∗
0
MUTE
L+R
L+R
0
1
1
0
0
0
MUTE
L+R
L+R
0
1
1
0
1
0
MUTE
L+R
L+R
0
1
1
1
0
0
(SAP)
(SAP)
(SAP)
0
1
1
1
1
0
(SAP)
L+R
(SAP)
1
0
∗
0
0
0
L–R
L
R
1
0
∗
0
1
0
MUTE
L+R
L+R
1
0
∗
1
0
0
L–R
L
R
1
0
∗
1
1
0
MUTE
L+R
L+R
1
1
1
0
0
0
L–R
L
R
1
1
1
0
1
0
MUTE
L+R
L+R
1
1
1
1
0
0
(SAP)
(SAP)
(SAP)
1
1
1
1
1
0
(SAP)
L+R
(SAP)
0
1
0
0
0
0
MUTE
L+R
L+R
0
1
0
0
1
0
MUTE
L+R
L+R
0
1
0
1
0
0
SAP
SAP
SAP
0
1
0
1
1
0
SAP
L+R
SAP
0
1
1
0
0
0
MUTE
L+R
L+R
0
1
1
0
1
0
MUTE
L+R
L+R
0
1
1
1
0
0
(SAP)
(SAP)
(SAP)
0
1
1
1
1
0
(SAP)
L+R
(SAP)
1
1
0
0
0
0
L–R
L
R
1
1
0
0
1
0
MUTE
L+R
L+R
1
1
0
1
0
0
SAP
SAP
SAP
1
1
0
1
1
0
SAP
L+R
SAP
1
1
1
0
0
0
L–R
L
R
1
1
1
0
1
0
MUTE
L+R
L+R
1
1
1
1
0
0
(SAP)
(SAP)
(SAP)
1
1
1
1
1
0
(SAP)
L+R
(SAP)
Input signal mode
Lch
Rch
Note
(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).
The signal is soft muted when NOISE = 1.
∗ : Don’t care.
∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
inputted in the weak electric field.
Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
– 25 –
CXA2094Q
Mode Control Table 3
M1
TVSW
EXT
FEXT1
FEXT2
TVOUT-L
TVOUT-R
1
0
—
—
—
—
MUTE
MUTE
2
1
0
—
—
—
TV (L)
TV (R)
3
1
1
0
0
—
AUX1-L
AUX1-R
4
1
1
0
1
—
AUX1-L
AUX1-L
5
1
1
1
—
0
AUX2-L
AUX2-R
6
1
1
1
—
1
AUX2-L
AUX2-L
TV (L) / TV (R) are selected in MATRIX
TV (L): MONO, ST-L, SAP, (SAPBPFout, D/Aout)
TV (R): MONO, ST-R, SAP, (NRBPFout, STVCO freerun (4fH))
I2C BUS block items (SDA, SCL)
No.
Item
Symbol
Min.
Typ.
Max.
Unit
1
High level input voltage
VIH
3.0
—
5.0
2
Low level input voltage
VIL
0
—
1.5
3
High level input current
IIH
—
—
10
4
Low level input current
IIL
—
—
10
5
Low level output voltage SDA (Pin 48) during 3mA inflow VOL
0
—
0.4
V
6
Maximum inflow current
IOL
3
—
—
mA
7
Input capacitance
CI
—
—
10
pF
8
Maximum clock frequency
fSCL
0
—
100
kHz
9
Minimum waiting time for data change
tBUF
4.7
—
—
10
Minimum waiting time for start of data transfer
tHD: STA
4.0
—
—
11
Low level clock pulse width
tLOW
4.7
—
—
12
High level clock pulse width
tHIGH
4.0
—
—
13
Minimum waiting time for start preparation
tSU: STA
4.7
—
—
14
Minimum data hold time
tHD: DAT
0
—
—
15
Minimum data preparation time
tSU: DAT
250
—
—
ns
16
Rise time
tR
—
—
1
µs
17
Fall time
tF
—
—
300
ns
18
Minimum waiting time for stop preparation
tSU: STO
4.7
—
—
µs
I2C BUS load conditions: Pull-up resistor 4kΩ (Connect to +5V)
Load capacity 200pF (Connect to GND)
– 26 –
V
µA
µs
CXA2094Q
I2C BUS Control Signal
SDA
tBUF
tF
tR
tHD: STA
SCL
P
S tHD: STA
tLOW
tHD: DAT
tHIGH
tSU: STA
tSU: DAT
Sr
tSU: STO
P
I2C BUS Signal
There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal.
• Accordingly there are 3 values outputs, H, L and HIZ.
H
L
HIZ
L
• I2C transfer begins with Start Condition and ends with Stop Condition.
Start Condition S
Stop Condition P
SDA
SCL
– 27 –
CXA2094Q
• I2C data Write (Write from I2C controller to the IC)
L during Write
MSB
MSB
LSB
HIZ
SDA
1
SCL
2
3
4
5
6
7
8
HIZ
9
1
8
9
S
Address
MSB
ACK
Sub Address
ACK
LSB
HIZ
1
8
HIZ
9
DATA (n)
1
ACK
8
DATA (n + 1)
ACK
HIZ
8
9
DATA (n + 2)
HIZ
9
1
8
∗ Data can be transferred in 8-bit units to be
9
set as required.
Sub address is incremented automatically.
P
DATA
ACK
DATA
ACK
• I2C data Read (Read from the IC to I2C controller)
H during Read
HIZ
SDA
1
SCL
6
7
8
9
7
1
8
9
P
S
Address
ACK
DATA
ACK
• Read timing
MSB
LSB
IC output SDA
SCL
Read timing
9
1
2
3
4
DATA
ACK
∗ Data Read is performed during SCL rise.
– 28 –
5
6
7
8
9
ACK
CXA2094Q
Input level vs. Distortion characteristics 2 (Stereo)
Input level vs. Distortion characteristics 1 (MONO)
10
Input signal: Stereo L = –R
(dbx-TVNR ON), 1kHz
0dB = 100% modulation level
VCC = 9V, 30kHz using LPF, ST mode
Measurement point: TVOUT-L/R
Distortion [%]
Distortion [%]
1.0
Input signal: MONO (Pre-emphasis on), 1kHz
0dB = 100% modulation level
VCC = 9V, 30kHz using LPF
Measurement point: TVOUT-L/R
1.0
0.1
Standard level (100%)
–10
0
10
Standard level (100%)
Input level [dB]
–10
0
Input level [dB]
Input level vs. Distortion characteristics 3 (SAP)
Distortion [%]
10
Input signal: SAP (dbx-TVNR ON)
1kHz, 0dB = 100% modulation
level
VCC = 9V, 30kHz using LPF, SAP mode
Measurement point: TVOUT-L/R
1.0
Standard level (100%)
–10
0
Input level [dB]
10
– 29 –
10
CXA2094Q
Stereo LPF frequency characteristics
Main LPF and Sub LPF frequency characteristics
10
Gain (FC main and FC sub) [dB]
30
Gain [dB]
5
0
–5
20
10
0
–10
–20
–30
–40
–10
–50
0
20
40
60
80
1
100
2
5
7
10
20
50 70 100
Frequency [kHz]
Frequency [kHz]
SAP frequency characteristics and group delay
Additional SAP frequency characteristics
100
20
90
5fH
60
50
0
40
30
–10
20
Group delay
3.8fH
–20
20
40
60
80
6.2fH
100
Output level [mVrms]
Gain [dB]
70
Group delay [µs]
Gain
10
500
80
100% modulation
30% modulation
100
10% modulation
1% modulation
10
10
0.1
0
120
1.0
Frequency [kHz]
Frequency [kHz]
– 30 –
10
CXA2094Q
Package Outline
Unit: mm
48PIN QFP (PLASTIC)
15.3 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
12.0 – 0.1
36
25
0.15
24
48
13
13.5
37
12
0.8
+ 0.15
0.3 – 0.1
± 0.12 M
0.9 ± 0.2
1
+ 0.2
0.1 – 0.1
+ 0.35
2.2 – 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-48P-L04
LEAD TREATMENT
SOLDER / PALLADIUM
PLATING
EIAJ CODE
∗QFP048-P-1212-B
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
0.7g
JEDEC CODE
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
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