CXP7500P10/7500P11 CMOS 8-bit Single Chip Microcomputer Description The CXP7500P10/7500P11 is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time-base timer, on-screen display function, I2C bus interface, PWM output, remote control reception circuit, HSYNC counter, watchdog timer, 32kHz timer/counter besides the basic configurations of 8-bit CPU, ROM, RAM, I/O ports. The CXP7500P10/7500P11 also provides a sleep function that enables to lower the power consumption. CXP7500P10/7500P11 is the PROM-incorporated version of the CXP750096/750010/750097/750011 with built-in mask ROM. This provides the additional feature of being able to write directly into the program. Thus, it is most suitable for evaluation use during system development and for small-quantity production. 64 pin SDIP (Plastic) 64 pin QFP (Plastic) 52 pin SDIP (Plastic) Features • A wide instruction set (213 instructions) which covers various types of data – 16-bit operation/multiplication and division/ Boolean bit operation instructions • Minimum instruction cycle 167ns at 24MHz operation 122µs at 32kHz operation Structure • Incorporated ROM 120K bytes Silicon gate CMOS IC • Incorporated RAM 2496 bytes (Excludes VRAM for on-screen display) • Peripheral functions – A/D converter 8-bit 6-channel successive approximation method (Conversion time of 3.25µs at 16MHz) – Serial interface 8-bit clock sync type (MSB/LSB first selectable), 1 channel – Timer 8-bit timer 8-bit timer/counter 19-bit time-base timer 32kHz timer/counter – On-screen display (OSD) function 24 × 32 dots, 512 character types, 15 character colors, 2 lines × 32 characters, frame background 8 colors/half blanking, background on full screen 15 colors/half blanking edging/shadowing/rounding for every line, background with shadow for every character, double scanning, Sprite OSD 24 × 32 dots, 1 screen, 8 colors for every dot – I2C bus interface – PWM output 8 bits, 8 channels 14 bits, 1 channel – Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO – HSYNC counter 2 channels – Watchdog timer • Interruption 13 factors, 13 vectors, multi-interruption possible • Standby mode Sleep • Package 64-pin plastic SDIP/QFP, 52-pin plastic SDIP • Piggy/evaluation chip CXP750000 64-pin ceramic PQFP/PSDIP (Supports custom font) Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99104-PS HSYNC COUNTER 1 ON SCREEN DISPLAY XLC EXLC R G B I YS YM HSYNC VSYNC HS1 8-BIT TIMER 1 TO HSYNC COUNTER 0 8-BIT TIMER/ COUNTER 0 EC HS0 SERIAL INTERFACE UNIT SI SO SCK FIFO 2 2 I2C BUS INTERFACE UNIT SDA0 REMOCON INTERRUPT CONTROLLER INT0 INT1 INT2 SDA1 RMC SCL0 A/D CONVERTER SCL1 6 2 ADJ AN0 to AN5 8 (6) PC0 to PC5∗ PC6, PC7∗ 6 2 PE2, PE3 PE4 to PE6 PF0 to PF7 2 3 8 5 PG3 to PG6∗, PG7 PE0, PE1 2 PD0 to PD7 PB0 to PB7 8 8 PA0 to PA7 8 ∗ Not incorrporated for 52-pin package. Parentheses indicate configurations for 52-pin package. 14 BITS PWM 1CH RAM 2496 BYTES CLOCK GENERATOR/ SYSTEM CONTROL TEX TX EXTAL XTAL RST VDD VSS Vpp 8 BITS PWM 8CH (6CH) 32kHz TIMER/COUNTER WATCHDOG TIMER PRESCALER/ TIME-BASE TIMER ROM 120K BYTES SPC 700αII CPU CORE PWM0 to PWM7 –2– PWM PORT A PORT B PORT C PORT D PORT E PORT F PORT G Block Diagram CXP7500P10/7500P11 CXP7500P10/7500P11 Pin Assignment (Top View) 64-pin SDIP PC3 1 64 PC4 PC2 2 63 PC5 PC1 3 62 PC6/PWM6 PC0 4 61 PC7/PWM7 PD7/EC 5 60 PF0/PWM0 PD6/RMC 6 59 PF1/PWM1 PD5/HS1 7 58 PF2/PWM2 PD4/HS0 8 57 PF3/PWM3 PD3/SI 9 56 PF4/SCL0 PD2/SO 10 55 PF5/SCL1/PWM4 PD1/SCK 11 54 PF6/SDA0 PD0/INT2 12 53 PF7/SDA1/PWM5 PA7/HSYNC 13 52 PE0/TO/ADJ PA6/VSYNC 14 51 PE1/PWM RST 15 50 PE2/TEX/INT0 VSS 16 49 PE3/TX XTAL 17 48 VSS EXTAL 18 47 VDD PA5/AN5 19 46 Vpp PA4/AN4 20 45 EXLC PA3/AN3 21 44 XLC PA2/AN2 22 43 PE4/YM PA1/AN1 23 42 PE5/YS PA0/AN0 24 41 PE6/I PB7 25 40 B PB6 26 39 G PB5 27 38 R PB4 28 37 PB0 PB3 29 36 PB1 PG7/INT1 30 35 PB2 PG6 31 34 PG3 PG5 32 33 PG4 Note) 1. Vpp (Pin 46) is left open. 2. Vss (Pins 16 and 48) are both connected to GND. –3– CXP7500P10/7500P11 PF2/PWM2 PF1/PWM1 PF0/PWM0 PC7/PWM7 PC6/PWM6 PC5 PC4 PC3 PC1 PC2 PC0 PD7/EC PD6/RMC Pin Assignment (Top View) 64-pin QFP 64 63 62 61 60 59 58 57 56 55 54 53 52 PD5/HS1 1 51 PF3/PWM3 PD4/HS0 2 50 PF4/SCL0 PD3/SI 3 49 PF5/SCL1/PWM4 PD2/SO 4 48 PF6/SDA0 PD1/SCK 5 47 PF7/SDA1/PWM5 PD0/INT2 6 46 PE0/TO/ADJ PA7/HSYNC 7 45 PE1/PWM PA6/VSYNC 8 44 PE2/TEX/INT0 RST 9 43 PE3/TX VSS 10 42 VSS XTAL 11 41 VDD EXTAL 12 40 Vpp PA5/AN5 13 39 EXLC PA4/AN4 14 38 XLC PA3/AN3 15 37 PE4/YM PA2/AN2 16 36 PE5/YS PA1/AN1 17 35 PE6/I PA0/AN0 18 34 B PB7 19 33 G R PB0 PB1 PB2 PG3 PG4 PG5 PG6 PB3 PG7/INT1 PB4 PB5 PB6 20 21 22 23 24 25 26 27 28 29 30 31 32 Note) 1. Vpp (Pin 40) is left open. 2. Vss (Pins 10 and 42) are both connected to GND. –4– CXP7500P10/7500P11 Pin Assignment (Top View) 52-pin SDIP 1 52 PF0/PWM0 PD6/RMC 2 51 PF1/PWM1 PD5/HS1 3 50 PF2/PWM2 PD4/HS0 4 49 PF3/PWM3 PD3/SI 5 48 PF4/SCL0 PD2/SO 6 47 PF5/SCL1/PWM4 PD1/SCK 7 46 PF6/SDA0 PD7/EC PD0/INT2 8 45 PF7/SDA1/PWM5 PA7/HSYNC 9 44 PE0/TO/ADJ PA6/VSYNC 10 43 PE1/PWM RST 11 42 PE2/TEX/INT0 VSS 12 41 PE3/TX XTAL 13 40 VSS EXTAL 14 39 VDD PA5/AN5 15 38 Vpp PA4/AN4 16 37 EXLC PA3/AN3 17 36 XLC PA2/AN2 18 35 PE4/YM PA1/AN1 19 34 PE5/YS PA0/AN0 20 33 PE6/I PB7 21 32 B PB6 22 31 G PB5 23 30 R PB4 24 29 PB0 PB3 25 28 PB1 PG7/INT1 26 27 PB2 Note) 1. Vpp (Pin 38) is left open. 2. Vss (Pins 12 and 40) are both connected to GND. –5– CXP7500P10/7500P11 Pin Description I/O Symbol PA0/AN0 to PA5/AN5 I/O/ Analog input PA6/VSYNC I/O/Input PA7/HSYNC I/O/Input PB0 to PB7 I/O Description (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) Analog inputs to A/D converter. (6 pins) OSD display vertical sync signal input. OSD display horizontal sync signal input. (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) (Port C) Lower 6 bits are I/O ports; I/O can be set in a unit of single bits. Upper 2 bits are output port and large current (12mA) N-channel open drain output. Upper 2 bits are medium drive voltage (12V); lower 6 bits are 5V drive. (8 pins) 8-bit PWM output. (2 pins) PC0 to PC5∗ I/O PC6/PWM6∗ to PC7/PWM7∗ Output/Output PD0/INT2 I/O/Input PD1/SCK I/O/I/O PD2/SO I/O/Output PD3/SI I/O/Input PD4/HS0 I/O/Input PD5/HS1 I/O/Input PD6/RMC I/O/Input Remote control reception circuit input. PD7/EC I/O/Input External event input for timer/counter. PE0/TO/ADJ I/O/Output/ Output Rectangular wave output for 8-bit timer/counter. PE1/PWM I/O/Output PE2/TEX/INT0 Input/Input/ Input PE3/TX Input PE4/YM Output/Output PE5/YS Output/Output PE6/I Output/Output B Output G Output R Output External interruption request input. Active at the falling edge. (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sink current. (8 pins) (Port E) Bits 0 and 1 are I/O port; I/O can be set in a unit of single bits. Bits 2 and 3 are input port. Bits 4, 5 and 6 are output port. (7 pins) Serial clock I/O. Serial data output. Serial data input. HSYNC counter (CH0) input. HSYNC counter (CH1) input. 14-bit PWM output. External interruption Connects a crystal for request input. Active at 32kHz timer/counter the falling edge. clock oscillation. When used as an event counter, input to TEX pin and leave TX pin open. OSD display 6-bit output. (6 pins) ∗ Not incorporated for 52-pin package. –6– TEX oscillation frequency dividing output. CXP7500P10/7500P11 Symbol I/O Description (Port F) 8-bit output port and large current (12mA) N-channel open drain output. Lower 4 bits are medium drive voltage (12V); upper 4 bits are 5V drive. (8 pins) 8-bit PWM output. (4 pins) PF0/PWM0 to PF3/PWM3 Output/Output PF4/SCL0 Output/I/O PF5/SCL1/ PWM4 Output/I/O/ Output PF6/SDA0 Output/I/O PF7/SDA1/ PWM5 Output/I/O/ Output PG3 to PG6∗ I/O PG7/INT1 I/O/Input EXTAL Input Connects a crystal for system clock oscillation. When a clock is supplied externally, input to EXTAL pin and input a reversed phase clock to XTAL pin. RST Input System reset; active at Low level. EXLC Input OSD display clock oscillation I/O. Oscillation frequency is determined by the external L and C. XTAL XLC I2C bus interface transfer clock I/O. (2 pins) 8-bit PWM output. I2C bus interface transfer data I/O. (2 pins) 8-bit PWM output. (Port G) 5-bit I/O port. I/O can be set in a unit of single bits. (5 pins) External interruption request input. Active at the falling edge. Vpp Positive power supply for incorporated PROM writing. Leave this pin open during normal operation. VDD Positive power supply. Vss GND. Connect two Vss pins to GND. ∗ Not incorporated for 52-pin package. –7– CXP7500P10/7500P11 Input/Output Circuit Formats for Pins Pin Circuit format After a reset Port A Port A data Port A direction PA0/AN0 to PA5/AN5 “0” after a reset Input protection circuit RD (Port A) Port A function selection 6 pins Hi-Z IP Internal data bus “0” after a reset A/D converter Input multiplexer Port A Port A data Port A direction “0” after a reset PA6/VSYNC PA7/HSYNC Schmitt input Internal data bus Hi-Z IP RD (Port A) HSYNC, VSYNC Input polarity 2 pins “0” after a reset Port B Ports B, C, G data Port C PB0 to PB7 PC0 to PC5∗ PG3 to PG6∗ PG7/INT1 Port G Ports B, C, G direction “0” after a reset PB0 to PB2 Schmitt input only for PG7 Internal data bus Hi-Z IP RD (Ports B, C, G) 19 pins INT1 Port C PC6/PWM6∗ PC7/PWM7∗ PF0/PWM0 to PF3/PWM3 Port F PWM0 to PWM3 PWM6, PWM7 Ports C, F function selection ∗ “0” after a reset Hi-Z Ports C, F data ∗ 12V drive voltage Large current 12mA “1” after a reset Internal data bus 6 pins RD (Ports C, F) ∗ Not incorporated for 52-pin package. –8– CXP7500P10/7500P11 Pin Circuit format After a reset Port D Port D data PD0/INT2 PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC Port D direction ∗ “0” after a reset Hi-Z Schmitt input Internal data bus IP RD (Port D) 6 pins ∗ Large current 12mA INT2, SI, HS0, HS1, RMC, EC Port D SCK, SO SIO output enable Port D data PD1/SCK PD2/SO ∗ Port D direction Hi-Z “0” after a reset Schmitt input only for PD1 Internal data bus IP RD (Port D) 2 pins ∗ Large current 12mA SCK only Port E “1” after a reset PE0/TO/ADJ Port E data 00 “1” after a reset TO ADJ16K ∗1 ADJ2K ∗1 01 10 11 MPX ∗2 Port E function selection (Upper) Port E function selection (Lower) “00” after a reset Port E direction “1” after a reset Internal data bus 1 pin ∗1 ADJ signals are frequency dividing outputs for 32kHz oscillation frequency IP adjustment. ADJ2K provides usage as buzzer output. ∗2 Pull-up transistors approx. 150kΩ RD (Port E) –9– High level H level at ON resistance of pull-up transistor during a reset ( ) CXP7500P10/7500P11 Pin Circuit format After a reset Port E PWM Port E function selection “0” after a reset Port E data PE1/PWM “1” after a reset High level Port E direction “1” after a reset IP Internal data bus RD (Port E) 1 pin Port E TEX oscillation circuit control “1” after a reset Schmitt input INT0 Intrenal data bus RD (Port E) PE2/TEX/INT0 PE3/TX Intrenal data bus RD (Port E) Schmitt input PE2/ TEX/ INT0 2 pins IP Oscillation stop Port input IP Clock input PE3/ TX Port E YM, YS, I Output polarity “0” after a reset PE4/YM PE5/YS PE6/I Port E function selection Hi-Z “1” after a reset Port E data Writing data to output polarity register or port data register brings output to activate. Internal data bus 3 pins RD (Port E) – 10 – CXP7500P10/7500P11 Pin Circuit format Port F After a reset SCL, SDA I2C bus enable ∗ PWM4, PWM5 PF4/SCL0 PF5/SCL1/PWM4 PF6/SDA0 PF7/SDA1/PWM5 Port F function selection “0” after a reset Hi-Z Port F data “1” after a reset Internal data bus RD (Port F) Schmitt input SCL, SDA (I2C bus circuit) IP BUS SW 4 pins To internal I2C pins (SCL1 for SCL0) ∗ Large current 12mA R, G, B R G B Output polarity “0” after a reset Hi-Z Writing data to output polarity register brings output to activate. 3 pins Oscillation control EXLC XLC EXLC 2 pins XLC EXTAL XTAL 2 pins IP IP OSD display clock Oscillation stop • Diagram shows the circuit composition during oscillation. • Feedback resistor is removed and XTAL is driven at "H" level during stop. (This device does not enter the stop mode.) IP EXTAL XTAL Oscillation Pull-up resistor RST 1 pin AA AA Schmitt input – 11 – Low level (during a reset) CXP7500P10/7500P11 Absolute Maximum Ratings Item Supply voltage (Vss = 0V reference) Symbol Ratings Unit VDD –0.3 to +7.0 V Vpp V Remarks Input voltage VIN –0.3 to +13.0 –0.3 to +7.0∗1 Output voltage VOUT –0.3 to +7.0∗1 V Medium drive output voltage VOUTP –0.3 to +15.0 V High level output current IOH –5 mA High level total output current ∑IOH –50 mA IOL 15 mA IOLC 20 mA Low level total output current ∑IOL 130 mA Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C 1000 mW SDIP-64P-01 600 mW QFP-64P-L01 875 mW SDIP-52P-01 V Low level output current Allowable power dissipation PD Incorporated PROM Total of all output pins Pins excluding large current output (value per pin) Large current output pins∗2 (value per pin) Total of all output pins ∗1 VIN and VOUT should not exceed VDD + 0.3V. ∗2 The large current drive transistor is Port C (PC6, PC7), Port D (PD) and Port F (PF). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. – 12 – CXP7500P10/7500P11 Recommended Operating Conditions Item Supply voltage High level input voltage Symbol (Vss = 0V reference) Min. Max. Unit 4.5 5.5 V Guaranteed operation range for 1/2 and 1/4 frequency dividing modes 3.5 5.5 V Guaranteed operation range for 1/16 frequency dividing mode or sleep 2.7 5.5 V — — V Guaranteed operation range for TEX mode Guaranteed data hold range for stop∗5 VIH 0.7VDD VDD V ∗1 VIHS 0.8VDD VDD V ∗2 V VDD Remarks VIL 0 0.3VDD V EXTAL pin∗3, TEX pin∗4 ∗1 VILS 0 0.2VDD V ∗2 VILEX –0.3 0.4 V EXTAL pin∗3, TEX pin∗4 Operating temperature Topr –20 +75 °C VIHEX Low level input voltage ∗1 ∗2 ∗3 ∗4 ∗5 VDD – 0.4 VDD + 0.3 PA0 to PA5, PB3 to PB7, PC0 to PC5, PD2, PE0, PE1, PE3, PG3 to PG6, SCL0, SCL1, SDA0, SDA1 pins VSYNC, HSYNC, INT2, SCK, SI, HS0, HS1, RMC, EC, INT0, INT1, RST, PB0 to PB2 pins Specifies only during external clock input. Specifies only during external event count input. This device does not enter the stop mode. – 13 – CXP7500P10/7500P11 Electrical Characteristics DC characteristics Item High level output voltage Low level output voltage (Ta = –20 to +75°C, Vss = 0V reference) Symbol VOH VOL Pins PA, PB, PC0 to PC5, VDD = 4.5V, IOH = –0.5mA PD, PE0 to PE1, PE4 to PE6, PG, R, VDD = 4.5V, IOH = –1.2mA G, B Input current IIHT IILT Min. Typ. Max. Unit 4.0 V 3.5 V PA to PD, PE0 to PE1, VDD = 4.5V, IOL = 1.8mA PE4 to PE6, PF0 to VDD = 4.5V, IOL = 3.6mA PF3, PG, R, G, B 0.4 V 0.6 V PC6, PC7, PD, PF VDD = 4.5V, IOL = 12.0mA 1.5 V PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) VDD = 4.5V, IOL = 3.0mA 0.4 V VDD = 4.5V, IOL = 4.0mA 0.6 V IIHE IILE Conditions EXTAL TEX VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA VDD = 5.5V, VIH = 5.5V 0.1 10 µA –0.1 –10 µA –1.5 –400 µA ±10 µA VDD = 5.5V, VIL = 0.4V IILR RST∗1 I/O leakage current IIZ PA, PB, PC0 to PC5,PD, VDD = 5.5V, PE, PG, R, G, B, RST∗1 VI = 0, 5.5V Open drain I/O leakage current (in N-ch Tr off state) ILOH I2C bus switch connection impedance (in output Tr off state) RBS PC6, PC7, PF0 to PF3 VDD = 5.5V, VOH = 12.0V 50 µA PF4 to PF7 VDD = 5.5V, VOH = 5.5V 10 µA SCL0: SCL1 SDA0: SDA1 VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V 120 Ω 1/2 frequency dividing mode VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) IDD1 IDD2 Supply current∗2 VDD IDDS1 IDDS2 IDDS3 27 42 mA VDD = 5.5V, 24MHz crystal oscillation 40 63 VDD = 3.3V, 32kHz crystal oscillation (C1 = C2 = 47pF) 40 95 µA 2.2 3.9 mA 17 45 µA — — µA Sleep mode VDD = 5.5V, 24MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.3V, 32kHz crystal oscillation (C1 = C2 = 47pF) Stop mode∗3 VDD = 5.5V, termination of 24MHz and 32kHz oscillation – 14 – — CXP7500P10/7500P11 Item Input capacitance Symbol CIN Pins PA, PB,PC0 to PC5, PD,PE0 to PE3, PF4 to PF7, PG, EXTAL, EXLC, RST Conditions Clock 1MHz 0V other than the measured pins Min. Typ. Max. Unit 10 20 pF ∗1 For RST pin, specifies the input current when pull-up resistance is selected, and specifies the leakage current when non-resistor is selected. ∗2 When all output pins are left open. Specifies only when the OSD oscillation is stopped. ∗3 This device does not enter the stop mode. – 15 – CXP7500P10/7500P11 AC Characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) (1) Clock timing Item Symbol System clock frequency fC Event count input clock rise and fall times tXL, tXH tCR, tCF tEH, tEL tER, tEF System clock frequency fC Event count input clock input pulse width tTL, tTH tTR, tTF System clock input pulse width System clock input rise and fall times Event count input clock pulse width Event count input clock rise and fall times Pins Conditions Min. XTAL EXTAL Fig. 1, Fig.2 8 EXTAL Fig. 1, Fig.2 External clock drive 17 EXTAL Fig. 1, Fig.2 External clock drive EC Fig. 3 EC Fig. 3 TEX TX VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied conditions) TEX Fig. 3 TEX Fig. 3 Typ. Max Unit 24 MHz ns 200 4tsys∗1 ns ns 20 ms kHz 32.768 µs 10 20 ms ∗1 Indicates three values according to the contents of the clock control register (CLC: 000FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”) 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 1. Clock timing AAAA AAAA AAAA AAAAAAAAAAAA Crystal oscillation Ceramic oscillation EXTAL C1 32kHz clock applied condition Crystal oscillation External clock EXTAL XTAL C2 TEX XTAL 74HC04 TX C1 C2 Fig.2. Clock applied conditions 0.8VDD TEX EC 0.2VDD tEH tTH tEF tTF tEL tTL Fig. 3. Event count clock timing – 16 – tER tTR CXP7500P10/7500P11 (2) Serial transfer Item SCK cycle time (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol tKCY Pins Conditions Min. ns 8000/fc ns 400 ns 4000/fc – 50 ns SCK input mode 100 ns SCK output mode 200 ns SCK input mode 200 ns SCK output mode 100 ns Output mode SCK High and Low level width tKH tKL SCK SI input setup time (for SCK ↑) tSIK SI SI hold time (for SCK ↑) tKSI SCK ↓ → SO delay time tKSO SCK input mode SCK output mode SI SO SCK input mode 200 ns SCK output mode 100 ns Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL. tKCY tKL tKH 0.8VDD SCK 0.2VDD tSIK tKSI 0.8VDD SI Unit 1000 Input mode SCK Max. Input data 0.2VDD tKSO 0.8VDD SO Output data 0.2VDD Fig. 4. Serial transfer timing – 17 – CXP7500P10/7500P11 (3) A/D converter Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Max. Unit Resolution 8 Bits Linearity error ±3 LSB Zero transition voltage VZT∗1 Full-scale transition voltage VFT∗2 Conversion time Sampling time tCONV tSAMP Analog input voltage VIAN Pins Conditions Ta = 25°C VDD = 5.0V Vss = 0V Min. Typ. –10 10 70 mV 4910 4970 5030 mV 26/fADC∗3 6/fADC∗3 AN0 to AN5 0 µs µs VDD V Digital conversion value FFh FEh ∗1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. ∗3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (ADC: 000F6h): Linearity error 01h 00h fADC = fc (CKS = “0”), fc/2 (CKS = “1”) VFT VZT Analog input Fig. 5. Definitions for A/D converter terms – 18 – CXP7500P10/7500P11 (4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Conditions Min. Max. Unit External interruption High, Low level width tIH tIL INT0 INT1 INT2 1 µs Reset input Low level width tRSL RST 32/fc µs tIH INT0 INT1 INT2 (falling edge) tIL 0.8VDD 0.2VDD Fig. 6. Interruption input timing tRSL RST 0.2VDD Fig. 7. RST input timing – 19 – CXP7500P10/7500P11 (5) I2C bus timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Conditions Min. Max. Unit 0 100 kHz SCL clock frequency fSLC SCL Bus-free time before starting transfer tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO SDA, SCL 4.7 µs SDA, SCL 4.0 µs SCL 4.7 µs SCL 4.0 µs SDA, SCL µs SDA, SCL 4.7 0∗1 SDA, SCL 250 ns Hold time for starting transfer Clock Low level width Clock High level width Setup time for repeated transfers Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion µs SDA, SCL 1 µs SDA, SCL 300 ns SDA, SCL µs 4.7 ∗1 The data hold time should be 300ns or more because the SCL rise time (300ns Max.) is not included in it. SDA tBUF tR tF tHD; STA SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH St tSU; DAT tSU; STO P Fig. 8. I2C bus transfer timing I2C bus device RS I2C bus device RS RS R S RP RP SDA0 (or SDA1) SCL0 (or SCL1) Fig. 9. I2C bus device recommended circuit • A pull-up resistor (Rp) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). • The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce the spike noise caused by CRT flashover. – 20 – CXP7500P10/7500P11 (6) OSD timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Conditions Min. Max. Unit 40.8 MHz fOSC∗1 EXLC XLC Fig. 11 4 tHWD tVWD HSYNC Fig. 10 30/fc VSYNC Fig. 10 1 HSYNC afterwrite rise and fall times tHCG HSYNC Fig. 10 200 ns VSYNC beforewrite rise and fall times tVCG VSYNC Fig. 10 1.0 µs OSD clock frequency HSYNC pulse width VSYNC pulse width µs H∗2 ∗1 The maximum value of fosc is specified with the following equation. fosc [max] ≤ fc × 1.7 ∗2 H indicates 1HSYNC period. tHWD HSYNC For OSD I/O polarity register (OPOL: 001FEh) bit 7 at “0” tHCG 0.8VDD 0.2VDD tVCG tVWD 0.8VDD VSYNC For OSD I/O polarity register (OPOL: 001FEh) bit 6 at “0” 0.2VDD Fig. 10. OSD timing EXLC XLC R∗3 L C2 C1 Fig. 11. LC oscillation circuit connection ∗3 The series resistor for XLC (R = 1kΩ or less) can reduce the frequency of occurrence of the undesired radiation. – 21 – CXP7500P10/7500P11 Appendix AAAA AAAA AAAA AAAA AAAAA AAAA AAAAA AAAA AAAAA AA A A (i) Main clock EXTAL (ii) Main clock EXTAL XTAL Rd C1 (iii) Sub clock TEX XTAL Rd C2 TX Rd C2 C1 C1 C2 Fig. 12. Recommended oscillation circuit Manufacturer MURATA MFG CO., LTD. fc (MHz) Model C2 (pF) 30 30 CSA10.0MTZ 10.0 CSA12.0MTZ 12.0 CSA16.00MXZ040 16.0 5 5 CSA24.00MXZ040 CST10.0MTW∗ 24.0 OPEN OPEN 30 30 10.0 Rd (Ω) Circuit example Remarks (i) 0 ∗1 CST12.0MTW∗ 12.0 CST16.00MXW0C1∗ 16.0 5 5 8.0 18 18 12.0 12 12 16.0 10 10 8.0 10 10 12.0 5 5 16.0 OPEN OPEN 24.0 3 3 32.768kHz 33 30 120k (iii) 32.768kHz 18 18 330k (iii) RIVER ELETEC HC-49/U03 CORPORATION KINSEKI LTD. C1 (pF) HC-49/U (-S) P3 Seiko VTC-200 Instruments Inc. SP-T (ii) 330 ∗1 (i) 0 ∗1 CL = 12.5pF ∗ Models with an astarisk (∗) have the built-in ground capacitance (C1, C2). ∗1 The series resistor for XTAL (Rd = 500Ω or less) can reduce the effect of the noise caused by the electrostatic discharge. Mask Option Table Item Mask ROM CXP7500P10-1- CXP7500P11-2- 64-pin plastic SDIP/QFP 52-pin plastic SDIP 64-pin plastic SDIP/QFP 52-pin plastic SDIP ROM capacitance 96K/120K byte PROM 120K byte PROM 120K byte Reset pin pull-up resistor Existent/Non-existent Existent Existent Package – 22 – CXP7500P10/7500P11 IDD vs. fc IDD vs. VDD (VDD = 5.0V, Ta = 25°C, Typical) (Ta = 25°C, fc = 16MHz, Typical) 100 40 1/2 dividing mode 1/2 dividing mode 35 1/4 dividing mode 10 30 Sleep mode 1 IDD – Supply current [mA] IDD – Supply current [mA] 1/16 dividing mode 25 1/4 dividing mode 20 15 32kHz operation mode 0.1 10 1/16 dividing mode 5 32kHz sleep mode Sleep mode 0.01 2 3 4 5 6 0 7 0 5 10 VDD – Supply voltage [V] 15 20 25 30 fc – Frequency [MHz] IDD vs. VDD Parameter curve for OSD oscillator L vs. C (Analytically calculated value) (Ta = 25°C, fc = 24MHz, Typical) 100 100 1/2 dividing mode 1/4 dividing mode 10 1/16 dividing mode Sleep mode 1 32kHz operation mode 0.1 L – Inductance [µH] IDD – Supply current [mA] 10 16MHz 20MHz 24MHz 28MHz 32MHz 36MHz 40MHz 1 0.1 32kHz sleep mode 0.01 2 3 4 5 6 7 0.01 0 10 20 30 40 50 60 70 C1, C2 – Capacitance [pF] VDD – Supply voltage [V] Fig. 13. Characteristic curves – 23 – 80 90 100 CXP7500P10/7500P11 Unit: mm + 0.1 0.05 0.25 – 64PIN SDIP (PLASTIC) + 0.4 57.6 – 0.1 64 19.05 + 0.3 17.1 – 0.1 33 1 0° to 15° 32 3.0 MIN 0.5 MIN + 0.4 4.75 – 0.1 1.778 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SDIP-64P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SDIP064-P-0750 LEAD MATERIAL 42 ALLOY PACKAGE MASS 8.6g JEDEC CODE 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 0.15 33 64 20 1 16.3 32 + 0.4 14.0 – 0.1 52 + 0.2 0.1 – 0.05 19 + 0.35 2.75 – 0.15 + 0.15 0.4 – 0.1 1.0 0.2 M 0° to10° 0.8 ± 0.2 51 17.9 ± 0.4 Package Outline PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING SONY CODE QFP-64P-L01 LEAD TREATMENT EIAJ CODE QFP064-P-1420 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.5g JEDEC CODE – 24 – CXP7500P10/7500P11 + 0.1 .05 0.25 – 0 52PIN SDIP (PLASTIC) + 0.4 47.0 – 0.1 15.24 + 0.3 13.5 – 0.1 27 52 0° to 15° 26 1 5.0 MIN 2.8 MIN 0.51 MIN 1.778 0.5 ± 0.1 + 0.1 0.9 – 0.05 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SDIP-52P-01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE SDIP052-P-0600 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 5.6g JEDEC CODE – 25 –