CXP851P16 CMOS 8-bit Single Chip Microcomputer Description The CXP851P16 are highly integrated microcomputers composed of a 8-bit CPU, PROM, RAM, and I/O ports. These chips feature many other highperformance circuits in a single-chip CMOS design, including an A/D converter, serial interface, timer/counter, time-base timer, vector interrupt, onscreen display function, I2C bus interface, PWM generator, remote control receiver, HSYNC counter, power supply frequency counter, and watchdog timer. Also this IC provides power-on reset and sleep functions. The designers have ensured low power consumption for these powerful microcomputers. The CXP851P16 is the on-chip PROM version of the CXP85116 with on-chip mask ROM, providing the function of being able to write directly into the program. Furthermore, because of the OSD character ROM can also be written directly into, it is suitable for evaluation use during system development and for small quantity production. 64 pin SDIP (Plastic) 64 pin QFP (Plastic) Structure Silicon gate CMOS IC Features • A wide instruction set (213 instructions) which cover various types of data. — 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction • Minimum instruction cycle During operation 1µs/4MHz • Incorporated PROM capacity 16K bytes (For program) 3K bytes (For OSD) • Incorporated RAM capacity 352 bytes • Peripheral functions — On-screen display function 12 × 16 dots, 128 types 4 lines of 21 characters (5 or more lines possible) double scanning mode supported includes jitter elimination circuit — I2C bus interface — PWM output 14-bits, 1 channel 6-bits, 8 channels — Remote control receiving circuit 8-bit pulse measuring counter, 6-stage FIFO — A/D converter 4-bit, 4-channel, successive approximation method (conversion time of 40µs/4MHz) — HSYNC counter — Power supply frequency counter — Watchdog timer — 8-bit synchronized serial I/O — 8-bit timer, 8-bit timer/counter, 19-bit time-base timer • Interruption 14 factors, 14 vectors, multiple interrupt possible • Standby mode SLEEP/STOP • Package 64-pin plastic SDIP/QFP Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94332A18-PS HSYNC COUNTER AC TIMER A/D CONVERTER I2C INTERFACE UNIT PD4/HSI PD5/ACI PE2/AN0 to PE5/AN3 PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 REMOCON TIMER/COUNTER PD7/EC PE7/TO PD6/RMC SERIAL I/O PD3/SI PD2/SO PD1/SCK FIFO ON SCREEN DISPLAY PROM 3K BITES 2 2 PE0/INT0 6 BIT PWM 8CH PROM 16K BYTES SPC700 CPU CORE 14BIT PWM WATCH DOG TIMER PD0/INT2 PE6/PWM EXLC XLC B G R BLK HSYNC VSYNC PE1/INT1 INTERRUPT CONTROLLER PF0/PWM0 to PF7/PWM7 Vpp VSS MP VDD RST XTAL EXTAL PRESCALER/ TIME BASE TIMER RAM 352 BYTES CLOCK GEN./ SYSTEM CONTROL PF0 to PF7 PE6 to PE7 PE0 to PE5 PD0 to PD7 PC0 to PC7 PA0 to PA7 PB0 to PB7 PORT A PORT B PORT C PORT D PORT E –2– PORT F Block Diagram CXP851P16 CXP851P16 55 PF2/PWM2 56 PF0/PWM0 57 PF1/PWM1 58 Vpp 59 MP VDD 60 PA7 61 VSS 62 PA5 63 PA6 PA3 64 PA4 PA2 Pin Configuration (Top View) 54 53 52 PA7 1 64 VDD PA6 2 63 Vpp PA5 3 62 VSS PA4 4 61 MP PA3 5 60 PF0/PWM0 PA2 6 59 PF1/PWM1 PA1 7 58 PF2/PWM2 PA0 8 57 PF3/PWM3 PB7 9 56 PF4/PWM4/SCL0 PB6 10 55 PF5/PWM5/SCL1 PB5 11 54 PF6/PWM6/SDA0 PB4 12 53 PF7/PWM7/SDA1 PB3 13 52 BLK PB2 14 51 R PB1 15 50 G PB0 16 49 B PC7 17 48 VSYNC PC6 18 47 HSYNC PC5 19 46 EXLC PC4 20 45 XLC PC3 21 44 PE0/INT0 PC2 22 43 PE1/INT1 PC1 23 42 PE2/AN0 PC0 24 41 PE3/AN1 EC/PD7 25 40 PE4/AN2 RMC/PD6 26 39 PE5/AN3 ACI/PD5 27 38 PE6/PWM HSI/PD4 28 37 PE7/TO SI/PD3 29 36 RST SO/PD2 30 35 EXTAL SCK/PD1 31 34 XTAL VSS 32 33 PD0/INT2 Note) 1. Vpp (Pin 63) is always connected to VDD. 2. Vss (Pins 32 and 62) are both connected to GND. 3. MP (Pin 61) is always connected to GND. PA1 1 51 PA0 2 50 PF4/PWM4/SCL0 PB7 3 49 PF5/PWM5/SCL1 PB6 4 48 PF6/PWM6/SDA0 PB5 5 47 PF7/PWM7/SDA1 PB4 6 46 BLK 45 R 44 G PF3/PWM3 12 40 EXLC PC5 13 39 XLC PC4 14 38 PE0/INT0 PC3 15 37 PE1/INT1 PC2 16 36 PE2/AN0 PC1 17 35 PE3/AN1 PC0 18 34 PE4/AN2 EC/PD7 19 33 PE5/AN3 20 21 22 23 24 25 26 27 28 29 30 31 32 PWM/PE6 HSYNC PC6 RST 41 TO/PE7 11 EXTAL VSYNC PC7 XTAL 42 INT2/PD0 10 VSS B PB0 SCK/PD1 43 SI/PD3 9 SO/PD2 PB1 HSI/PD4 8 ACI/PD5 7 PB2 RMC/PD6 PB3 Note) 1. Vpp (Pin 56) is always connected to VDD. 2. Vss (Pins 26 and 58) are both connected to GND. 3. MP (Pin 55) is always connected to GND. –3– CXP851P16 Pin Description Symbol I/O Description PA0 to PA7 I/O (Port A) Single bit selectable 8-bit port. (8 lines) PB0 to PB7 I/O (Port B) Single bit selectable 8-bit port. (8 lines) PC0 to PC7 I/O (Port C) Single bit selectable 8-bit port. (8 lines) PD0/INT2 I/O/Input PD1/SCK I/O/I/O PD2/SO I/O/Output PD3/SI I/O/Input PD4/HSI I/O/Input PD5/ACI I/O/Input PD6/RMC I/O/Input Remote control receiver circuit input pin. PD7/EC I/O/Input External event timer/counter input pin. PE0/INT0 PE1/INT1 Input/Input Input pin for external interrupt request. Active on falling edge. (2 lines) Input pin for external interrupt request. Active on falling edge. Serial clock pin. (Port D) Single bit selectable Serial data output pin. 8-bit port. Serial data input pin. 12mA sink current HSYNC counter input pin. drive possible. (8 lines) Power supply frequency counter input pin. (Port E) 8-bit port, lower 6 bits for input, upper 2 bits for output. (8 lines) PE2/AN0 to PE5/AN3 Input/Input PE6/PWM Output/Output PE7/TO Output/Output PF0/PWM0 to PF3/PWM3 Output/Output PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 Output/Output/ I/O PF6/PWM6/ SDA0 PF7/PWM7/ SDA1 Output/Output/ I/O R, G, B, BLK Output CRT display 4-bit output pin. HSYNC Input CRT display horizontal synchronization signal input pin. VSYNC Input CRT display vertical synchronization signal input pin. Analog input pin for A/D converter. (4 lines) 14-bit PWM output pin. (CMOS output) Square wave output for timer 1. (50% duty cycle) (Port F) 8-bit output port with large current (12mA) N-ch open drain output. Lower 4 bits middle voltage tolerance (12V), upper 4 bits 5V suppression. (8 lines) –4– 6-bit PWM output pin. (8 lines) I2C bus interface transfer clock input/output pin. I2C bus interface transfer data input/output pin. CXP851P16 Symbol I/O Description EXLC Input XLC Output EXTAL Input XTAL Output RST I/O "L" level active system reset. This pin also acts as an input/output pin during power up. While internal power-on reset function is taking place a "L" level is output. (Mask option) MP Input Microprocessor mode input pin. Must be connected to GND. CRT display clock oscillator input/output pin. Oscillator frequency is determined by external L, C circuit. System clock oscillator crystal connection pin. When using an external clock, input to EXTAL pin and leave XTAL pin open. VDD Positive power supply pin. Vpp Positive power supply pin for on-chip PROM writing. Please connect to VDD for normal operation. Vss GND. Both Vss pins should be connected to common GND. –5– CXP851P16 Input/Output Circuit Formats for Pins Pin Circuit format Port A Port B Port C PA0 to PA7 PB0 to PB7 PC0 to PC7 When reset AAAA AAAA AAAA AAAA AA AA AA AA Port A data Port B data Port C data Port A direction Port B direction Port C direction Data bus IP RD (Port A, B, C) 24 pins Hi-Z Input protection circuit Port D PD0/INT2 PD3/SI PD4/HSI PD5/ACI Port D data Port D direction PD6/RMC PD7/EC AAAA AAAA AAAA Data bus AA A A High current 12mA Hi-Z IP RD (Port D) INT2, SI, HSI, ACI, RMC, EC Schmitt input 6 pins Port D AA AA AA SCK or SO Output enable PD1/SCK PD2/SO AAAAA AAAAA AAAAA High current 12mA Port D data IP Port D direction Data bus RD (Port D) SCK only 2 pins –6– Schmitt input Hi-Z CXP851P16 Pin Port E PE0/INT0 PE1/INT1 AAAA Circuit format When reset Schmitt input (To interrupt circuit) IP Hi-Z Data bus 2 pins RD (Port E) Port E PE2/AN0 to PE5/AN3 AA A AAA Input multiplexer IP To A/D converter Hi-Z Data bus 4 pins RD (Port E) Port E AAAA AAAA AAAA AA AA TO, PWM PE6/PWM PE7/TO Port E data Port selection 2 pins H level Port F PWM PF0/PWM0 to PF3/PWM3 AAAAA AAAAA AAAAA AA AA AA AA Middle tension proof 12V Port F data High current 12mA Port selection 4 pins Port F SCL, SDA PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 PF6/PWM6/ SDA0 PF7/PWM7/ SDA1 I2C output enable AAAA AAAA AAAA Hi-Z AA AA PWM Port F data Hi-Z IP Port selection Schmitt input SCL, SDA (To I2C circuit) BUS SW To other I2C pins 4 pins –7– CXP851P16 Pin BLK R G B 4 pins Circuit format AAAA AAAA When reset AA BLK, R, G, B Output polarity Hi-Z To output polarity register Writing data to port register brings output from high impedance to active AAA AAAAA AAA AA AA AA AA AA A AA A Schmitt input HSYNC VSYNC 2 pins IP XLC 2 pins EXTAL XTAL 2 pins RST 1 pin MP 1 pin Hi-Z Input polarity EXLC EXLC XLC HSYNC VSYNC IP Oscillator control Oscillation halted CRT display clock IP AA AA AA AA A A EXTAL • Diagram indicates equivalent circuit during oscillation IP • Feedback resistor is disconnected during STOP Oscillation XTAL AA AA AAAA Mask option Pull-up resistor Schmitt input OP L level From power-on reset circuit (Mask option) IP CPU mode –8– HI-Z CXP851P16 Absolute Maximum Ratings (Vss = 0V) Item Symbol Supply voltage Ratings Unit VDD –0.3 to +7.0 V Vpp V Remarks Input voltage VIN –0.3 to +13.0 –0.3 to +7.0∗1 Output voltage VOUT –0.3 to +7.0∗1 V Medium voltage tolerance output voltage VOUTP –0.3 to +15.0 V High level output current IOH –5 mA High level total output current ∑IOH –50 mA Total of all output pins IOL 15 mA IOLC 20 mA Excludes large current output Large current output∗2 Low level total output current ∑IOL 130 mA Total of all output pins Operating temperature Topr –10 to +75 °C Strage temperature Tstg –55 to +150 °C PD 1000 mW SDIP Allowable power dissipation 600 mW QFP Low level output current Incorporated PROM V Pins PF0 to PF3 ∗1) VIN and VOUT should not exceed VDD + 0.3V. ∗2) The high current operation transistors are the N-ch transistors of the PD and PF0 to PF3 ports. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operation Conditions Item Supply voltage Symbol VDD Min. Max. Unit 4.5 5.5 V Guaranteed range during operation 3.5 5.5 V Guaranteed range for low speed data ∗1 2.5 5.5 V Guaranteed data hold operation range during stop V ∗5 I2C Schmitt input included ∗2 Vpp High level input voltage Vpp = VDD Remarks VIH 0.7VDD VDD V VIHS 0.8VDD VDD V VIHEX VDD – 0.4 VDD + 0.3 V 0 0.3VDD V 0 0.2VDD V I2C Schmitt input included ∗2 CMOS Schmitt input ∗3 VILEX –0.3 0.4 V EXTAL pin ∗4 Topr –10 +75 °C VIL Low level input voltage VILS Operating temperature (Vss = 0V) CMOS Schmitt input ∗3 EXTAL pin ∗4 ∗1) Rating for 1/16 frequency mode and sleep mode. ∗2) Normal input port (All pins of PA, PB, PC, PE2 to PE5), PF4 tp PF7, and MP pins. ∗3) Includes PD0/INT2, PD1/SCK, PD2, PD3/SI, PD4/HSI, PD5/ACI, PD6/RMC, PD7/EC, PE0/INT0, PE1/INT1, HSYNC, VSYNC, RST pins. ∗4) It specifies only when the external clock is input. ∗5) Vpp and VDD should be set to a same voltage. –9– CXP851P16 DC Characteristics Item High level output voltage Low level output voltage (Ta = –10 to +75°C, Vss = 0V) Symbol VOH VOL IIHE Input current Pin Condition PA to PD, PE6, PE7, VDD = 4.5V, IOH = –0.5mA R, G, B, BLK VDD = 4.5V, IOH = –1.2mA Min. Typ. Max. Unit 4.0 V 3.5 V PA to PD, PE6, PE7, VDD = 4.5V, IOL = 1.8mA R, G, B, BLK, VDD = 4.5V, IOL = 3.6mA PF0 to PF3, RST 0.4 V 0.6 V PD, PF0 to PF3 VDD = 4.5V, IOL = 12.0mA 1.5 V PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) VDD = 4.5V, IOL = 3.0mA 0.4 V VDD = 4.5V, IOL = 4.0mA 0.6 V EXTAL IIHL VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA –1.5 –400 µA IILR RST VDD = 5.5V, VIL = 0.4V Input/output leak current IIZ PA to PE, HSYNC, VSYNC, R, G, B, BLK, MP VDD = 5.5V VI = 0, 5.5V ±10 µA Open drain output leak current (N-ch Tr off case) PF0 to PF3 VDD = 5.5V, VOH = 12.0V 50 µA ILOH PF4 to PF7 VDD = 5.5V, VOH = 5.5V 10 µA SCL0: SCL1 SDA0: SDA1 VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V 120 Ω I2C bus switch connection impedance RBS (output Tr off case) Operating mode∗ (1/2 clock rate) 4MHz crystal oscillator (C1 = C2 = 22pF) All output pins open 10 25 mA IDDSL SLEEP mode 0.7 3 mA IDDST STOP mode 30 µA 20 pF IDD VDD∗ Supply current Input capacitance CIN Pins other than VDD and Vss 1MHz clock 0V other than the measure pins ∗ Rating applies only if OSD oscillator is haited. – 10 – 10 CXP851P16 AC Characteristics (1) Clock timing (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Symbol Pin Condition Min. Max. Unit 4.5 MHz System clock frequency fC XTAL EXTAL Fig. 1, Fig. 2 3.5 System clock input pulse width tXL, tXH EXTAL Fig. 1, Fig. 2 External clock drive 100 System clock rise and fall times tCR, tCF tEH, tEL tER, tEF EXTAL Fig. 1, Fig. 2 External clock drive EC Fig. 3 EC Fig. 3 Event counter input clock pulse width Event counter input clock rise and fall times ns 200 tsys + 50∗ ns ns 20 ms ∗ tsys indicates three values according to the contents of the clock control register (address: 00FEH) upper 2 bits (CPU clock selection). tsys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig, 2. Clock applied condition AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA Crystal oscillator Ceramic oscillator EXTAL External clock EXTAL XTAL C2 C1 XTAL OPEN Fig. 3. Event count clock timing 0.8VDD EC 0.2VDD tEH tEF – 11 – tEL tER CXP851P16 (2) Serial transfer Item (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pin tKCY SCK SCK high and low level widths tKH tKL SCK SI input set up time (against SCK ↑) tSIK SI SI input hold time (against SCK ↑) tKSI SI SCK ↓ → SO delay time tKSO SO SCK cycle time Condition Min. Max. 1000 ns 8000/fc ns 400 ns 4000/fc – 50 ns SCK input mode 100 ns SCK output mode 200 ns SCK input mode 200 ns SCK output mode 100 ns Input mode Output mode SCK input mode SCK output mode SCK input mode 200 ns SCK output mode 100 ns Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL. Fig. 4. Serial transfer timing tKCY tKL tKH 0.8VDD SCK 0.2VDD tSIK tKSI 0.8VDD Input data SI Unit 0.2VDD tKSO 0.8VDD SO Output data 0.2VDD – 12 – CXP851P16 (3) Interrupt, Reset input (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Symbol tIH tIL tRSL External interrupt high and low level widths Reset input low level width Pin Condition Min. INT0 to INT2 RST Max. Unit 1 µs 8/fc µs Fig. 5. Interrupt input timing tIH tIL 0.8VDD INT0 to INT2 (falling edge) 0.2VDD Fig. 6. RST input timing tRSL RST 0.2VDD (4) Power-on reset Power-on reset∗ (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Symbol tR Power supply cut-off time tOFF Power supply rise time Pin VDD Condition Power-on reset Min. Max. Unit 0.05 50 ms 1 Repetitive power-on ms ∗ Specifies only when power-on reset function is selected. Fig. 7. Power-on reset VDD 4.5V 0.2V 0.2V tR tOFF The power supply should rise smoothly. – 13 – CXP851P16 (5) A/D converter characteristics Item Symbol (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Max. Unit Resolution 4 Bits Linearity error ±1 LSB Zero transition voltage VZT∗1 Full-scale transition voltage VFT∗2 Conversion time Sampling time tCONV tSAMP Analog Input voltage VIAN Pin Condition Ta = 25°C VDD = 5.0V Vss = 0V AN0 to AN3 Min. Typ. –10 160 320 mV 4370 4530 4690 mV 160/fc µs 12/fc µs 0 VDD V Fig. 8. Definitions for A/D converter terms Digital conversion value FH EH ∗1) VZT: Indicates the value that digital conversion value changes from 00H to 01H and vice versa. ∗2) VFT: Indicates the value that digital conversion value changes from EH to FH and vice versa. Linearity error 1H 0H VZT VFT Analog input Note) For 4-bit conversion, correction of the upper 5 bits A/D data register (ADD: address 00F5H) into 4 bit data is defined according to the following program example. (A/D converter program example) MOV A, ADD LSR A LSR A LSR A LSR A ADC A, #00H CMP A, #10H BNE ADC_SKIP MOV A, #0FH ADC_SKIP: ; ACC ← conversion data ; logical shift right (4 times) ; ; ; ; carry addition (if AD3 is 1, data is incremented) ; ; ; – 14 – CXP851P16 (6) I2C bus timing (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Symbol Pin Condition Min. Max. Unit 0 100 kHz SCL clock frequency fSLC SCL Bus free time before starting transfer tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO SDA, SCL 4.7 µs SDA, SCL 4.0 µs SCL 4.7 µs SCL 4.0 µs SDA, SCL µs SDA, SCL 4.7 0∗ SDA, SCL 250 ns Hold time for starting transfer Clock low level width Clock high level width Set-up time for repetitive transfers Data hold time Data set-up time SDA, SCL rise time SDA, SCL fall time Set-up time for transfer completion µs SDA, SCL 1 µs SDA, SCL 300 ns SDA, SCL 4.7 µs ∗ Since SCL rise time (max: 300ns) is not considered part of data hold time, allow at least 300ns. Fig. 9. I2C Bus transfer data timing SDA tBUF tR tF tHD; STA SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH St tSU; DAT tSU; STO P Fig. 10. I2C device recommended circuit I2C device RS I2C device RS RS R S RP RP SDA0 (or SDA1) SCL0 (or SCL1) • A pull-up resistor must be connected to SDA0 (or SDA1), and SCL0 (or SCL1). • The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (RS = 300Ω or less) can be used to reduce spike noise caused by CRT flashover. – 15 – CXP851P16 (7) OSD (On Screen Display) timing Item (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pin Condition Min. Max. Unit 13 MHz OSD clock frequency fOSC EXLC XLC Fig. 12 4 HSYNC pulse width tHWD HSYNC Fig. 11 1.2 HSYNC afterwrite rise and fall times tHCG HSYNC Fig. 11 200 ns VSYNC afterwrite rise and fall times tVCG VSYNC Fig. 11 1.0 µs Fig. 11. OSD timing tHCG tHWD 0.8VDD HSYNC For OPOL register (01FBH) bit 5 at "0" 0.2VDD tVCG 0.8VDD VSYNC For OPOL register (01FBH) bit 4 at "0" 0.2VDD Fig. 12. LC oscillator circuit connection EXLC XLC L C1 C2 – 16 – µs CXP851P16 Supplement Fig. 13. Recommended Oscillation Circuit AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA (i) EXTAL (ii) EXTAL XTAL Rd C1 XTAL Rd C2 C1 C2 Manufacturer MURATA MFG CO., LTD. RIVER ELETEC CO., LTD. KINSEKI LTD. Model fc (MHz) CSA4.00MG 4.00 CSA4.19MG 4.19 CST4.00MGW∗ CST4.19MGW∗ C1 (pF) 30 4.00 Circuit Example 30 0 (ii) 4.19 15 15 4.00 22 22 4.19 18 18 4.19 HC49/U (-S) Rd (Ω) (i) 4.00 HC-49/U03 C2 (pF) 0 (i) 0 ∗ Indicates types with on-chip grounding capacitors (C1 and C2). Selection Guide Option item Mask version CXP851P16AS-1- CXP851P16AQ-1- 64-pin plastic SDIP/QFP 64-pin plastic SDIP 64-pin plastic QFP 12K/16K bytes PROM 16K bytes PROM 16K bytes Reset pin pull-up resistor Existent/non-existent Existent Existent Power-on reset circuit Existent/non-existent Existent Package PROM capacitance Font data User specified Existent ∗ User specified (PROM) User specified (PROM)∗ ∗ The font data for the one-time PROM version is operated in the same way as the program writing. – 17 – CXP851P16 Fig. 14. Characteristic curves IDD vs. VDD (fc = 4MHz, Ta = 25°C, Typical) IDD vs. fc (VDD = 5V, Ta = 25°C, Typical) 14 15 1 2 frequency mode 10 1 2 frequency mode 13 12 11 1 frequency mode 16 1 IDD – Supply current (mA) IDD – Supply current (mA) 1 frequency mode 4 SLEEP mode 10 1 4 frequency mode 9 8 7 1 frequency mode 16 6 5 4 0.1 3 2 2 3 4 5 6 1 VDD – Supply voltage (V) 0 SLEEP mode 1 2 3 4 5 fc – System clock (MHz) Parameter Curve for OSD Oscillator L vs. C (Analytically calculated value) 100 L – Inductance (µH) 5.0MHz 6.5MHz 10 13.0MHz 1 fOSC = 2π √ LC C = C1//C2 1 0 50 C1, C2 – Capacitance (pF) 100 – 18 – 6 CXP851P16 Unit: mm + 0.1 0.05 0.25 – 64PIN SDIP (PLASTIC) + 0.4 57.6 – 0.1 33 19.05 + 0.3 17.1 – 0.1 64 1 0˚ to 15˚ 32 3.0 MIN 0.5 MIN + 0.3 4.75 – 0.1 1.778 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SDIP-64P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE P-SDIP64-17.1x57.6-1.778 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 8.6g JEDEC CODE + 0.1 0.05 0.25 – 64PIN SDIP (PLASTIC) + 0.4 57.6 – 0.1 33 19.05 + 0.3 17.1 – 0.1 64 1 0˚ to 15˚ 32 0.5 ± 0.1 + 0.3 4.75 – 0.1 0.5 MIN 1.778 3.0 MIN Package Outline 0.9 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SDIP-64P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE P-SDIP64-17.1x57.6-1.778 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 8.6g JEDEC CODE LEAD SPECIFICATIONS ITEM SPEC. LEAD MATERIAL ALLOY 42 LEAD TREATMENT Sn-Bi 2.5% LEAD TREATMENT THICKNESS 5-18µm – 19 – CXP851P16 Unit: mm 64PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 51 0.15 64 20 1 16.3 32 + 0.4 14.0 – 0.1 52 17.9± 0.4 33 + 0.2 0.1 – 0.05 0.8 ± 0.2 19 + 0.35 2.75 – 0.15 + 0.15 0.4 – 0.1 1.0 0.2 M 0 ˚ to10 ˚ PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE QFP-64P-L01 LEAD TREATMENT EIAJ CODE P-QFP64-14x20-1.0 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.5g JEDEC CODE 64PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 51 0.15 64 20 1 16.3 32 + 0.2 0.1 – 0.05 19 + 0.35 2.75 – 0.15 + 0.15 0.4 – 0.1 1.0 0.2 M 0 ˚ to10 ˚ 0.8 ± 0.2 52 17.9± 0.4 33 + 0.4 14.0 – 0.1 Package Outline PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE QFP-64P-L01 LEAD TREATMENT EIAJ CODE P-QFP64-14x20-1.0 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.5g JEDEC CODE LEAD SPECIFICATIONS ITEM SPEC. LEAD MATERIAL ALLOY 42 LEAD TREATMENT Sn-Bi 2.5% LEAD TREATMENT THICKNESS 5-18µm – 20 – Sony Corporation