ILX514 3918-pixel CCD Linear Image Sensor (B/W) For the availability of this product, please contact the sales office. Description The ILX514 is a reduction type CCD linear sensor developed for high resolution facsimiles and copiers. This sensor reads A4-size documents at a density of 400 DPI (Dot Per Inch). A built-in timing generator and clock-drivers ensure direct drive at 5V logic for easy use. In addition, reset pulse can be switched between internal generation and external input. 22 pin DIP (Cer-DIP) Features • Number of effective pixels: 3918 pixels • Pixel size: 7µm × 7µm (7µm pitch) • Built-in timing generator and clock-drivers • Ultra low lag/ultra high sensitivity/low dark output • Single output method • Maximum clock frequency: 5MHz Absolute Maximum Ratings • Supply voltage VDD1 VDD2 • Operating temperature • Storage temperature 11 6 –10 to +60 –30 to +80 V V °C °C Pin Configuration (Top View) 22 φCLK NC 1 GND 2 21 VDD1 VDD1 3 20 RS/SH VOUT 4 19 VDD1 GND 5 18 VDD1 φROG 6 17 GND NC 7 16 NC VDD2 8 15 GND RSSW 9 14 GND 13 NC 12 NC 1 NC 10 NC 11 3918 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93302C78-PS Read out gate Read out gate 6 11 10 20 9 22 8 7 5 3 2 Read out gate pulse generator GND Mode selector VDD1 Clock-drivers CCD analog shift register 12 13 GND Clock pulse generator Sample-and-hold pulse generator VDD1 NC 1 VDD1 VDD2 NC VDD1 φCLK AAAA AA D17 RSSW 4 D18 RS/SH VOUT . CCD analog shift register Clock-drivers 14 GND 15 NC NC • Output amplifier • Sample-and-hold circuit • Feed through suppression circuit 16 GND 17 S1 NC D98 GND S2 18 S3917 19 D99 NC S3918 21 D116 NC –2– φROG Block Diagram ILX514 ILX514 Pin Description Pin No. Symbol Description 1 NC NC 2 GND GND 3 VDD1 9V power supply 4 VOUT Signal output 5 GND GND 6 φROG Clock pulse 7 NC NC 8 VDD2 9 5V power supply ∗ 1 RSSW Reset pulse swithover pin 10 NC NC 11 NC NC 12 NC NC 13 NC NC 14 GND GND 15 GND GND 16 NC NC 17 GND GND 18 VDD1 9V power supply 19 VDD1 9V power supply 20 RS/SH∗1 Clock pulse or with S/H; without S/H switch 21 VDD1 9V power supply 22 φCLK Clock pulse ∗1 Output mode is changeable as follows. 20pin GND VDD1 φRS GND Internal RS without S/H Internal RS with S/H — VDD1 — — External RS without S/H 9pin –3– ILX514 Recommended Voltage Item Min. Typ. Max. Unit VDD1 8.5 9.0 9.5 V VDD2 4.75 5.0 5.25 V Note) Rules for raising and lowering power supply voltage To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V). To lower voltage, first lower VDD2 (5V) and then VDD1 (9V). Clock Characteristics Item Symbol Min. Typ. Max. Unit Input capacity of φCLK pin CφCLK — 10 — pF Input capacity of φROG pin CφROG — 10 — pF Input capacity of RS/SH pin CRS/SH — 10 — pF Frequency of φCLK fφCLK — 1 5 MHz Frequency of φRS fφRS — 1 5 MHz –4– ILX514 Electro-optical Characteristics (Note 1) (Ta = 25°C, VDD1 = 9V, VDD2 = 5V, φCLK = 1MHz, Internal φRS mode without S/H, Light source = 3200K, IR cut filter, CM-500S (t = 1.0mm)) Item Symbol Min. Typ. Max. Unit Remarks Sensitivity 1 R1 7.5 10.8 13.9 V/(lx · s) Note 2 Sensitivity 2 R2 — 24.6 — V/(lx · s) Note 3 Sensitivity nonuniformity PRNU — 4 10 % Note 4 Saturation output voltage VSAT 1.0 1.5 — V Note 5 Saturation exposure SE 0.072 0.139 — lx · s Note 6 Even and odd black level DC difference ∆V — 1.0 10 mV Note 7 Dark voltage average VDRK — 0.3 2 mV Note 8 Dark signal nonuniformity DSNU — 0.6 3 mV Note 9 Image lag IL — 0.02 — % Note 10 9V supply current IVDD1 — 16 32 mA — 5V supply current IVDD2 — 2.1 5.0 mA — Total transfer efficiency TTE 92 98 — % — Output impedance ZO — 600 — Ω — Offset level VOS — 3.0 — V Note 11 Dynamic range DR 500 5000 — — Note 12 Notes) 1) In accordance with the given electrooptical characteristics, the even black level is defined as the mean value of D8, D10, D12 and D14. The odd black level is defined as the mean value of D7 , D9, D11 and D13. 2) For the sensitivity test light is applied with a uniform intensity of illumination. 3) W lamp (2854K) 4) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. PRNU = (VMAX – VMIN)/2 × 100 [%] VAVE Where the 3918 pixels are divided into blocks of 98, even and odd pixels, respectively (Even and odd last blocks are 97). The maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE. 5) Use below the minimum value of the saturation output voltage. 6) Saturation exposure is defined as follows. SE = VSAT R1 7) Indicates the DC difference in value between odd black level and even black level. 8) Optical signal accumulated time τ int stands at 10ms. –5– ILX514 9) The difference between the maximum and mean values of the dark output voltage is calculated for even and odd respectively. The larger value is defined as the dark signal nonuniformity. Optical signal accumulated time τ int stands at 10ms. 10) VOUT = 500mV (Typ.) 11) Vos is defined as indicated below. Vout VOS GND 12) Dynamic range is defined as follows. DR = VSAT VDRK When optical accumulated time is shorter, the dynamic range gets wider because dark voltage is in proportion to optical accumulated time. –6– 0.01µ 5V 9V φCLK Application Circuit∗ 10µ/16V –7– 1kΩ (A) VDD1 3 (A) VOUT 4 VDD1 (A) 19 (A) GND 5 VDD1 (A) 18 6 φROG GND (D) 17 φROG NC 7 NC 16 (D) VDD2 8 GND (D) 15 (D) RSSW 9 GND 14 NC 10 NC 13 NC 11 NC 12 0.01µ 10µ/10V noise influence into output signal is large, connect pins indicated by (A) to the analog power supply and ( When ) pins indicated by (D) to the digital power supply, and also use a decoupling capacitor of large capacitance. ∗ This application circuit shows when φRS is used externally. 2SA1175 RS/SH (D) 20 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Output signal (A) GND 2 VDD1 (D) φCLK NC 1 21 22 φRS ILX514 –8– VOUT φRS φCLK 0 5 0 5 0 1 D1 φROG 2 3 4 Optical black (80 pixels) D16 D17 D18 D19 D20 2 1 ∗ This clock timing diagram shows when φRS is used externally. Dummy signal (18 pixels) S3915 S3916 S3917 S3918 D99 D100 D106 D107 D108 D109 Effective picture elements signal (3918 pixels) AAAAA AA AAAAAA AAAA AAA D96 D97 D98 S1 S2 S3 S4 1-line output period (4034 pixels) Dummy signal (98 pixels) D2 D3 D4 D5 D6 5 4034 D116 Clock Timing Diagram∗ ILX514 ILX514 Clock Pulse Waveform Conditions φCLK, φROG pulse related t8 t9 t2 φROG t1 φCLK t3 Internal φRS mode t8 t9 t4 φCLK Vout t5 AAAA AAAA t10 t11 AAA AAA t10 External φRS mode φCLK t4 t5 t9 φRS t7 t8 t6 AAAA AAA AAAA AAA t13 t12 –9– t10 ILX514 Item Symbol Min. Typ. Max. Unit φROG, φCLK pulse timing t1 100 200 — ns φROG, φCLK pulse timing t3 800 1000 — ns φROG pulse high level period t2 800 — ns φCLK pulse high level period t4 100 1000 500∗1 — ns 500∗1 — ns φCLK pulse low level period t5 100 φRS pulse low level period t6 40 φCLK, φRS pulse timing t7 Input clock pulse rise/fall time Input clock pulse voltage — ns 100 100∗1 550∗1 t1 + t2 ns t8, t9 — 5 10 ns High level VφCLK, VφROG 4.5 5.0 5.5 V Low level VφRS 0 — 0.5 V t10 — 110 — ns t11 — 65 — ns t12 — 40 — ns t13 — 75 — ns Internal φRS Signal output delay time External φRS ∗1 Recommended condition during φCLK = 1MHz. – 10 – ILX514 Example of Representative Characteristics (VDD1 = 9V, VDD2 = 5V, Ta = 25°C) Spectral sensitivity characteristics (Standard characteristics) 1.0 Relative sensitivity 0.8 0.6 0.4 0.2 0 400 500 600 700 800 Wavelength [nm] 900 1000 MTF of main scanning direction (Standard characteristics) 0 Spatial frequency [cycles/mm] 14.3 28.6 42.9 57.1 71.4 1.0 0.8 MTF 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 Normalized spatial frequency Dark signal output temperature characteristics (Standard characteristics) 1.0 Integration time output voltage characteristics (Standard characteristics) 10 Output voltage rate Output voltage rate 5 1 0.5 0.1 1 0.5 0.1 0 10 20 30 40 50 Ta – Ambient temperature [°C] 1 60 – 11 – 5 τ int – Integration time [ms] 10 ILX514 Operational frequency characteristics of the VDD2 supply current (Standard characteristics) IVDD2 – VDD2 supply current [mA] IVDD1 – VDD1 supply current [mA] Operational frequency characteristics of the VDD1 supply current (Standard characteristics) 15 10 5 0 20 10 0 0 1 2 3 4 fφCLK – φCLK clock frequency [MHz] 0 5 Offset level vs. VDD1 characteristics (Standard characteristics) 1 2 3 4 fφCLK – φCLK clock frequency [MHz] Offset level vs. VDD2 characteristics (Standard characteristics) 6 6 Ta = 25°C Ta = 25°C 5 Vos – Offset level [V] 5 4 3 2 ∆Vos ∆VDD1 4 3 2 ∆Vos ∆VDD2 0.35 1 –0.14 1 0 0 8.5 9 9.5 4.75 VDD1 [V] 5 VDD2 [V] Offset level vs. Temperature characteristics (Standard characteristics) 6 5 Vos – Offset level [V] Vos – Offset level [V] 5 4 3 2 ∆Vos ∆Ta –0.8mV/°C 1 0 0 10 30 50 20 40 Ta – Ambient temperature [°C] – 12 – 60 5.25 ILX514 Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Regulation for raising and lowering the power supply voltage When raising the supply voltage, first raise VDD1 (9V) and then VDD2 (5V). Similarly, lower VDD2 (5V) first and then VDD1 (9V). 3) Notes on handling CCD Cer-DIP Packages The following points should be observed when handling and installing cer-DIP packages. a) Remain within the following limits when applying a static load to the ceramic portion of the package: (1) Compressive strength: 39N/surface (Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Upper ceramic layer 39N Lower ceramic layer (1) Low-melting glass 29N 29N (2) (3) 0.9Nm (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. – 13 – ILX514 4) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. 5) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 6) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 7) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. – 14 – 5.0 ± 0.5 – 15 – V H 1 22 8.19 ± 0.8 Cer-DIP TIN PLATING 42 ALLOY 5.2g LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT 2.54 No.1 Pixel 40.2 41.6 ± 0.5 27.426 (7µm × 3918Pixels) PACKAGE MATERIAL PACKAGE STRUCTURE 4.0 ± 0.5 11 12 0.51 22pin DIP (400mil) 9.0 φ0.3 3.65 Unit: mm 10.0 ± 0.5 M 4.45 ± 0.5 Package Outline 0.25 0° to 9° (AT STAND OFF) 10.16 2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5. 1. The height from the bottom to the sensor surface is 2.45 ± 0.3mm. ILX514