ILX703A
2048-pixel CCD Linear Image Sensor (B/W) with Shutter Function
For the availability of this product, please contact the sales office.
Description
The ILX703A is a reduction type CCD linear sensor
designed for facsimile, image scanner and OCR use.
This sensor reads B4 size documents at a density of
200 DPI (Dot Per Inch). Featuring a shutter function,
correspondences with the sensitivity correction, etc,
is possible. A built-in timing generator and clockdrivers ensure direct drive at 5V logic for easy use.
22 pin DIP (Ceramic)
Features
• Number of effective pixels: 2048 pixels
• Pixel size: 14µm × 14µm (14µm pitch)
• Built-in timing generator and clock-drivers
• Shutter function
• Ultra low lag
• Maximum clock frequency: 5MHz
Absolute Maximum Ratings
• Supply voltage
VDD1
VDD2
• Operating temperature
• Storage temperature
11
6
–10 to +55
–30 to +80
V
V
°C
°C
Pin Configuration (Top View)
22
VDD2
2
21
EXRS
GND
3
20
VDD1
SHSW
4
19
RSSW
φCLK
5
18
VGG
VDD1
6
17
GND
GND
7
16
GND
VDD2
8
15
VDD1
SHUT
9
14
NC
13
NC
12
GND
VOUT
1
GND
1
NC 10
φROG 11
2048
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E93124D78-PS
9
11
4
21
19
5
8
7
6
3
2
GND
Shutter gate
pulse generator
GND
Read out gate
pulse generator
10
VDD1
Mode
selector
12
GND
Clock pulse generator
Sample-and-hold pulse
generator
Clock-drivers
CCD analog shift register
Read out gate
13
VDD2
VGG 18
AAAA
AA
.
VDD2
φCLK
Output amplifier
Sample-and-hold
circuit
Shutter gate
S2047
RSSW
1
14
VDD1
Shutter drain
NC
15
D34
EXRS
VOUT
VDD1
D14
16
AAAAAAAAAAAAA
AAAAAAAAAAAAA
D15
GND
S1
GND
D33
17
S2
NC
S2048
20
D35
SHSW
D37
GND
D36
NC
D38
22
D39
φROG
–2–
SHUT
Block Diagram
ILX703A
ILX703A
Pin Description
Pin No.
Symbol
Description
1
VOUT
Signal output
2
GND
GND
3
GND
GND
4
SHSW
Switch
5
φCLK
Clock pulse
6
VDD1
9V power supply
7
GND
GND
8
VDD2
5V power supply
9
SHUT
Shutter pulse
10
NC
NC
11
φROG
Clock pulse
12
GND
GND
13
NC
NC
14
NC
NC
15
VDD1
9V power supply
16
GND
GND
17
GND
GND
18
VGG
Output circuit gate bias
19
RSSW
Reset pulse swithover pin
(External RS → VDD2, Internal RS → GND)
20
VDD1
9V power supply
21
EXRS
RS input pin during external RS pulse usage
22
VDD2
5V power supply
{
with S/H → GND
without S/H → VDD2
–3–
ILX703A
Recommended Voltage
Item
Min.
Typ.
Max.
Unit
VDD1
8.5
9.0
9.5
V
VDD2
4.75
5.0
5.25
V
Note) Rules for raising and lowering power supply voltage
To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V).
To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).
Mode Description
Mode in use
RS
Pin condition
S/H
Internal
Externel
4 pin SHSW 19 pin RSSW 21 pin EXRS
Yes
GND
GND
VDD2
No
VDD2
GND
VDD2
No
VDD2
VDD2
φRS
Input Capacity of Pins
Item
Symbol
Min.
Typ.
Max.
Unit
Input capacity of φCLK pin
CφCLK
—
10
—
pF
Input capacity of φROG pin
CφROG
—
10
—
pF
Input capacity of SHUT pin
CSHUT
—
10
—
pF
Input capacity of EXRS pin
CEXRS
—
10
—
pF
Recommended Input Pulse Voltage
Parameter
Min.
Typ.
Max.
Unit
Input clock high level
4.5
5.0
5.5
V
Input clock low level
0.0
—
0.5
V
–4–
ILX703A
Electro-optical Characteristics
(Ta = 25°C, VDD1 = 9V, VDD2 = 5V, Clock frequency: 1MHz,
Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm)),
When Internal RS (Pin 19 = GND, Pin 21 = VDD2)
Item
Symbol
Min.
Typ.
Max.
Unit
Remarks
Sensitivity 1
R1
22.5
30
37.5
V/(lx · s)
Note 1
Sensitivity 2
R2
—
95
—
V/(lx · s)
Note 2
Sensitivity 3
R3
—
20
—
V/(lx · s)
Note 3
Sensitivity 4
R4
—
500
—
V/(lx · s)
Note 4
Sensitivity nonuniformity
PRNU
—
2.0
8.0
%
Note 5
Saturation output voltage
VSAT
1.5
1.8
—
V
—
Dark voltage average
VDRK
—
0.3
2.0
mV
Note 6
Dark signal nonuniformity
DSNU
—
0.5
3.0
mV
Note 6
Image lag
IL
—
0.02
—
%
Note 7
Dynamic range
DR
—
6000
—
—
Note 8
Saturation exposure
SE
—
0.060
—
lx · s
Note 9
9V supply current
IVDD1
—
8.0
14.0
mA
—
5V supply current
IVDD2
—
3.0
6.0
mA
—
Total transfer efficiency
TTE
92.0
97.0
—
%
—
Output impedance
ZO
—
600
—
Ω
—
Offset level
VOS
—
4.5
—
V
Note 10
Shutter lag
SHUT
0
1.0
5.0
%
Note 11
Notes)
1) For the sensitivity test light is applied with a uniform intensity of illumination.
2) W lamp (2854K)
3) Light source: LED λ = 570nm
4) Light source: LED λ = 660nm
5) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1.
PRNU =
(VMAX – VMIN)/2
× 100 [%]
VAVE
The maximum output is set to VMAX, the minimum output to VMIN and the average output to VAVE.
6) Integration time is 10ms.
7) VOUT = 500mV
8) DR = VSAT/VDRK
When optical accumulated time is shorter, the dynamic range gets wider because dark voitage is in
proportion to optical accumulated time.
9) SE = VSAT/R1
–5–
ILX703A
10) VOS is defined as indicated below.
D31
D32
D33
S1
OS
VOS
GND
11) To stipulate the lag during shutter operation, use the formula below.
Place the output voltage average value during shutter operation at VSHUT and the output voltage average
value when the shutter is not in operation at VAVE. (Refer to Figure 7.)
SHUT = VSHUT × 100 [%]
VAVE
Please note that the shutter pulse at this time accord with Figure 6.
–6–
VOUT∗
φCLK
0
5
0
–7–
1-line output period (2087 pixels)
Effective picture
elements signal
(2048 pixels)
D31
D32
D33
S1
S2
S3
S4
Optical black
(18 pixels)
D11
D12
D13
D14
D15
Dummy signal (33 pixels)
1
D1
φROG
2
3
4
D2
D3
D4
D5
D6
5
2087
∗ Internal S/H is not in use (Pin4 → VDD2)
Dummy signal
(6 pixels)
S2045
S2046
S2047
S2048
D34
D35
D36
D37
D38
D39
Figure 1. Clock Timing Diagram (For internal RS mode)
ILX703A
2
1
VOUT
φRS
φCLK
φROG
0
5
0
5
0
2
3
4
–8–
1-line output period (2087 pixels)
Effective picture
elements signal
(2048 pixels)
D31
D32
D33
S1
S2
S3
S4
Optical black
(18 pixels)
D11
D12
D13
D14
D15
Dummy signal (33 pixels)
D2
D3
D4
D5
D6
5
2087
Dummy signal
(6 pixels)
S2045
S2046
S2047
S2048
D34
D35
D36
D37
D38
D39
1
Figure 2. Clock Timing Diagram (For external RS mode)
ILX703A
2
1
ILX703A
Figure 3. φCLK, VOUT Timing (For internal RS mode)
t1
t2
φCLK
t3
t4
t10
AAAA
AAAA
AAAA
VOUT
t17
Item
Symbol
AAAAAA
AAAAAA
AAAAAA
Min.
Typ.
Max.
Unit
0
10
—
ns
40
50
60
%
φCLK pulse rise/fall time
φCLK pulse duty∗1
t1, t2
φCLK – VOUT 1
t10
50
80
110
ns
φCLK – VOUT 2
t17
30
75
120
ns
—
∗1 100 × t3/(t3 + t4)
–9–
ILX703A
Figure 4. φCLK, φRS, VOUT Timing (For external RS mode)
t1
t2
φCLK
t3
t4
t5
φRS
t8
t9
t6
t7
t11
t10
AAAA
AAAA
VOUT
t18
AAAAAA
AAAAAA
Item
Symbol
Min.
Typ.
Max.
Unit
φCLK, φRS pulse rise/fall time
φCLK pulse duty∗1
t1, t2, t8, t9
—
10
50
ns
—
40
50
60
%
φCLK – φRS pulse timing
t6
0
100
—
ns
φCLK – φRS pulse timing
t7
50
100
—
ns
φRS pulse period
t5
50
100
—
ns
φCLK – VOUT
t10
50
80
110
ns
φRS – VOUT
t11, t18
30
50
70
ns
∗1 100 × t3/(t3 + t4)
– 10 –
ILX703A
Figure 5. φROG, φCLK Timing
φROG
t13
t14
t15
φCLK
t12
Item
Symbol
t16
Min.
Typ.
Max.
Unit
φROG, φCLK pulse timing
t12, t16
500
1000
—
ns
φROG pulse rise/fall time
t13, t15
0
10
—
ns
φROG pulse period
t14
500
1000
—
ns
– 11 –
– 12 –
0
5
0
5
0
Illumination∗
φSHUT
φCLK
φROG
5
2087 bits or more
∗ During shutter lag evaluation, the light source will be accompanied by a flash.
Light
source
ON
Figure 6. Shutter Operation Mode Clock
1ms
ILX703A
– 13 –
VOUT
φSHUT
Illumination
φROG
0V
5V
0V
5V
ON
Figure 7. Shutter Pulse and Output Voltage
OFF
VAVE
ON
Shutter ON
OFF
VSHUT
ON
OFF
ILX703A
ILX703A
∗ Description of Shutter Pin 9
1) The state at 5V is when the shutter is not in operation.
2) When dropped to 0V, the shutter gate will open, letting the accumulated charge of the sensor be thrown
away to the shutter drain.
φROG
5V
0V
AAAAAAAAAA
AAAAAAAAAAAAAAAAAA
The charge is sent to the transfer register as
signal charge.
Accumulated charge
of the sensor
The charge up to this point will be thrown away
to the shutter drain.
φSHUT
5V
0V
Shutter gate ON
– 14 –
ILX703A
Example of Representative Characteristics
Spectral sensitivity characteristics
(Standard characteristics)
1.0
Ta = 25°C
0.9
Relative sensitivity
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400
500
600
700
800
Wavelength [nm]
MTF of main scanning direction
(Standard characteristics)
Spatial frequency [cycles/mm]
7.1
14.3
21.4
28.6
1000
MTF of sub scanning direction
(Standard characteristics)
35.7
0
1.0
1.0
0.8
0.8
0.6
0.6
Spatial frequency [cycles/mm]
7.1
14.3
21.4
28.6
35.7
Y-MTF
X-MTF
0
900
0.4
0.4
0.2
0.2
0
0
0
0.2
0.4
0.6
0.8
Normalized spatial frequency
0
1.0
– 15 –
0.2
0.4
0.6
0.8
Normalized spatial frequency
1.0
ILX703A
Dark signal voltage rate vs. Ambient temperature
(Standard characteristics)
VDD1, VDD2 supply current vs. Clock frequency
(Standard characteristics)
IVDD1
10
10
5
5
IVDD1, IVDD2 – VDD1, VDD2 supply current [mA]
Dark signal voltage rate
IVDD2
1
0.5
0.1
0
1
0.5
0.1
0.1M
10
20
30
40
50
Ta – Ambient temperature [°C]
– 16 –
1M
Clock frequency [Hz]
5M
0.01µ
9V
5V
– 17 –
Output signal
3kΩ
10µ/16V
1Ω
2SA1175
VOUT
1
(D)
GND
2
21
EXRS
22
VDD2
(D)
Application Circuit (When internal RS)
20
19
SHSW
4
RSSW
18
φCLK
5
φCLK
VGG
17
(A)
VDD1
6
22 pin DIP
GND
(A)
16
(D)
GND
7
GND
(A)
15
(D)
VDD2
8
VDD1
(A)
14
φSHUT
SHUT
9
NC
13
NC
10
NC
12
φROG
11
φROG
GND
(D)
0.01µ
22µ/10V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
(A)
GND
3
VDD1
(A)
10µ/16V
ILX703A
ILX703A
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Regulation for raising and lowering the power supply voltage
When raising the supply voltage, first raise VDD1 (9V) and then VDD2 (5V). Similarly, lower VDD2 (5V) first and
then VDD1 (9V).
3) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, ground the controller. For the control system, use a zero cross type.
4) Dust and dirt protection
a) Operate in clean environments.
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air
is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
– 18 –
5.0 ± 0.5
– 19 –
V
7.35 ± 0.8
H
1
22
Cer-DIP
TIN PLATING
42 ALLOY
3.9g
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
2.54
No.1 Pixel
40.2
11
12
0.51
22pin DIP (400mil)
41.6 ± 0.5
28.672 (14µm × 2048Pixels)
PACKAGE MATERIAL
PACKAGE STRUCTURE
4.0 ± 0.5
Unit: mm
9.0
10.0 ± 0.5
0.3
2.6
3.3 ± 0.5
Package Outline
M
0.25
0° to 9°
(AT STAND OFF)
10.16
2. The thickness of the cover glass is 0.7mm, and the refractive
index is 1.5 .
1. The height from the bottom to the sensor surface is 1.61 ± 0.3mm.
ILX703A