HV518 32-Channel Vacuum-Fluorescent Display Driver Ordering Information Package Options Device 40 Pin Dip 44 Plastic Chip Carrier Die HV518 HV518P HV518PJ HV518X Features General Description ❏ 32 output lines The HV518 is designed for vacuum fluorescent or DC plasma applications, where it can serve as a segment, digit or matrix display driver. Each device has 32 outputs, 32 latches and a 32 bit cascadable shift register. ❏ 90V output swing ❏ Active pull-down ❏ Latches on all outputs Serial data enters the shift register on the LOW-to-HIGH transition of the clock input. With latch enable (LE) HIGH, parallel data is transferred to the output buffers through a 32-bit latch. When LE is low the data is stored in the latch. When STROBE is LOW, all outputs are enabled; if STROBE is HIGH, all outputs are LOW. ❏ Up to 6MHz @ VDD = 5V ❏ -40°C to +85°C operation Absolute Maximum Ratings Supply voltage, VDD 1 -0.5V to +6.0V 1 -0.5V to +90V Supply voltage, VPP Logic input levels1 Continuous total power dissipation -0.5V to VDD +0.5V 2,3 Operating temperature range Storage temperature range Lead temperature 1.6mm(1/16 inch) from case for 10 seconds 1200mW -40°C to +85°C -65°C to +150°C 260°C Notes: 1. All voltages referenced to GND. 2. Duty cycle is limited by the total power dissipated in the package. 3. For operation above 25°C ambient, derate linearly to 85°C at 20mW/°C. 12/13/01 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the 1 refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, HV518 Electrical Characteristics (over recommended ranges of operating free-air temperature and VDD. Unless otherwise noted, VPP = 80V) Symbol Parameter Min Typ Max Units Conditions IDD Supply current 10 mA VDD = 5V, fCH = 6.0 MHz IDDQ Quiescent supply current 0.5 mA VDD = 5.5V, VIN = 0V IPP Supply current 12 mA Output high, TA = -40°C 10 mA Output high, TA = 0 to +85°C 500 µA Outputs low V IOH= -25mA 5 V VDD = 5V, IOH = -20µA 5 V IOL= 1mA 0.06 0.8 V IOL =20µA 7 VOH High-level output voltage HVoutput 70.0 Serial output VOL Low-level output 4.5 4.9 HVoutput Serial output IIH High-level logic input current 0.1 1 µA VIH = VDD IIL Low-level logic input current -0.1 -1 µA VIL = 0V Note: The total number of ON outputs times the duty cycle must not exceed the allowable package power disspation. Switching Characteristics (VPP = 80V, CL = 50 pF, TA = 25°C, unless otherwise noted) Symbol Parameter td Delay time, Clock to data output VDD = 4.5V tDHL Delay time, high-to-low-level, from latch enable VDD = 4.5V HVoutput from strobe Delay time, low-to-high-level from latch enable HVoutput from strobe tDLH Min Max Unit Conditions 600 ns CL =15 pF See Figure 4 1.5 µs See Figure 5 1 VDD = 4.5V 1.5 See Figure 6 See Figure 5 µs 1 See Figure 6 tTHL Transition time, high-to-low-level, HVoutput VDD = 4.5V 3 µs See Figure 6 tTLH Transition time, low-to-high-level, HVoutput VDD = 4.5V 2.5 µs See Figure 6 Recommended Operating Conditions (TA = 25°C, unless otherwise noted) Symbol Parameter Min Max Units 4.5 5.5 V 8 80 V VDD Logic voltage supply VPP High voltage supply VIH High-level input voltage (See Fig.3.) VDD = 4.5V VIL Low-level input voltage (See Fig. 3.) VDD = 4.5V IOH High-level output current IOL Low-level output current fCLK Clock frequency (see Figure 3) VDD = 4.5V tw(CKH) Pulse duration , clock high VDD = 4.5V 83 ns tw(CKL) Pulse duration , clock low VDD = 4.5V 83 ns tsu Setup time, data before clock VDD = 4.5V 75 ns th Hold time, data after clock VDD = 4.5V 75 ns TA Operating free-air temperature Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 3.5 V 1 -25 -40 4. 5. Apply VPP. The VPP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. 2 V mA 2 mA 6.0 MHz 85 °C HV518 Input and Output Equivalent Circuits VDD VDD VPP Data Out Input GND GND HVOUT GND Logic Data Output Logic Inputs High Voltage Outputs Parameter Measurement Information t w(CKH) V IH Clock V IH Latch Enable 50% 50% V IL V IL t w(CKL) t DLH or t DHL t su th V OH 90% HV Output V IH 10% Data In V OL V IL Figure 3: Input Timing Voltage Waveforms Figure 5 V IH t w(CKH) Clock 50% Strobe V IH V IL 50% t DLH V IL td t DHL 90% HV Output 10% V OH Data Output 50% t TLH V OH V OL t THL V OL Figure 4 Figure 6: Switching-Time Voltage Waveforms Note: For testing purposes, all input pulses have maximum rise and fall times of 30 nsec. 3 HV518 Block Diagram LE STB V PP HV OUT1 D IN 32-Bit Latches Shift CLK Register D OUT HV OUT 32 Truth Tables Output Input Data Out Data In LE STB HV Outputs H H X X H All Low L L H H L High * L H L Low X L L * Data In X CLK No Change * Previous state * Previous state Typical Operating Sequence Clock • • • Data In SR Contents VALID IRRELEVANT INVALID VALID Latch Enable Latch Contents PREVIOUSLY STORED DATA NEW DATA VALID Strobe HV Output VALID 4 HV518 Pin Configurations HV518 40 Pin Dual-In-Line Package Pin Function Pin 1 VPP 21 2 Serial Out 22 3 HVOUT 32 23 4 HVOUT 31 24 5 HVOUT 30 25 6 HVOUT 29 26 7 HVOUT 28 27 8 HVOUT 27 28 9 HVOUT 26 29 10 HVOUT 25 30 11 HVOUT 24 31 12 HVOUT 23 32 13 HVOUT 22 33 14 HVOUT 21 34 15 HVOUT 20 35 16 HVOUT 19 36 17 HVOUT 18 37 18 HVOUT 17 38 19 Strobe 39 20 GND 40 HV518 44 Pin J-Lead Package Pin Function 1 VPP 2 Serial Out 3 HVOUT 32 4 HVOUT 31 5 HVOUT 30 6 N/C 7 HVOUT 29 8 HVOUT 28 9 HVOUT 27 10 HVOUT 26 11 HVOUT 25 12 HVOUT 24 13 HVOUT 23 14 HVOUT 22 15 HVOUT 21 16 HVOUT 20 17 HVOUT 19 18 N/C 19 HVOUT 18 20 HVOUT 17 21 Strobe 22 GND Package Outline Function Clock LE HVOUT 16 HVOUT 15 HVOUT 14 HVOUT 13 HVOUT 12 HVOUT 11 HVOUT 10 HVOUT 9 HVOUT 8 HVOUT 7 HVOUT 6 HVOUT 5 HVOUT 4 HVOUT 3 HVOUT 2 HVOUT 1 Data In VDD 1 40 20 21 top view 40-pin DIP 39 38 37 36 35 34 33 32 31 30 29 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function Clock LE HVOUT 16 HVOUT 15 HVOUT 14 N/C N/C HVOUT 13 HVOUT 12 HVOUT 11 HVOUT 10 HVOUT 9 HVOUT 8 HVOUT 7 HVOUT 6 HVOUT 5 HVOUT 4 HVOUT 3 HVOUT 2 HVOUT 1 Data In VDD 40 28 41 27 42 26 43 25 44 24 1 23 2 22 3 21 4 20 5 19 6 18 7 8 9 10 11 12 13 14 15 16 17 top view 12/13/010 ©2001 Supertex Inc. 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