W83193R-01 83.MHZ 3-DIMM CLOCK 1.0 GENERAL DESCRIPTION The W83193R-01 is a Clock Synthesizer which provides all clocks required for high-speed RISC or CISC microprocessor such as Intel PentiumPro , AMD or Cyrix. Eight different frequency of CPU and PCI clocks are externally selectable with smooth transitions. The W83193R-02/-04 also provides I2C serial bus interface to program the registers to enable or disable each clock outputs and choose the 0.6% or 1.5% center type spread spectrum. The W83193R-01 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate. 2.0 PRODUCT FEATURES • Supports Pentium, Pentium Pro, Pentium II, AMD and Cyrix CPUs with I2C. • 4 CPU clocks. • 12 SDRAM clocks for 3 DIMs. • 7 PCI synchronous clocks. • One IOAPIC clock for multiprocessor support. • Optional single or mixed supply: (Vdd = Vddq3 = Vddq2 = 3.3V) or (Vdd = Vddq3 = 3.3V, Vddq2 = 2.5V) • < 250ps skew among CPU and SDRAM clocks. • < 250ps skew among PCI clocks. • Smooth frequency switch with selections from 50 MHz to 83.3 MHz CPU. • I2C 2-Wire serial interface. • 0.6% or 1.5% center type spread spectrum function to reduce EMI. • Programmable registers to enable/stop each output and select modes. (mode as Tri-state, or Normal ) • MODE pin for power Management. • 48 MHz for USB. • 24 MHz for super I/O. • 48-pin SSOP package. -1- Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY 3.0 BLOCK DIAGRAM Vdd Xin Xout *SDATA *SDCLK REF OSC Vddq2 b Register CPU_stop# Vddq2 Stop clock Buffers REF[0:1] IOAPIC Buffers CPUCLK[0:3] Buffers Vddq3 PLL 1 SDRAM[0:11] Buffers PCI_stop# Stop clock *MODE *CPU3.3#_2.5 *FS[0:2] LATC H *CPU_STOP# *PCI_STOP # Contr ol Logic Vddq3 PCICLK[0:5] Dela y Buffers Vddq3 Buffers PCICLK_F Vddq3 48MHz PLL2 Vddq3 Buffers 1/2 24MHz Buffers 4.0 PIN CONFIGURATION Vdd REF0 Vss Xin Xout Vddq3 PCICLK_F/*FS1 PCICLK0/*FS2 Vss PCICLK1/*FTS PCICLK2 PCICLK3 PCICLK4 Vddq3 PCICLK5/PCI_STOP# Vss SDRAM11 SDRAM10 Vddq3 SDRAM 9 SDRAM 8 Vss *SDATA *SDCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 -2- Vddq2 IOAPIC REF1/CPU_STOP# Vss CPUCLK0 CPUCLK1 Vddq2 CPUCLK2 CPUCLK3 Vss SDRAM 0 SDRAM 1 Vddq3 SDRAM 2 SDRAM 3 Vss SDRAM 4 SDRAM 5 Vddq3 SDRAM 6 SDRAM 7 Vss 48MHz/*FS0 24MHz/*MODE Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY 5.0 PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250kΩ pull-up 5.1 Crystal I/O SYMBOL PIN I/O Xin 4 IN Xout 5 OUT FUNCTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally. 5.2 CPU, SDRAM, PCI Clock Outputs SYMBOL CPUCLK [ 0:3 ] IOAPIC SDRAM [ 0:11] PCICLK_F/ *FS1 PIN I/O FUNCTION 40,41,43,44 OUT Low skew (< 250ps) clock outputs for host frequencies such as CPU, Chipset and Cache. Vddq2 is the supply voltage for these outputs. 47 OUT High drive buffered output of the crystal, and is powered by VDDq2. 17,18,20,21,28 ,29,31,32,34, 35,37,38 O SDRAM clock outputs which have the same frequency as CPU clocks. 7 I/O Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Free running PCI clock during normal operation. PCICLK 0 / *FS2 8 I/O Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. PCI clock during normal operation. PCICLK 1/ *FTS 10 I/O Latched input for FTS at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. PCI clock during normal operation. -3- Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY 5.2 CPU, SDRAM, PCI Clock Outputs, continued SYMBOL SDRAM [ 0: 11 ] PCICLK [ 2:4 ] PIN I/O 17,18,20,21, 28,29,31,32, 34,35,37,38 O 11,12,13 OUT 15 I/O PCICLK5/ PCI_STOP# FUNCTION Synchronous DRAM DIMs clocks which have the same frequency as CPU clocks Low skew (< 250ps) PCI clock outputs. Internal 250kΩ pull-up. If MODE = 1 (default), then this pin is a PCI5 clock output. If MODE = 0 , then this pin is PCI_STOP # and used in power management mode for synchronously stopping the all PCI clocks. 2 5.3 I C Control Interface SYMBOL PIN I/O FUNCTION *SDATA 23 I/O Serial data of I2C 2-wire control interface with internal pull-up resistor. *SDCLK 24 IN Serial clock of I2C 2-wire control interface with internal pull-up resistor. 5.4 Fixed Frequency Outputs SYMBOL PIN I/O FUNCTION REF0 2 I/O Internal 250kΩ pull-up buffered output of the crystal. REF1 / CPU_STOP# 46 I/O Internal 250kΩ pull-up. If MODE =1 (default), then this pin is a REF1 buffered output of the crystal. If MODE = 0 , then this pin is CPU_STOP# input used in power management mode for synchronously stopping the all CPU clocks. 24MHz / *MODE 25 I/O Internal 250kΩ pull-up. Latched input for MODE at initial power up. 24MHz output for super I/O during normal operation. 48MHz / *FS0 26 I/O Internal 250kΩ pull-up. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 48MHz output for USB during normal operation. -4- Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY 5.5 Power Pins SYMBOL PIN Vdd FUNCTION 1 Power supply for Ref [0:1] crystal and core logic. Vddq2 42, 48 Power supply for IOAPIC output and CPUCLK[0:3], either 2.5V or 3.3V. Vddq3 6,14,19, 30, 36 Power supply for SDRAM, PCICLK and 48/24MHz outputs. Vss 3,9,16,22,27, 33,39,45 Circuit Ground. 6.0 FREQUENCY SELECTION FTS = 1 (MHz) FTS = 0 (MHz) REF,IOAPIC (MHz) FS2 FS1 FS0 CPU PCI CPU PCI 0 0 0 61.8 30.9 62.4 31.2 14.318 0 0 1 75 30 78 39 14.318 0 1 0 83.3 33.3 85.8 42.8 14.318 0 1 1 68.5 34.25 69.5 34.74 14.318 1 0 0 55 27.5 83.3 41.7 14.318 1 0 1 75 37.5 75 32 14.318 1 1 0 60 30 80 40 14.318 1 1 1 66.8 33.4 50 25 14.318 -5- Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY 7.0 FUNTION DESCRIPTION 7.1 POWER MANAGEMENT FUNCTIONS All clocks can be individually enabled or disabled via the 2-wire control interface. On power up, external circuitry should allow 3 ms for the VCO’s to stabilize prior to enabling clock outputs to assure correct pulse widths. When MODE=0, pins 15 and 46 are inputs (PCI_STOP#), (CPU_STOP#), when MODE=1, these functions are not available. A particular clock could be enabled as both the 2-wire serial control interface and one of these pins indicate that it should be enable. The W83193R-01 may be disabled in the low state according to the following table in order to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop. The CPU and PCI clocks transform between running and stop by waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. CPU_STOP# PCI_STOP# CPU PCI OTHER CLKs XTAL & VCOs 0 0 LOW LOW RUNNING RUNNING 0 1 LOW RUNNING RUNNING RUNNING 1 0 RUNNING LOW RUNNING RUNNING 1 1 RUNNING RUNNING RUNNING RUNNING 2 7.2 2-WIRE I C CONTROL INTERFACE The 2-wire control interface implements a write only slave interface and cannot be read back. All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. On power up, the W83193R-01 initializes with default register settings, and then it’s optional to use the 2-wire control interface. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated. Byte writing starts with a “start” condition followed by 7-bit slave address and a write command bit [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an “acknowledge“ (low) on the SDATA wire will be generated by the clock 2 chip. Controller can start to write to internal I C registers after the string of data. The sequence order is as follows: -6- Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY Bytes sequence order for I2C controller : Clock Address A(6:0) & R/W Ack 8 bits dummy Command code Ack 8 bits dummy Byte count Ack Byte0,1,2... until Stop 7.3 SERIAL CONTROL REGISTERS The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. 7.3.1 Register 0: CPU Frequency Select Register (1 = enable, 0 = Stopped) Bit @PowerUp Pin Description 7 1 - FTS(for frequency table selection by software via I2C) 6 5 1 1 - FS2 (for frequency table selection by software via I2C) FS1 (for frequency table selection by software via I2C) 4 3 1 0 - 2 x n/a FS0 (for frequency table selection by software via I2C) 0 = Selection by hardware 1 = Selection by software I2C Reserved 1 0 0 0 - Bit1 Bit0 1 1 Tri-state all outputs 1 0 ±0.6% Spread Spectrum 0 1 ±1.5% Spread Spectrum 0 0 Normal FUNCTION TABLE Function Outputs Description CPU PCI SDRAM REF IOAPIC Tri-State Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Normal see table see table CPU 14.318 14.318 -7- Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY 7.3.2 Register 1 : CPU , 48/24 MHz Clock Register (1 = enable, 0 = Stopped) Bit @PowerUp Pin Description 7 1 26 48MHz (Active / Inactive) 6 1 25 24 MHz (Active / Inactive) 5 1 - 0 - test mode, 1 - normal mode 4 X - Reserved 3 1 40 CPUCLK3 (Active / Inactive) 2 1 41 CPUCLK2 (Active / Inactive) 1 1 43 CPUCLK1 (Active / Inactive) 0 1 44 CPUCLK0 (Active / Inactive) 7.3.3 Register 2: PCI Clock Register (1 = enable, 0 = Stopped) Bit @PowerUp Pin Description 7 x - Reserved 6 1 7 PCICLK_F / FS1 (Active / Inactive) 5 1 15 PCICLK5 / PCI_STOP# (Active / Inactive) 4 1 13 PCICLK4 (Active / Inactive) 3 1 12 PCICLK3 (Active / Inactive) 2 1 11 PCICLK2 (Active / Inactive) 1 1 10 PCICLk1/FTS (Active / Inactive) 0 1 8 PCICLK0 / FS2 (Active / Inactive) 7.3.4 Register 3: SDRAM Clock Register ( 1 = enable, 0 = Stopped ) Bit @PowerUp Pin Description 7 1 28 SDRAM7 (Active / Inactive) 6 1 29 SDRAM6 (Active / Inactive) 5 1 31 SDRAM5 (Active / Inactive) 4 1 32 SDRAM4 (Active / Inactive) 3 1 34 SDRAM3 (Active / Inactive) 2 1 35 SDRAM2 (Active / Inactive) 1 1 37 SDRAM1 (Active / Inactive) 0 1 38 SDRAM0 (Active / Inactive) -8- Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY 7.3.5 Register 4: Additional SDRAM Clock Register (1 = enable, 0 = Stopped) Bit @PowerUp Pin Description 7 x - Reserved 6 x - Reserved 5 x - Reserved 4 x - Reserved 3 1 17 SDRAM11 (Active / Inactive) 2 1 18 SDRAM10 (Active / Inactive) 1 1 20 SDRAM9 (Active / Inactive) 0 1 21 SDRAM8 (Active / Inactive) 7.3.6 Register 5: Peripheral Control (1 = enable, 0 = Stopped) Bit @PowerUp Pin Description 7 x - Reserved 6 x - Reserved 5 x - Reserved 4 1 47 3 x - Reserved 2 x - Reserved 1 1 46 REF1 / CPU_STOP# (Active / Inactive) 0 1 2 REF0 (Active / Inactive) IOAPIC (Active / Inactive) 7.3.7 Register 6: Reserved Register Bit @PowerUp Pin Description 7 x - Reserved 6 x - Reserved 5 x - Reserved 4 x - Reserved 3 x - Reserved 2 x - Reserved 1 x - Reserved 0 x - Reserved -9- Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY 8.0 SPECIFICATIONS 8.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). Symbol Parameter Rating Vdd , VIN Voltage on any pin with respect to GND - 0.5 V to + 7.0 V TSTG Storage Temperature - 65°C to + 150°C TB Ambient Temperature - 55°C to + 125°C TA Operating Temperature 0°C to + 70°C 8.2 AC CHARACTERISTICS Vdd = Vddq3 = 3.3V ± 5 %, Vddq2= 2.375V~2.9V , TA = 0°C to +70°C Parameter Symbol Output Duty Cycle Min Typ Max Units 45 50 55 % Measured at 1.5V 4 ns 15 pF Load Measured at 1.5V 15 pF Load Measured at 1.5V CPU/SDRAM to PCI Offset tOFF Skew (CPU-CPU), (PCIPCI), (SDRAM-SDRAM) tSKEW 250 ps tCCJ ¡Ó250 ps tJA 500 ps BWJ 500 KHz 0.4 1.6 ns 15 pF Load on CPU and PCI outputs CPU/SDRAM 1 Test Conditions Cycle to Cycle Jitter CPU/SDRAM Absolute Jitter Jitter Spectrum 20 dB Bandwidth from Center Output Rise (0.4V ~ 2.0V) tTLH & Fall (2.0V ~0.4V) Time tTHL Overshoot/Undershoot Vover 0.7 1.5 V 22 Ω at source of 8 inch PCB run to 15 pF load VRBE 0.7 2.1 V Ring Back must not enter this range. Beyond Power Rails Ring Back Exclusion - 10 - Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY 8.3 DC CHARACTERISTICS Vdd = Vddq3 = 3.3V ± 5 %, Vddq2 = 2.375V~2.9V , TA = 0°C to +70°C Parameter Symbol Min Typ Max Units 0.8 Vdc Test Conditions Input Low Voltage VIL Input High Voltage VIH Input Low Current IIL -66 µA Input High Current IIH 5 µA Output Low Voltage VOL 0.4 Vdc All outputs Vdc All outputs using 3.3V power 2.0 Vdc IOL = 4 mA Output High Voltage VOH 2.4 IOH = 4mA Tri-State leakage Current Ioz Dynamic Supply Current Idd3 10 µA mA PCI = 33.3 Mhz with load for Vdd + Vddq3 Dynamic Supply Current CPU = 66.6 MHz Idd2 mA Same as above ICPUS3 mA Same as above ICPUS2 mA Same as above IPD3 mA for Vddq2 + Vddq2b CPU Stop Current for Vdd + Vddq3 CPU Stop Current for Vddq2 + Vddq2b PCI Stop Current for Vdd + Vddq3 - 11 - Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY 8.4 BUFFER CHARACTERISTICS 8.4.1 TYPE 1 BUFFER FOR CPU (0:3) Parameter Symbol Min Pull-Up Current Min IOH(min) -27 Pull-Up Current Max IOH(max) Pull-Down Current Min IOL(min) Pull-Down Current Max IOL(max) Rise/Fall Time Min Between 0.4 V and 2.0 V TRF(min) Rise/Fall Time Max Between 0.4 V and 2.0 V TRF(max) Typ Max -27 27 0.4 1.6 Units Test Conditions mA Vout = 1.0 V mA Vout = 2.0V mA Vout = 1.2 V mA Vout = 0.3 V ns 10 pF Load ns 20 pF Load 8.4.2 TYPE 2 BUFFER FOR IOAPIC Parameter Symbol Pull-Up Current Min IOH(min) Pull-Up Current Max IOH(max) Pull-Down Current Min IOL(min) Pull-Down Current Max IOL(max) Rise/Fall Time Min Between 0.7 V and 1.7 V TRF(min) Rise/Fall Time Max Between 0.7 V and 1.7 V TRF(max) Min Typ Max -29 28 0.4 1.8 - 12 - Units Test Conditions mA Vout = 1.4 V mA Vout = 2.7V mA Vout = 1.0 V mA Vout = 0.2 V ns 10 pF Load ns 20 pF Load Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY 8.4.3 TYPE 3 BUFFER FOR REF1, 24MHZ, 48MHZ Parameter Symbol Min Pull-Up Current Min IOH(min) -29 Pull-Up Current Max IOH(max) Pull-Down Current Min IOL(min) Pull-Down Current Max IOL(max) Rise/Fall Time Min Between 0.8 V and 2.0 V TRF(min) Rise/Fall Time Max TRF(max) Typ Max Units Test Conditions mA Vout = 1.0 V mA Vout = 3.135V mA Vout = 1.95 V mA Vout = 0.4 V ns 10 pF Load 4.0 ns 20 pF Load Max Units -23 29 1.0 Between 0.8 V and 2.0 V 8.4.4 TYPE 4 BUFFER FOR SDRAM(0:11) Parameter Symbol Pull-Up Current Min IOH(min) Pull-Up Current Max IOH(max) Pull-Down Current Min IOL(min) Pull-Down Current Max IOL(max) Rise/Fall Time Min Between 0.8 V and 2.0 V TRF(min) Rise/Fall Time Max TRF(max) Min Typ Test Conditions mA Vout = 1.65V mA Vout = 3.135V mA Vout = 1.65 V mA Vout = 0.4 V ns 20 pF Load 1.3 ns 30 pF Load Max Units -46 53 0.5 Between 0.8 V and 2.0 V 8.4.5 TYPE 5 BUFFER FOR PCICLK(0:5,F) Parameter Symbol Min Pull-Up Current Min IOH(min) -33 Pull-Up Current Max IOH(max) Pull-Down Current Min IOL(min) Pull-Down Current Max IOL(max) Rise/Fall Time Min Between 0.8 V and 2.0 V TRF(min) Rise/Fall Time Max TRF(max) Typ -33 30 38 0.5 2.0 Test Conditions mA Vout = 1.0 V mA Vout = 3.135 V mA Vout = 1.95 V mA Vout = 0.4 V ns 15 pF Load ns 30 pF Load Between 0.8 V and 2.0 V - 13 - Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY 9.0 POWER MANAGEMENT TIMING 9.1 CPU_STOP# Timing Diagram ( synchronous ) CPUCLK (Internal) 2 1 2 1 PCICLK (Internal) PCICLK_F CPU_STOP# CPUCLK[0:3] SDRAM For synchronous Chipset, CPU_STOP# pin is a synchronous “ active low ” input pin used to stop the CPU clocks for low power operation. This pin is asserted synchronously by the external control logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume output with full pulse width. In this case, CPU “clocks on latency“ is less than 2 CPU clocks and “clocks off latency” is less then 2 CPU clocks. 9.2 PCI_STOP# Timing Diagram ( synchronous ) CPUCLK (Internal) PCICLK (Internal) 1 2 1 2 PCICLK_F PCI_STOP# PCICLK[0:5] For synchronous Chipset, PCI_STOP# pin is a synchronous “active low” input pin used to stop the PCICLK [0:5] for low power operation. This pin is asserted synchronously by the external control logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output with full pulse width. In this case, PCI “clocks on latency“ is less than 1 PCI clocks and “clocks off latency” is less then 1 PCI clocks. - 14 - Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY 10.0 OPERATION OF DUAL FUCTION PINS Pins 7, 8, 10, 25, and 26 are dual function pins and are used for selecting different functions in this device (see Pin description). During power up, these pins are in input mode (see Fig1), therefore, and are considered input select pins. When Vdd reaches 2.5V, the logic level that is present on these pins are latched into their appropriate internal registers. Once the correct information are properly latched, these pins will change into output pins and will be pulled low by default. At the end of the power up timer (within 3 ms) outputs starts to toggle at the specified frequency. 2.5V #2 REF0/CPU3.3#_2.5 #7 PCICLK_F/FS1 #8 PCICLK0/FS2 #25 24/MODE #26 48/FS0 Vdd Output pull-low Output tri-state Within 3ms Input All other clocks Output Output pull-low Output tri-state Each of these pins are a large pull-up resistor ( 250 kΩ @3.3V ) inside. The default state will be logic 1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these dual function pins. Under these conditions, an external 10 kΩ resistor is recommended to be connected to Vdd if logic 1 is expected. Otherwise, the direct connection to ground if a logic 0 is desired. The 10 kΩ resistor should be place before the serious terminating resistor. Note that these logic will only be latched at initial power on. If optional EMI reducing capacitor are needed, they should be placed as close to the series terminating resistor as possible and after the series terminating resistor. These capacitor has typical values ranging from 4.7pF to 22pF . - 15 - Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY Vdd 10kΩ Series Terminating Resistor Device Pin Clock Trace EMI Reducing Cap 10kΩ Optional Ground Ground Programming Header Vdd Pad Ground Pad 10kΩ Series Terminating Resistor Device Pin Clock Trace EMI Reducing Cap Optional Ground - 16 - Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY 11.0 POWER SUPPLY SUGGESTION 1.A solid ground plane should be placed around the clock device. Ground connections should be tied to this main ground plane as short as possible. No cuts should be made in the ground plane around the device. 2.C21,C22,C31,C36 are decoupling capacitors (0.1£gF surface mount, low ESR, ceramic capacitors.) They should be placed as possible as the Vdd pin and the ground via. 3.C1 and C2 are supply filtering capacitors for low frequency power supply noise. A 22£gF (or 10£gF) tantalum capacitor is recommended. 4.Use of Ferrite Bead’s (FB) are recommended to further reduce the power supply noise. 5.The power supply race to the Vdd pins must be thick enough so that voltage drops across the trace resistance is negligible. Vdd (3.3V) C1 FB2 FB1 Vdd Plane C31 C32 C33 C34 Vdd2 Plane 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 - 17 - C21 Vdd2 (3.3Vor2.5V) C2 C22 C36 C35 Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY 12.0 ORDERING INFORMATION Part Number Package Type Production Flow W83193R-01 48 PIN SSOP Commercial, 0°C to +70°C 13.0 HOW TO READ THE TOP MARKING W83193R-01 28051234 814GBB 1st line: Winbond logo and the type number: W83193R-01 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; A means ASE, S means SPIL, G means GR BB: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 18 - Publication Release Date: May 1998 Revision 0.20 W83193R-01 PRELIMINARY 14.0 PACKAGE DRAWING AND DIMENSIONS Headquarters Winbond Electronics (H.K.) Ltd. No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. - 19 - Publication Release Date: May 1998 Revision 0.20