W83196S-14A 100MHZ CLOCK FOR BX CHIPSET(2 CHIP) W83196S-14A Data Sheet Revision History Pages Dates Version Version Main Contents On Web 1 n.a. 2 n.a. 02/Apr 1.0 n.a. All of the versions before 0.50 are for internal use. 1.0 Change version and version on web site to 1.0 3 4 5 6 7 8 9 10 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. -1- Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A 1.0 GENERAL DESCRIPTION The W83196S-14A is a Clock Synthesizer which provides all clocks required for high-speed RISC or CISC microprocessor. different frequency of CPU, and PCI clocks are externally selectable with smooth transitions. The W83196S-14A provides I2C serial bus interface to program the registers to enable or disable each clock outputs and choose the 0.5% center type spread spectrum to reduce EMI. The W83196S-14A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate. 2.0 PRODUCT FEATURES • Supports Pentium II CPUs with I2C • 16 sets of CPU frequencies selection • 2 CPU clocks (one free running CPU clock) • 7 PCI synchronous clocks(one free running PCI clock) • Optional single or mixed supply: (VddR = VddCore = VddP = Vdd4 = 3.3V±5%) (VddA = VddC = 2.5V±5%) • Skew form CPU to PCI clock 1.5 to 4.0 ns, CPU leads. • CPU clock jitter less than 200ps • PCI_F,PCI1:6 clock skew less than 500ps • Smooth frequency switch with selections from 66.8 MHz to 150 MHz CPU • I2C 2-Wire serial interface and I2C read back • ±0.5% or ±0.75% center type spread spectrum function to reduce EMI • Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) • MODE pin for power management • 48 MHz for USB • 24 MHz for super I/O • 28-pin SOP package -2- Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A 3.0 BLOCK DIAGRAM VddR REF2X X1 XTAL OSC X2 IOAPIC VddA VddC PLL1 SEL100/66# STOP Spread Spectrum CPUCLK1 ÷2/3/4 SEL48* Latch VddC VddP PCI clock Divder MODE* CPUCLK_F STOP 6 PCICLK(1:6) PCICLK_F Control Logic Config. Reg. CPU_STOP# PCI_STOP# SDATA* SCLK* VddP Vdd4 48MHz PLL2 24/48MHz Vdd4 4.0 PIN CONFIGURATION Xin Xout VssP PCICLK_F PCICLK1 PCICLK2 PCICLK3 PCICLK4 VddP PCI_STOP#/PCICLK5 CPU_STOP#/PCICLK6 Vdd4 48MHz/Mode* 24/48MHz -3- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VssR REF2X/SEL48* VddR VddA IOAPIC VddC CPUCLK_F CPUCLK1 VddCore VssC SDATA SDCLK SEL100/66# Vss4 Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A 5.0 PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin # - Low active * - Internal 250kΩ pull-up 5.1 Crystal I/O SYMBOL PIN I/O Xin 1 IN Xout 2 OUT FUNCTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally. 5.2 CPU, PCI Clock Outputs SYMBOL CPUCLK_F PIN I/O 22,21 OUT Low skew (< 250ps) clock outputs for host frequencies such as CPU, Chipset and Cache. VddC is the supply voltage for these outputs. 4,5,6,7,8 OUT Low skew (< 250ps) PCI clock outputs. 10 I/O If Mode* =1 (default), then this pin is a PCICLK5 buffered output of the crystal. If Mode* = 0 , then this pin is PCI_STOP# input used in power management mode for synchronously stopping the all CPU clocks. 11 I/O If Mode* = 1 (default), then this pin is a PCICLK6 clock output. If Mode* = 0 , then this pin is CPU_STOP # and used in power management mode for synchronously stopping the all PCI clocks. PIN I/O CPUCLK1 PCICLK [ 1:4 ] FUNCTION PCICLK_F PCICLK5/ PCI_STOP# PCICLK6/ CPU_STOP# 5.3 I2C Control Interface SYMBOL FUNCTION 2 SDATA* 18 I/O Serial data of I C 2-wire control interface SDCLK* 17 IN Serial clock of I2C 2-wire control interface -4- Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A 5.4 Fixed Frequency Outputs SYMBOL PIN I/O FUNCTION SEL100/66# 16 IN CPU clock frequency select pin. IOAPIC REF2X / SEL48* 24 27 O I/O Provides 14.318 fixed frequency. 24/48MHz 48MHz/Mode* 14 13 O I/O Internal 250kΩ pull-up. Latched input for SEL48* at initial power up. SEL48*=1 , pin14 is 24MHz SEL48*=0 , pin14 is 48MHz Reference clock during normal operation. Frequency is set by the state of pin27 on power up. Internal 250kΩ pull-up. 48MHz output for USB during normal operation. Latched input for Mode* at initial power up. Mode* = 0 , then pin10 is PCI_STOP#, and pin11 is CPU_STOP#. Mode* = 1.(default), pin10 is PCICLK5 and pin11 is PCLCLK6. 5.5 Power Pins SYMBOL PIN FUNCTION VddCore 20 Power supply for core logic and PLL circuitry. Connect to 3.3V supply. VddP 9 Power supply for PCICLK_F and PCICLK 1:6. Connect to 3.3V supply. VddA 25 Power supply for IOAPIC output, Connect to 2.5V supply VddC 23 Power supply for CPUCLK _F and CPUCLK1. Connect to 2.5V supply. Vdd4 12 Power supply for 48mhz USB clock . Connect to 3.3V supply. VddR 26 Power supply for 14.318mhz ISA clock . Connect to 3.3V supply. VssC, VssP VssR, Vss4, 3, 15, 19, 28 -5- Circuit Ground. Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A 6.0 FREQUENCY SELECTION SEL100/66# CPUCLK_F, CPUCLK1 PCI 1 100MHz 33.3MHz 0 66.8MHz 33.3MHz 7.0 FUNTION DESCRIPTION 7.1 POWER MANAGEMENT FUNCTIONS All clocks can be individually enabled or disabled via the 2-wire control interface. On power up, external circuitry should allow 3 ms for the VCOs to stabilize prior to enabling clock outputs to assure correct pulse widths. When MODE=0, pins 10 and 11 are inputs (PCI_STOP#), (CPU_STOP#), when MODE=1, these functions are not available. A particular clock could be enabled as both the 2-wire serial control interface and one of these pins indicate that it should be enabled. The W83196S-14A may be disabled in the low state according to the following table in order to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop. The CPU and PCI clocks transform between running and stop by waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. CPU_STOP# PCI_STOP# CPUCLK1 PCICLK1:4 CPUCLK_F& PCICLK_F XTAL & VCOs 0 0 LOW LOW RUNNING RUNNING 0 1 LOW RUNNING RUNNING RUNNING 1 0 RUNNING LOW RUNNING RUNNING 1 1 RUNNING RUNNING RUNNING RUNNING -6- Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A 7.2 2-WIRE I2C CONTROL INTERFACE The clock generator is a slave I2C component which can be read back the data stored in the latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2wire control interface allows each clock output individually enabled or disabled. On power up, the W83196S-14A initializes with default register settings, and then it is optional to use the 2-wire control interface. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated. Byte writing starts with a start condition followed by 7-bit slave address and a write command bit [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to write to internal I2C registers after the string of data. The sequence order is as follows: Bytes sequence order for I2C controller : Clock Address A(6:0) & R/W Ack 8 bits dummy Command code Ack 8 bits dummy Byte count Ack Byte0,1,2... until Stop Ack Byte2, 3, 4... until Stop Set R/W to 1 when read back the data sequence is as follows : Clock Address A(6:0) & R/W Ack Byte 0 Ack Byte 1 7.3 SERIAL CONTROL REGISTERS The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After -7- Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. Register 0 to Register 2 are referred to the Winbond SDRAM buffer(W83178S) drivers. 7.3.1 Register 3: CPU Frequency Select Register (1 = Enable, 0 = Stopped) Bit 7 6 5 4 3 @PowerUp 0 0 0 0 0 Pin - 2 0 - 1-0 00 - Description SSEL3 ( Frequency table selection by software via I2C) SSEL2 ( Frequency table selection by software via I2C) SSEL1 ( Frequency table selection by software via I2C) SSEL0 ( Frequency table selection by software via I2C) 0 = Selection by SEL100/66# 1 = Selection by software I2C - Bit 6:4 and Register 7 Bit0 0 = ±0.5% center type 1 = ±0.75% center type Bit1 Bit0 (See FUNCTION TABLE) 0 0 Normal 0 1 Test Mode 1 0 Spread Spectrum enabled 1 1 Tristate (I) Default Frequency table selection by software via I2C SSEL3 SSEL2 SSEL1 SSEL0 CPU,SDRAM (MHz) PCI (MHz) REF2X (MHz) 0 0 0 0 68.5 34.25 14.318 0 0 0 1 75 37.5 14.318 0 0 1 0 83.3 41.6 14.318 0 0 1 1 66.8 33.4 14.318 0 1 0 0 103 34.25 14.318 0 1 0 1 112 37.3 14.318 0 1 1 0 133.3 33.3 14.318 0 1 1 1 100 33.3 14.318 1 0 0 0 124 31 14.318 1 0 0 1 129 32.25 14.318 1 0 1 0 138 34.5 14.318 1 0 1 1 143 35.75 14.318 1 1 0 0 148 37 14.318 1 1 0 1 153 38.25 14.318 1 1 1 0 155 38.75 14.318 -8- Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A 1 1 1 1 160 40 14.318 7.3.2 Register 4 : CPU , 48/24 MHz Clock Register (1 = Enable, 0 = Stopped) Bit @PowerUp Pin Description 7 0 - 6 1 14 5 0 - Reserved 4 0 - Reserved 3 0 - Reserved 2 1 21 1 0 - 0 1 22 Reserved 24/48 Mhz (Active / Inactive) CPUCLK1 (Active / Inactive) Reserved CPUCLK_F (Active / Inactive) 7.3.3 Register 5: PCI Clock Register (1 = Enable, 0 = Stopped) Bit @PowerUp Pin Description 7 1 4 PCICLK_F (Active / Inactive) 6 1 11 PCICLK6 (Active / Inactive) 5 1 10 PCICLK5 (Active / Inactive) 4 0 - Reserved 3 1 8 PCICLK4 (Active / Inactive) 2 1 7 PCICLK3 (Active / Inactive) 1 1 6 PCICLK2 (Active / Inactive) 0 1 5 PCICLK1 (Active / Inactive) 7.3.4 Register 6: IOAPIC and REF2X Clock Register ( 1 = Enable, 0 = Stopped ) Bit @PowerUp Pin 7 0 - Reserved 6 0 - Reserved 5 1 24 4 0 - Reserved 3 0 - Reserved 2 1-0 0 11 27 -9- Description IOAPIC (Active / Inactive) Reserved Bit1 Bit0 1 1 REF2X Drive strength 2X Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A 1 0 0 0 1 0 Drive strength 1X Drive strength 1X Tri-state 7.3.5 Register 7: Winbond Chip ID Bit @PowerUp Pin Description 7 0 - Chip ID 6 1 - Chip ID 5 1 - Chip ID 4 0 - Chip ID 3 0 - Chip ID 2 0 - Chip ID 1 1 - Chip ID 0 1 - Chip ID - 10 - Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A 8.0 SPECIFICATIONS 8.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). Symbol Parameter Rating Vdd , VIN Voltage on any pin with respect to GND - 0.5 V to + 7.0 V TSTG Storage Temperature - 65°C to + 150°C TB Ambient Temperature - 55°C to + 125°C TA Operating Temperature 0°C to + 70°C 8.2 AC CHARACTERISTICS VddR = VddCore = VddP = Vdd4 = 3.3V±5%, VddA = VddC = 2.5V±5% , TA = 0°C to +70°C Parameter Symbol Min Typ Max Units 45 50 55 % Measured at 1.5V 4 ns 15 pF Load Measured at 1.5V tSKEW 250 ps 15 pF Load Measured at 1.5V tCCJ 200 ps tJA 500 ps BWJ 500 KHz 0.4 1.6 ns 15 pF Load on CPU and PCI outputs Output Duty Cycle CPU to PCI Offset Skew PCI) (CPU-CPU), tOFF (PCI- Cycle to Cycle Jitter CPU 1 Test Conditions Absolute Jitter Jitter Spectrum 20 dB Bandwidth from Center Output Rise (0.4V ~ 2.0V) tTLH & Fall (2.0V ~0.4V) Time tTHL Overshoot/Undershoot Vover 0.7 1.5 V 22 Ω at source of 8 inch PCB run to 15 pF load VRBE 0.7 2.1 V Ring Back must not enter this Beyond Power Rails Ring Back Exclusion - 11 - Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A range. - 12 - Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A 8.3 DC CHARACTERISTICS VddR = VddCore = VddP = Vdd4 = 3.3V±5%, VddA = VddC = 2.5V±5% , TA = 0°C to +70°C Parameter Symbol Min Typ Max Units 0.8 Vdc Test Conditions Input Low Voltage VIL Input High Voltage VIH Input Low Current IIL -25 µA Input High Current IIH 10 µA VOL 50 mVdc CPU_F, CPU1 Vdc CPU_F, CPU1 Output Low Voltage 2.0 Vdc IOL = 1 mA Output High Voltage VOH 3.1 IOL 27 57 97 mA CPU_F,CPI1 20.5 53 139 mA PCI_F,PCI1:6 40 85 140 mA IOAPIC 50 74 152 mA REF2X 25 37 76 mA 48,24MHz 25 55 97 mA CPU_F,CPI1 31 55 189 mA PCI_F,PCI1:6 40 87 155 mA IOAPIC 54 88 188 mA REF2X 27 44 94 mA 48,24MHz IOH = -1mA Output Low Current Output High Current IOH - 13 - Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A 8.4 BUFFER CHARACTERISTICS 8.4.1 TYPE 1 BUFFER FOR CPUCLK_F and CPUCLK1 Parameter Symbol Min Pull-Up Current Min IOH(min) -27 Pull-Up Current Max IOH(max) Pull-Down Current Min IOL(min) Pull-Down Current Max IOL(max) Rise/Fall Time Min Between 0.4 V and 2.0 V TRF(min) Rise/Fall Time Max Between 0.4 V and 2.0 V TRF(max) Typ Max -27 27 0.4 1.6 Units Test Conditions mA Vout = 1.0 V mA Vout = 2.0V mA Vout = 1.2 V mA Vout = 0.3 V ns 10 pF Load ns 20 pF Load 8.4.2 TYPE 2 BUFFER FOR IOAPIC Parameter Symbol Pull-Up Current Min IOH(min) Pull-Up Current Max IOH(max) Pull-Down Current Min IOL(min) Pull-Down Current Max IOL(max) Rise/Fall Time Min Between 0.7 V and 1.7 V TRF(min) Rise/Fall Time Max Between 0.7 V and 1.7 V TRF(max) - 14 - Min Typ Max -29 28 0.4 1.8 Units Test Conditions mA Vout = 1.4 V mA Vout = 2.7V mA Vout = 1.0 V mA Vout = 0.2 V ns 10 pF Load ns 20 pF Load Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A 8.4.3 TYPE 3 BUFFER FOR REF2X, 24MHZ, 48MHZ Parameter Symbol Min Pull-Up Current Min IOH(min) -29 Pull-Up Current Max IOH(max) Pull-Down Current Min IOL(min) Pull-Down Current Max IOL(max) Rise/Fall Time Min Between 0.8 V and 2.0 V TRF(min) Rise/Fall Time Max TRF(max) Typ Max Units Test Conditions mA Vout = 1.0 V mA Vout = 3.135V mA Vout = 1.95 V mA Vout = 0.4 V ns 10 pF Load 4.0 ns 20 pF Load Max Units -23 29 1.0 Between 0.8 V and 2.0 V 8.4.4 TYPE 5 BUFFER FOR PCICLK(1:6,F) Parameter Symbol Min Pull-Up Current Min IOH(min) -33 Pull-Up Current Max IOH(max) Pull-Down Current Min IOL(min) Pull-Down Current Max IOL(max) Rise/Fall Time Min Between 0.8 V and 2.0 V TRF(min) Rise/Fall Time Max TRF(max) Typ -33 30 38 0.5 2.0 Test Conditions mA Vout = 1.0 V mA Vout = 3.135 V mA Vout = 1.95 V mA Vout = 0.4 V ns 15 pF Load ns 30 pF Load Between 0.8 V and 2.0 V - 15 - Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A 9.0 OPERATION OF DUAL FUCTION PINS Pin13 is dual function pins and are used for selecting different functions in this device (see Pin description). During power up, these pins are in input mode (see Fig1), therefore, and are considered input select pins. When Vdd reaches 2.5V, the logic level that is present on these pins are latched into their appropriate internal registers. Once the correct information are properly latched, these pins will change into output pins and will be pulled low by default. At the end of the power up timer (within 3 ms) outputs starts to toggle at the specified frequency. 2.5V #13 48/MODE* Output tri-state Vdd Output pull-low Within 3ms Input All other clocks Output tri-state Output Output pull-low Each of these pins are a large pull-up resistor ( 250 kΩ @3.3V ) inside. The default state will be logic 1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these dual function pins. Under these conditions, an external 10 kΩ resistor is recommended to be connected to Vdd if logic 1 is expected. The same 10 kΩ connection to ground if a logic 0 is desired. The 10 kΩ resistor should be place before the serious terminating resistor. Note that these logic will only be latched at initial power on. If optional EMI reducing capacitor are needed, they should be placed as close to the series terminating resistor as possible and after the series terminating resistor. These capacitor has typical values ranging from 4.7pF to 22pF. - 16 - Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A Vdd 10kΩ Series Terminating Resistor Device Pin Clock Trace EMI Reducing Cap 10kΩ Optional Ground Ground Programming Header Vdd Pad Ground Pad 10kΩ Device Pin Series Terminating Resistor Clock Trace EMI Reducing Cap Optional Ground - 17 - Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A 10.0 ORDERING INFORMATION Part Number Package Type Production Flow W83196S-14A 28 PIN SOP Commercial, 0°C to +70°C 11.0 HOW TO READ THE TOP MARKING W83196S-14A 28051234 814GBB 1st line: Winbond logo and the type number: W83196S-14A 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; A means ASE, S means SPIL, G means GR BB: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 18 - Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A 12.0 PACKAGE DRAWING AND DIMENSIONS 28-SOP Headquarters Winbond Electronics (H.K.) Ltd. No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. - 19 - Publication Release Date: Mar. 1999 Revision 1.0 W83196S-14A - 20 - Publication Release Date: Mar. 1999 Revision 1.0