W83194R-81 100MHZ CLOCK FOR SIS CHIPSET 1.0 GENERAL DESCRIPTION The W83194R-81 is a Clock Synthesizer for SiS chipset. W83194R-81 provides all clocks required for high-speed RISC or CISC microprocessor such as AMD,Cyrix,Intel Pentium and also provides 16 different frequencies of CPU clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83194R-81 makes SDRAM in synchronous or asynchronous frequency with CPU clocks. The W83194R-81 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and W83194R-81 provides the 0.25%, 0.5% center type spread spectrum to reduce EMI. The W83194R-81 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate. 2.0 PRODUCT FEATURES • • • • • • • • Supports Pentium, Pentium Pro, AMD and Cyrix CPUs with I2C. 3 CPU clocks 13 SDRAM clocks for 3 DIMMs 6 PCI synchronous clocks. Optional single or mixed supply: (Vdd = Vddq4=Vddq3 = Vddq2b = 3.3V, Vddq2=2.5V) or (Vdd = Vddq4=Vddq3 = 3.3V, Vddq2=Vdq2b = 2.5V) Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns SDRAM frequency synchronous or asynchronous to CPU clocks Smooth frequency switch with selections from 66 to 133mhz(including 90MHz) I2C 2-Wire serial interface and I2C read back 0.25%, 0.5% center type spread spectrum to reduce EMI Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) MODE pin for power Management 48 MHz for USB 24 MHz for super I/O • 48-pin SSOP package • • • • • • -1- Publication Release Date: Dec. 1998 Revision 0.20 W83194R-81 PRELIMINARY 3.0 BLOCK DIAGRAM 48MHz PLL2 ¡Ò2 SIO SEL24_14# Xin Xout XTAL OSC 3 REF(0:2) IOAPIC PLL1 STOP Spread Spectrum *FS(0:2) 3 *MODE CPU3.3_2.5# *SD_SEL# CPUCLK(0:2) 3 CPU_STOP# LATCH 13 5 POR PCI clock Divder STOP 5 SDRAM(0:12) PCICLK(0:4) PCICLK_F SDRAM_STOP# CPU_STOP# PCI_STOP# PD# Contro l Logic *SDAT A*SCLK Config . Reg. PCI_STOP# 4.0 PIN CONFIGURATION Vdd REF0/ *MODE Vss Xin Xout Vddq4 PCICLK_F/ *FS1 PCICLK0/ *FS2 Vss PCICLK1 PCICLK2 PCICLK3 PCICLK4 Vddq4 SDRAM12 Vss *CPU_STOP#/SDRAM11 *PCI_STOP#/SDRAM10 Vddq3 *SDRAM_STOP#/SDRAM 9 *PD#/SDRAM 8 Vss *SDATA *SDCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 -2- Vddq2 IOAPIC REF1/ *SD_SEL# Vss REF2/CPU3.3_2.5# CPUCLK0 Vddq2b CPUCLK1 CPUCLK 2Vss SDRAM 0 SDRAM 1 Vddq3 SDRAM 2 SDRAM 3 Vss SDRAM 4 SDRAM 5 Vddq3 SDRAM 6 SDRAM 7 Vss 48MHz/*FS0 SIO/*SEL24_14# Publication Release Date: Dec. 1998 Revision 0.20 W83194R-81 PRELIMINARY 5.0 PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250kΩ pull-up 5.1 Crystal I/O SYMBOL PIN I/O Xin 4 IN Xout 5 OUT FUNCTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally. 5.2 CPU, SDRAM, PCI Clock Outputs SYMBOL PIN I/O FUNCTION CPUCLK [ 0:2 ] 40,41,43 OUT SDRAM11/ *CPU_STOP# 17 I/O SDRAM10/ *PCI_STOP# 18 I/O SDRAM9/ *SDRAM_STOP# 20 I/O SDRAM8/ *PD# 21 I/O SDRAM[0:7], SDRAM12 PCICLK_F/ *FS1 28,29,31,32,34 , 35,37,38,15 O Low skew (< 250ps) clock outputs for host frequencies such as CPU, Chipset and Cache. Vddq2b is the supply voltage for these outputs. If MODE =1 (default), then this pin is a SDRAM clock buffered output of the crystal. If MODE = 0 , then this pin is CPU_STOP# input used in power management mode for synchronously stopping the all CPU clocks. If MODE = 1 (default), then this pin is a SDRAM clock output. If MODE = 0 , then this pin is PCI_STOP # and used in power management mode for synchronously stopping the all PCI clocks. If MODE = 1 (default), then this pin is a SDRAM clock output. If MODE = 0 , then this pin is SDRAM_STOP # and used in power management mode for stopping the all SDRAM clocks. If MODE = 1 (default), then this pin is a SDRAM clock output. If MODE = 0 , then this pin is PD # and used to power down the device into a power down state. SDRAM clock outputs which have the same frequency as CPU clocks. 7 I/O -3- Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Free running PCI clock during normal operation. Publication Release Date: Dec. 1998 Revision 0.20 W83194R-81 PRELIMINARY 5.2 CPU, SDRAM, PCI Clock Outputs, continued SYMBOL PCICLK 0 / *FS2 PIN I/O 8 I/O FUNCTION Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. PCI clock during normal operation. PCICLK [ 1:4 ] 10,11,12,13 OUT Low skew (< 250ps) PCI clock outputs. 5.3 I2C Control Interface SYMBOL PIN I/O FUNCTION 2 *SDATA 23 I/O Serial data of I C 2-wire control interface *SDCLK 24 IN Serial clock of I2C 2-wire control interface 5.4 Fixed Frequency Outputs SYMBOL PIN I/O IOAPIC REF0 / *MODE 47 2 O I/O REF1 /*SD_SEL# 46 I/O REF2 / CPU3.3#_2.5 44 I/O SIO / *SEL24_14# 25 I/O 48MHz / *FS0 26 I/O -4- FUNCTION 2.5V fixed 14.318MHz 3.3V, 14.318MHz reference clock output. Internal 250kΩ pull-up. Function select pin. 3.3V, 14.318MHz reference clock output Internal 250kΩ pull-up. Latched input at Power On selects the frequencies for clock outputs. Internal 250kΩ pull-up. Latched input for CPU3.3#_2.5 at initial power up. Reference clock during normal operation. Latched high - Vddq2b = 2.5V Latched low - Vddq2b = 3.3V *SEL24_14# controls the frequency of SIO. If logic 0 at power on, SIO=14.318. If logic 1, SIO=24MHz for super I/O. Internal 250kΩ pull-up. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 48MHz output for USB during normal operation. Publication Release Date: Dec. 1998 Revision 0.20 W83194R-81 PRELIMINARY 5.5 Power Pins SYMBOL PIN FUNCTION Vdd 1 Power supply for REF0 crystal and core logic. Vddq2 48 Power supply for REF1,IOAPIC output, 2.5V. Vddq2b 42 Power supply for REF2, CPUCLK[0:2], either 2.5V or 3.3V. Vddq3 19, 30, 36 Vddq4 6,14 Vss 3,9,16,22,27, 33,39,45 Power supply for SDRAM and 48/24MHz outputs. Power supply for PCICLK outputs. Circuit Ground. 6.0 FREQUENCY SELECTION BY HARDWARE SD_SEL FS2 FS1 FS0 CPU SDRAM (MHz) (MHz) PCI (MHz) REF (MHz) IOAPIC 0 0 0 0 66.70 100.05 33.35 14.318 0 0 0 1 90 90 30 14.318 0 0 1 0 95.25 63.4 31.7 14.318 0 0 1 1 100.2 66.8 33.4 14.318 0 1 0 0 100 75 30 14.318 0 1 0 1 112 74.7 37.3 14.318 0 1 1 0 124 82.7 31 14.318 0 1 1 1 133.3 88.9 33.3 14.318 1 0 0 0 66.8 66.8 33.4 14.318 1 0 0 1 75 75 30 14.318 1 0 1 0 83.3 83.3 33.32 14.318 1 0 1 1 95.25 95.25 31.7 14.318 1 1 0 0 100.2 100.2 33.4 14.318 1 1 0 1 112 112 37.3 14.318 1 1 1 0 124 124 31 14.318 1 1 1 1 133.3 133.3 33.3 14.318 -5- Publication Release Date: Dec. 1998 Revision 0.20 W83194R-81 PRELIMINARY 7.0 CPU 3.3#_2.5 BUFFER SELECTION CPU 3.3#_2.5 ( Pin 44 ) Input Level CPU Operate at 1 VDD = 2.5V 0 VDD = 3.3V -6- Publication Release Date: Dec. 1998 Revision 0.20 W83194R-81 PRELIMINARY 8.0 FUNTION DESCRIPTION 8.1 POWER MANAGEMENT FUNCTIONS All clocks can be individually enabled or disabled via the 2-wire control interface. On power up, external circuitry should allow 3 ms for the VCO to stabilize prior to enabling clock outputs to assure correct pulse widths. When MODE=0, pins 17, 18, 20 and 21 are inputs (PCI_STOP#), (CPU_STOP#), (SDRAM_STOP#), (PD#). when MODE=1, these functions are not available. A particular clock could be enabled as both the 2-wire serial control interface and one of these pins indicate that it should be enabled. The W83194R-81 may be disabled in the low state according to the following table in order to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop. The CPU and PCI clocks transform between running and stop by waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. MODE PIN-POWER MANAGEMENT INPUT MODE(Pin2) Pin17 Pin18 Pin20 Pin21 0 (Input) CPU_STOP# PCI_STOP# SDRAM_STOP# PD# 1 (Output) SDRAM11 SDRAM10 SDRAM9 SDRAM8 PD# CPU_STOP# PCI_STOP# SDRAM _STOP# PCI [0:4] SDRAM [0:12] CPU[1:2] XTAL & VCOs 0 X X X Low Low Low Low 1 X X X Running Running Running Running 1 1 1 1 Running Running Running Running 1 1 1 0 Running Running Running Running 1 1 0 1 Low Running Running Running 1 1 0 0 Low Low Running Running 1 0 1 1 Running Running Low Running 1 0 1 0 Running Low Low Running 1 0 0 1 Low Running Low Running 1 0 0 0 Low Low Low Running -7- Publication Release Date: Dec. 1998 Revision 0.20 W83194R-81 PRELIMINARY 8.2 2-WIRE I2C CONTROL INTERFACE The clock generator is a slave I2C component which can be read back the data stored in the latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. On power up, the W83194R-81 initializes with default register settings, and then it optional to use the 2-wire control interface. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated. Byte writing starts with a start condition followed by 7-bit slave address [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to write to internal I2C registers after the string of data. The sequence order is as follows: Bytes sequence order for I2C controller : Clock Address A(6:0) & R/W Ack 8 bits dummy Command code Ack 8 bits dummy Byte count Ack Byte0,1,2... until Stop Set R/W to 1 when read back the data sequence is as follows, [1101 0011] : Clock Address A(6:0) & R/W Ack Byte 0 Ack Byte 1 Ack Byte2, 3, 4... until Stop 8.3 SERIAL CONTROL REGISTERS The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. -8- Publication Release Date: Dec. 1998 Revision 0.20 W83194R-81 PRELIMINARY 8.3.1 Register 0: CPU Frequency Select Register Bit 7 @PowerUp 0 Pin - 6 5 4 3 0 0 0 0 - 2 1 0 0 - 0 0 - Description 0 = ¡Ó0.25% Spread Spectrum Modulation 1 = ¡Ó0.5% Spread Spectrum Modulation SSEL2 ( Frequency table selection by software via I2C) 2 SSEL1 ( Frequency table selection by software via I C) SSEL0 ( Frequency table selection by software via I2C) 0 = Selection by hardware 1 = Selection by software I2C - Bit 6:4 and Bit2 SSEL3 (Frequency table selection by software via I2C ) 0 = Normal 1 = Spread Spectrum enabled 0 = Running 1 = Tristate all outputs Frequency table selection by software via I2C SSEL3 SSEL2 SSEL1 SSEL0 CPU SDRAM (MHz) (MHz) PCI (MHz) REF (MHz) IOAPIC 14.318 0 0 0 0 66.70 100.05 33.35 0 0 0 1 90 90 30 14.318 0 0 1 0 95.25 63.4 31.7 14.318 0 0 1 1 100.2 66.8 33.4 14.318 0 1 0 0 100 75 30 14.318 0 1 0 1 112 74.7 37.3 14.318 0 1 1 0 124 82.7 31 14.318 0 1 1 1 133.3 88.9 33.3 14.318 1 0 0 0 66.8 66.8 33.4 14.318 1 0 0 1 75 75 30 14.318 1 0 1 0 83.3 83.3 33.32 14.318 1 0 1 1 95.25 95.25 31.7 14.318 1 1 0 0 100.2 100.2 33.4 14.318 1 1 0 1 112 112 37.3 14.318 1 1 1 0 124 124 31 14.318 1 1 1 1 133.3 133.3 33.3 14.318 -9- Publication Release Date: Dec. 1998 Revision 0.20 W83194R-81 PRELIMINARY 8.3.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive) Bit @PowerUp Pin Description 7 1 - Reserved 6 1 - Reserved 5 1 - Reserved 4 1 - Reserved 3 1 40 CPUCLK2 (Active / Inactive) 2 1 41 CPUCLK1 (Active / Inactive) 1 1 43 CPUCLK0 (Active / Inactive) 0 - - Latched FS0# 8.3.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive) Bit @PowerUp Pin Description 7 - - Latched FS1# 6 1 7 PCICLK_F (Active / Inactive) 5 1 - Reserved 4 1 13 PCICLK4 (Active / Inactive) 3 1 12 PCICLK3 (Active / Inactive) 2 1 11 PCICLK2 (Active / Inactive) 1 1 10 PCICLK1 (Active / Inactive) 0 1 8 PCICLK0 (Active / Inactive) 8.3.4 Register 3: SDRAM Clock Register (1 = Active, 0 = Inactive) Bit @PowerUp Pin Description 7 1 28 SDRAM7 (Active / Inactive) 6 1 29 SDRAM6 (Active / Inactive) 5 1 31 SDRAM5 (Active / Inactive) 4 1 32 SDRAM4 (Active / Inactive) 3 1 34 SDRAM3 (Active / Inactive) 2 1 35 SDRAM2 (Active / Inactive) 1 1 37 SDRAM1 (Active / Inactive) 0 1 38 SDRAM0 (Active / Inactive) - 10 - Publication Release Date: Dec. 1998 Revision 0.20 W83194R-81 PRELIMINARY 8.3.5 Register 4: Additional SDRAM Clock Register (1 = Active, 0 = Inactive) Bit @PowerUp Pin Description 7 1 - 6 1 25 24/14MHz(Active / Inactive) 5 1 26 48MHz(Active / Inactive) 4 1 15 SDRAM12 (Active / Inactive) 3 1 17 SDRAM11 (Active / Inactive) 2 1 18 SDRAM10 (Active / Inactive) 1 1 20 SDRAM9 (Active / Inactive) 0 1 21 SDRAM8 (Active / Inactive) Reserved 8.3.6 Register 5: Peripheral Control (1 = Active, 0 = Inactive) Bit @PowerUp Pin Description 7 1 - Reserved 6 - - Latched FS2# 5 1 - Reserved 4 1 47 3 - - 2 1 44 REF2 (Active / Inactive) 1 1 46 REF1 (Active / Inactive) 0 1 2 REF0 (Active / Inactive) IOAPIC (Active / Inactive) Latched SD_SEL 8.3.7 Register 6: Winbond Chip ID Register (Read Only) Bit @PowerUp Pin Description 7 0 - Winbond Chip ID 6 1 - Winbond Chip ID 5 0 - Winbond Chip ID 4 1 - Winbond Chip ID 3 0 - Winbond Chip ID 2 1 - Winbond Chip ID 1 0 - Winbond Chip ID 0 0 - Winbond Chip ID - 11 - Publication Release Date: Dec. 1998 Revision 0.20 W83194R-81 PRELIMINARY 9.0 SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). Symbol Parameter Rating Vdd , VIN Voltage on any pin with respect to GND - 0.5 V to + 7.0 V TSTG Storage Temperature - 65°C to + 150°C TB Ambient Temperature - 55°C to + 125°C TA Operating Temperature 0°C to + 70°C 9.2 AC CHARACTERISTICS Vddq4 = Vdd = Vddq3 = 3.3V ± 5 %, Vddq2=Vddq2b = 2.375V~2.9V , TA = 0°C to +70°C Parameter Symbol Output Duty Cycle Min Typ Max Units 45 50 55 % Measured at 1.5V 4 ns 15 pF Load Measured at 1.5V 15 pF Load Measured at 1.5V CPU/SDRAM to PCI Offset tOFF Skew (CPU-CPU), (PCIPCI), (SDRAM-SDRAM) tSKEW 250 ps tCCJ ¡Ó250 ps tJA 500 ps BWJ 500 KHz 1.6 ns 15 pF Load on CPU and PCI outputs CPU/SDRAM 1 Test Conditions Cycle to Cycle Jitter CPU/SDRAM Absolute Jitter Jitter Spectrum 20 dB Bandwidth from Center Output Rise (0.4V ~ 2.0V) tTLH 0.4 & Fall (2.0V ~0.4V) Time tTHL Overshoot/Undershoot Vover 1.5 V 22 Ω at source of 8 inch PCB run to 15 pF load VRBE 2.1 V Ring Back must not enter this range. Beyond Power Rails Ring Back Exclusion - 12 - Publication Release Date: Dec. 1998 Revision 0.20 W83194R-81 PRELIMINARY 9.3 DC CHARACTERISTICS Vddq4 = Vdd = Vddq3 = 3.3V ± 5 %, Vddq2=Vddq2b = 2.375V~2.9V , TA = 0°C to +70°C Parameter Symbol Min Typ Max Units 0.8 Vdc Test Conditions Input Low Voltage VIL Input High Voltage VIH Input Low Current IIL -66 µA Input High Current IIH 5 µA Output Low Voltage VOL 0.4 Vdc All outputs Vdc All outputs using 3.3V power 2.0 Vdc IOL = 4 mA Output High Voltage VOH 2.4 IOH = 4mA Tri-State leakage Current Ioz Dynamic Supply Current Idd3 10 µA mA PCI = 33.3 Mhz with load for Vdd + Vddq3 Dynamic Supply Current CPU = 66.6 MHz Idd2 mA Same as above ICPUS3 mA Same as above ICPUS2 mA Same as above IPD3 mA for Vddq2 + Vddq2b CPU Stop Current for Vdd + Vddq3 CPU Stop Current for Vddq2 + Vddq2b PCI Stop Current for Vdd + Vddq3 - 13 - Publication Release Date: Dec. 1998 Revision 0.20 W83194R-81 PRELIMINARY 9.4 BUFFER CHARACTERISTICS 9.4.1 TYPE 1 BUFFER FOR CPU (0:2) Parameter Symbol Min Pull-Up Current Min IOH(min) -27 Pull-Up Current Max IOH(max) Pull-Down Current Min IOL(min) Pull-Down Current Max IOL(max) Rise/Fall Time Min Between 0.4 V and 2.0 V TRF(min) Rise/Fall Time Max Between 0.4 V and 2.0 V TRF(max) Typ Max -27 27 0.4 1.6 Units Test Conditions mA Vout = 1.0 V mA Vout = 2.0V mA Vout = 1.2 V mA Vout = 0.3 V ns 10 pF Load ns 20 pF Load 9.4.2 TYPE 2 BUFFER FOR IOAPIC Parameter Symbol Pull-Up Current Min IOH(min) Pull-Up Current Max IOH(max) Pull-Down Current Min IOL(min) Pull-Down Current Max IOL(max) Rise/Fall Time Min Between 0.7 V and 1.7 V TRF(min) Rise/Fall Time Max Between 0.7 V and 1.7 V TRF(max) Min Typ Max -29 28 0.4 1.8 - 14 - Units Test Conditions mA Vout = 1.4 V mA Vout = 2.7V mA Vout = 1.0 V mA Vout = 0.2 V ns 10 pF Load ns 20 pF Load Publication Release Date: Dec. 1998 Revision 0.20 W83194R-81 PRELIMINARY 9.4.3 TYPE 3 BUFFER FOR REF(0:2), 24MHZ, 48MHZ Parameter Symbol Min Pull-Up Current Min IOH(min) -29 Pull-Up Current Max IOH(max) Pull-Down Current Min IOL(min) Pull-Down Current Max IOL(max) Rise/Fall Time Min Between 0.8 V and 2.0 V TRF(min) Rise/Fall Time Max TRF(max) Typ Max Units Test Conditions mA Vout = 1.0 V mA Vout = 3.135V mA Vout = 1.95 V mA Vout = 0.4 V ns 10 pF Load 4.0 ns 20 pF Load Max Units -23 29 1.0 Between 0.8 V and 2.0 V 9.4.4 TYPE 4 BUFFER FOR SDRAM(0:12) Parameter Symbol Pull-Up Current Min IOH(min) Pull-Up Current Max IOH(max) Pull-Down Current Min IOL(min) Pull-Down Current Max IOL(max) Rise/Fall Time Min Between 0.8 V and 2.0 V TRF(min) Rise/Fall Time Max TRF(max) Min Typ Test Conditions mA Vout = 1.65V mA Vout = 3.135V mA Vout = 1.65 V mA Vout = 0.4 V ns 20 pF Load 1.3 ns 30 pF Load Max Units -46 53 0.5 Between 0.8 V and 2.0 V 9.4.5 TYPE 5 BUFFER FOR PCICLK(0:4, F) Parameter Symbol Min Pull-Up Current Min IOH(min) -33 Pull-Up Current Max IOH(max) Pull-Down Current Min IOL(min) Pull-Down Current Max IOL(max) Rise/Fall Time Min Between 0.8 V and 2.0 V TRF(min) Rise/Fall Time Max TRF(max) Typ -33 30 38 0.5 2.0 Test Conditions mA Vout = 1.0 V mA Vout = 3.135 V mA Vout = 1.95 V mA Vout = 0.4 V ns 15 pF Load ns 30 pF Load Between 0.8 V and 2.0 V - 15 - Publication Release Date: Dec. 1998 Revision 0.20 W83194R-81 PRELIMINARY 10.0 POWER MANAGEMENT TIMING 10.1 CPU_STOP# Timing Diagram CPUCLK (Internal) 1 2 1 2 PCICLK (Internal) PCICLK_F CPU_STOP# CPUCLK[0:3] SDRAM For synchronous Chipset, CPU_STOP# pin is a synchronous “active low ”input pin used to stop the CPU clocks for low power operation. This pin is asserted synchronously by the external control logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume output with full pulse width. In this case, CPU locks on latency“ is less than 2 CPU clocks and locks off latency is less then 2 CPU clocks. 10.2 PCI_STOP# Timing Diagram CPUCLK (Internal) PCICLK (Internal) 1 1 2 2 PCICLK_F PCI_STOP# PCICLK[0:4] For synchronous Chipset, PCI_STOP# pin is a synchronous ctive low” input pin used to stop the PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output with full pulse width. In this case, PCI locks on latency“ is less than 1 PCI clocks and locks off latency is less then 1 PCI clocks. - 16 - Publication Release Date: Dec. 1998 Revision 0.20 W83194R-81 PRELIMINARY 11.0 ORDERING INFORMATION Part Number Package Type Production Flow W83194R-81 48 PIN SSOP Commercial, 0°C to +70°C 12.0 HOW TO READ THE TOP MARKING W83194R-81 28051234 814GBB 1st line: Winbond logo and the type number: W83194R-81 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; A means ASE, S means SPIL, G means GR BB: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 17 - Publication Release Date: Dec. 1998 Revision 0.20 W83194R-81 PRELIMINARY 13.0 PACKAGE DRAWING AND DIMENSIONS Headquarters Winbond Electronics (H.K.) Ltd. No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. - 18 - Publication Release Date: Dec. 1998 Revision 0.20