TI SN74ACT7882

SN74ACT7882
2048 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445C – JUNE 1994 – REVISED APRIL 1998
D
D
D
D
D
Member of the Texas Instruments
Widebus Family
Independent Asynchronous Inputs and
Outputs
Read and Write Operations Can Be
Synchronized to Independent System
Clocks
Programmable Almost-Full/Almost-Empty
Flag
Pin-to-Pin Compatible With SN74ACT7881
and SN74ACT7811
D
D
D
D
D
Input-Ready, Output-Ready, and Half-Full
Flags
Cascadable in Word Width and/or Word
Depth (See Application Information)
Fast Access Times of 11 ns With a 50-pF
Load
High Output Drive for Direct Bus Interface
Package Options Include 68-Pin Plastic
Leaded Chip Carriers (FN) or 80-Pin Shrink
Quad Flat (PN) Package
D15
D16
D17
GND
RDCLK
RDEN1
RDEN2
OE
RESET
VCC
GND
OR
VCC
Q17
Q16
GND
Q15
FN PACKAGE
(TOP VIEW)
9
10
8 7
6
5 4 3 2 1 68 67 66 65 64 63 62 61
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
VCC
Q14
Q13
GND
Q12
Q11
VCC
Q10
Q9
GND
Q8
Q7
VCC
Q6
Q5
GND
Q4
Q0
Q1
GND
Q2
Q3
V CC
AF/AE
GND
IR
HF
V CC
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DAF
GND
WRTCLK
WRTEN1
WRTEN2
V CC
D14
D13
D12
D11
D10
D9
VCC
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ACT7882
2048 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445C – JUNE 1994 – REVISED APRIL 1998
GND
GND
Q4
Q14
Q13
GND
GND
Q12
Q11
VCC
Q10
Q9
GND
Q8
Q7
VCC
Q6
Q5
Q15
VCC
PN PACKAGE
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VCC
VCC
NC
Q3
Q2
GND
Q1
Q0
VCC
HF
IR
GND
GND
AF/AE
VCC
WRTEN2
WRTEN1
WRTCLK
GND
NC
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
DAF
NC
1
NC
D14
D13
D12
D11
D10
D9
VCC
NC
GND
GND
Q16
Q17
VCC
OR
GND
VCC
RESET
OE
RDEN2
RDEN1
RDCLK
GND
D17
D16
D15
NC
NC
NC – No internal connection
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT7882 is organized as 2048 bits deep × 18 bits wide. The SN74ACT7882 processes
data at rates up to 67 MHz and access times of 11 ns in a bit-parallel format. Data outputs are noninverting with
respect to the data inputs. Expansion is accomplished easily in both word width and word depth.
The SN74ACT7882 has normal input-bus to output-bus asynchronous operation. The special enable circuitry
adds the ability to synchronize independent reads and writes to their respective system clocks.
The SN74ACT7882 is characterized for operation from 0°C to 70°C.
2
POST OFFICE BOX 655303
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SN74ACT7882
2048 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445C – JUNE 1994 – REVISED APRIL 1998
logic symbol†
Φ
FIFO
SN74ACT7882 – 2048 × 18
RESET
WRTCLK
WRTEN1
WRTEN2
RDCLK
RDEN1
OE
RDEN2
DAF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
1
RESET
29
WRTCLK
30
&
31
5
WRTEN
RDCLK
4
2
IN RDY
HALF FULL
ALMOST FULL/EMPTY
OUT RDY
&
EN1
35
36
33
66
IR
HF
AF/AE
OR
RDEN
3
27
26
DEF ALMOST FULL
0
0
38
25
39
24
41
23
42
22
44
21
46
20
47
19
49
17
Data
15
Data
50
1
52
14
53
13
55
12
56
11
58
10
59
9
61
8
63
7
64
17
17
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the FN package.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74ACT7882
2048 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445C – JUNE 1994 – REVISED APRIL 1998
functional block diagram
OE
D0–D17
RDCLK
RDEN1
RDEN2
Synchronous
Read
Control
Location 1
Location 2
Read
Pointer
RAM
2048 × 18
WRTCLK
WRTEN1
WRTEN2
Synchronous
Write
Control
Write
Pointer
•
•
Register
Reset Logic
Q0–Q17
RESET
OR
StatusFlag
Logic
DAF
IR
HF
AF/AE
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ACT7882
2048 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445C – JUNE 1994 – REVISED APRIL 1998
Terminal Functions†
TERMINAL
NAME
NO.
I/O
DESCRIPTION
Almost-full/almost-empty flag. The AF/AE boundary is defined by the AF/AE offset value (X). This
value can be programmed during reset or the default value of 256 can be used. AF/AE is high when
the number of words in memory is less than or equal to X. AF/AE also is high when the number of words
in memory is greater than or equal to (2048 – X).
Programming the AF/AE offset value (X) is accomplished during a reset cycle. The AF/AE offset value
(X) is either user-defined or the default value of X = 256. The procedure to program AF/AE is as follows:
AF/AE
33
User-defined X
Step 1: Take DAF from high to low. The high-to-low transition of DAF input stores the binary value
on the data inputs as X. The following bits are used, listed from most significant bit to least significant
bit D9–D0.
Step 2: If RESET is not already low, take RESET low.
Step 3: With DAF held low, take RESET high. This defines the AF/AE using X.
NOTE: To retain the current (X) offset, keep DAF low during subsequent reset cycles.
O
Default X
To redefine AF/AE using the default value of X = 256, hold DAF high during the reset cycle.
DAF
D0–D17
HF
27
I
Define almost-full. The high-to-low transition of DAF stores the binary value of data inputs as the AF/AE
offset value (X). With DAF held low, a RESET cycle defines the AF/AE flag using X.
26–19, 17,
15–7
I
Data inputs for 18-bit-wide data to be stored in the memory. A high-to-low transition on DAF captures
data for the almost-empty/almost-full offset (X) from D9–D0.
36
O
Half-full flag. HF is high when the FIFO contains 1024 or more words and is low when the number of
words in memory is less than half the depth of the FIFO.
IR
35
O
Input-ready flag. IR is high when the FIFO is not full and low when the device is full. During reset, IR
is driven low on the rising edge of the second WRTCLK pulse. IR then is driven high on the rising edge
of the second WRTCLK pulse after RESET goes high. After the FIFO is filled and IR is driven low, IR
is driven high on the second WRTCLK pulse after the first valid read.
OE
2
I
Output enable. The Q0–Q17 outputs are in the high-impedance state when OE is low. OE must be high
before the rising edge of RDCLK to read a word from memory.
66
O
Output-ready flag. OR is high when the FIFO is not empty and low when it is empty. During reset, OR
is set low on the rising edge of the third RDCLK pulse. OR is set high on the rising edge of the third
RDCLK pulse to occur after the first word is written into the FIFO. OR is set low on the rising edge of
the first RDCLK pulse after the last word is read.
Q0–Q17
38–39, 41–42,
44, 46–47,
49–50, 52–53,
55–56, 58–59,
61, 63–64
O
Data out. The first data word to be loaded into the FIFO is moved to Q0–Q17 on the rising edge of the
third RDCLK pulse to occur after the first valid write. RDEN1 and RDEN2 do not affect this operation.
Following data is unloaded on the rising edge of RDCLK when RDEN1, RDEN2, OE, and OR are high.
RDCLK
5
I
Read clock. Data is read out of memory on the low-to-high transition at RDCLK if OR, OE, and RDEN1
and RDEN2 are high. RDCLK is a free-running clock and functions as the synchronizing clock for all
data transfers out of the FIFO. OR also is driven synchronously with respect to RDCLK.
RDEN1
RDEN2
4
3
I
Read enable. RDEN1 and RDEN2 must be high before a rising edge on RDCLK to read a word out
of memory. RDEN1 and RDEN2 are not used to read the first word stored in memory.
OR
RESET
1
I
Reset. A reset is accomplished by taking RESET low and generating a minimum of four RDCLK and
WRTCLK cycles. This ensures that the internal read and write pointers are reset and that OR, HF, and
IR are low, and AF/AE is high. The FIFO must be reset upon power up. With DAF at a low level, a low
pulse on RESET defines AF/AE using the AF/AE offset value (X), where X is the value previously
stored. DAF held high during a RESET cycle defines the AF/AE flag using the default value of X = 256.
WRTCLK
29
I
Write clock. Data is written into memory on a low-to-high transition of WRTCLK if IR, WRTEN1, and
WRTEN2 are high. WRTCLK is a free-running clock and functions as the synchronizing clock for all
data transfers into the FIFO. IR also is driven synchronously with respect to WRTCLK.
WRTEN1
WRTEN2
30
31
I
Write enable. WRTEN1 and WRTEN2 must be high before a rising edge on WRTCLK for a word to
be written into memory. WRTEN1 and WRTEN2 do not affect the storage of the AF/AE offset value (X).
† Terminals listed are for the FN package.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN74ACT7882
2048 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445C – JUNE 1994 – REVISED APRIL 1998
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RESET
Don’t Care
DAF
1
WRTCLK
WRTEN1
Don’t Care
WRTEN2
Don’t Care
D0–D17
Don’t Care
1
RDCLK
2
3
Don’t Care
RDEN2
Don’t Care
1
2
X†
2
RDEN1
4
3
4
OE
Invalid
Q0–Q17
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Invalid
OR
AF/AE
Invalid
HF
Invalid
Invalid
IR
Store the Value of Data as X
† X is the binary value on D9–D0.
Define the AF/AE Flag
Using the Value of X
Figure 1. Reset Cycle: Define AF/AE Using a Programmed Value of X
6
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• DALLAS, TEXAS 75265
SN74ACT7882
2048 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445C – JUNE 1994 – REVISED APRIL 1998
RESET
DAF
WRTCLK
WRTEN1
WRTEN2
D0–D17
RDCLK
RDEN1
RDEN2
OE
Q0–Q17
OR
AF/AE
HF
IR
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Don’t Care
1
2
3
4
1
2
Don’t Care
Don’t Care
Don’t Care
1
2
3
4
Don’t Care
Don’t Care
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Invalid
Invalid
Invalid
Invalid
Define the AF/AE Flag Using
the Default Value of X = 256
Figure 2. Reset Cycle: Define AF/AE Using the Default Value
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN74ACT7882
2048 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445C – JUNE 1994 – REVISED APRIL 1998
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RESET
Don’t Care
DAF
WRTCLK
WRTEN1
WRTEN2
D0–D17
RDCLK
W1
W2
W3
W4
1
2
3
W(X+2)
A
B
RDEN1
RDEN2
OE
Q0–Q17
Invalid
W1
OR
AF/AE
HF
IR
DATA-WORD NUMBERS FOR FLAG TRANSITIONS
TRANSITION WORD
A
B
C
W1025
W(2049 – X)
W20495
Figure 3. Write
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
C
SN74ACT7882
2048 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445C – JUNE 1994 – REVISED APRIL 1998
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RESET
Don’t Care
DAF
WRTCLK
1
2
WRTEN1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
WRTEN2
D0–D17
F
RDCLK
RDEN1
RDEN2
OE
Q0–Q17
W1
W1
W2
W3
W(X+1)
W(X+2)
A
B
C
D
E
F
OR
AF/AE
HF
IR
DATA-WORD NUMBERS FOR FLAG TRANSITIONS
TRANSITION WORD
A
B
C
D
E
F
W1025
W1030
W(2048 – X)
W(2049 – X)
W2048
W2049
Figure 4. Read
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SN74ACT7882
2048 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445C – JUNE 1994 – REVISED APRIL 1998
absolute maximum ratings over operating free-air temperature range†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Package thermal impedance, θJA (see Note 1): FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
PN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN
MAX
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
V
High-level output current
–8
mA
IOL
TA
Low-level output current
16
mA
70
°C
High-level input voltage
2
Operating free-air temperature
0
V
V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
VOL
VCC = 4.5 V,
VCC = 4.5 V,
IOH = –8 mA
IOL = 16 mA
II
IOZ
VCC = 5.5 V,
VCC = 5.5 V,
VI = VCC or 0
VO = VCC or 0
ICC§
VI = VCC – 0.2 V or 0
One input at 3.4 V,
Other inputs at VCC or GND
Ci
Co
VI = 0,
VO = 0,
POST OFFICE BOX 655303
TYP‡
MAX
2.4
UNIT
V
0.5
V
±5
µA
±5
µA
400
µA
1
mA
f = 1 MHz
4
pF
f = 1 MHz
8
pF
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ ICC is tested with outputs open.
10
MIN
• DALLAS, TEXAS 75265
SN74ACT7882
2048 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445C – JUNE 1994 – REVISED APRIL 1998
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 5)
’ACT7882-15
MIN
fclock
tw
tsu
th
MAX
Clock frequency
Pulse duration
Setup time
Hold time
’ACT7882-20
MIN
67
MAX
’ACT7882-30
MIN
50
MAX
33.4
WRTCLK high
5
7
8.5
WRTCLK low
6
7
11
RDCLK high
5
7
8.5
RDCLK low
6
7
11
DAF high (default AF/AE value)
7
8
10
Data in (D0–D17) before WRTCLK↑
5
5
5
WRTEN1, WRTEN2 high before WRTCLK↑
4
5
5
OE, RDEN1, RDEN2 high before RDCLK↑
4
5
5
Reset: RESET low before first WRTCLK↑
and RDCLK↑†
5
6
7
Define AF/AE: D0–D9 before DAF↓
5
5
5
Define AF/AE: DAF↓ before RESET↑
4
6
7
Define AF/AE (default): DAF high before RESET↑
4
5
5
Data in (D0–D17) after WRTCLK↑
0
0
0
WRTEN1, WRTEN2 high after WRTCLK↑
0
0
0
OE, RDEN1, RDEN2 high after RDCLK↑
0
0
1
Reset: RESET low after fourth WRTCLK↑
and RDCLK↑†
0
0
0
Define AF/AE: D0–D9 after DAF↓
0
0
0
Define AF/AE: DAF low after RESET↑
0
0
0
Define AF/AE (default): DAF high after RESET↑
0
0
0
UNIT
MHz
ns
ns
ns
† To permit the clock pulse to be utilized for reset purposes
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 5)
PARAMETER
FROM
(INPUT)
fmax
WRTCLK or RDCLK
tpd
tpd‡
RDCLK↑
Any Q
tpd
d
TO
(OUTPUT)
’ACT7882-15
MIN
MAX
67
’ACT7882-20
MIN
MAX
50
’ACT7882-30
MIN
MAX
33.4
MHz
3
12
3
13
3
18
8
2
9.5
2
12
RDCLK↑
Any Q
WRTCLK↑
IR
2
RDCLK↑
OR
2
8
2
9.5
2
12
6
17
6
19
6
22
6
17
6
19
6
22
WRTCLK↑
AF/AE
RDCLK↑
UNIT
ns
ns
tPLH
tPHL
WRTCLK↑
HF
6
14
6
17
6
21
ns
RDCLK↑
HF
6
14
6
17
6
21
ns
tPLH
RESET↓
AF/AE
3
12
3
17
3
21
ns
tPHL
RESET↓
HF
3
14
3
19
3
23
ns
OE
Any Q
2
9
2
11
2
11
ns
Any Q
2
10
2
14
2
14
ns
ten
tdis
OE
‡ This parameter is measured with CL = 30 pF (see Figure 6).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SN74ACT7882
2048 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445C – JUNE 1994 – REVISED APRIL 1998
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per 1K bits
CL = 50 pF,
TYP
f = 5 MHz
65
UNIT
pF
PARAMETER MEASUREMENT INFORMATION
7V
PARAMETER
S1
ten
500 Ω
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
tdis
tpd
500 Ω
S1
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
Open
Closed
Open
Closed
Open
Open
tw
LOAD CIRCUIT
3V
Input
Timing
Input
0V
VOLTAGE WAVEFORMS
PULSE DURATION
0V
th
3V
Data
Input
1.5 V
1.5 V
0V
3V
Output
Control
tPZL
3V
1.5 V
1.5 V
1.5 V
0V
tPLH
1.5 V
1.5 V
tPZH
1.5 V
VOL
Output
Waveform 2
S1 at Open
VOL + 0.3 V
1.5 V
VOH
VOH – 0.3 V
≈0V
NOTE A: CL includes probe and jig capacitance.
Figure 5. Load Circuit and Voltage Waveforms
• DALLAS, TEXAS 75265
VOL
tPHZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
POST OFFICE BOX 655303
tPLZ
≈ 3.5 V
Output
Waveform 1
S1 at 7 V
tPHL
VOH
12
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
1.5 V
1.5 V
tsu
Input
1.5 V
3V
SN74ACT7882
2048 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445C – JUNE 1994 – REVISED APRIL 1998
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
POWER-DISSIPATION CAPACITANCE
vs
SUPPLY VOLTAGE
18
68
t pd – Propagation Delay Time – ns
17
Cpd – Power Dissipation Capacitance – pF
VCC = 5 V,
RL = 500 Ω,
TA = 25°C
16
15
14
13
12
11
67
fi = 5 MHz,
TA = 25°C,
CL = 50 pF
66
65
64
63
62
10
0
50
100
150
200
250
300
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
VCC – Supply Voltage – V
CL – Load Capacitance – pF
Figure 6
Figure 7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SN74ACT7882
2048 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445C – JUNE 1994 – REVISED APRIL 1998
APPLICATION INFORMATION
expanding the SN74ACT7882
The SN74ACT7882 is expandable in both word width and word depth. Word-depth expansion is accomplished
by connecting the devices in series such that data flows through each device in the chain. Figure 8 shows two
SN74ACT7882 devices configured for depth expansion. The common clock between the devices can be tied
to either the write clock (WRTCLK) of the first device or the read clock (RDCLK) of the last device. The
output-ready (OR) flag of the previous device and the input-ready (IR) flag of the next device maintain data flow
to the last device in the chain whenever space is available.
Figure 9 is an example of two SN74ACT7882 devices in word-width expansion. Width expansion is
accomplished by simply connecting all common control signals between the devices and creating composite
IR and OR signals. The almost-full/almost-empty (AF/AE) flag and half-full (HF) flag can be sampled from any
one device. Depth expansion and width expansion can be used together.
CLOCK
SN74ACT7882
SN74ACT7882
WRTCLK
WRTEN1
WRTCLK
WRTEN1
RDCLK
OR
WRTCLK
WRTEN1
RDCLK
RDEN1
RDCLK
RDEN1
WRTEN2
IR
WRTEN2
IR
RDEN1
RDEN2
WRTEN2
IR
RDEN2
OR
RDEN2
OR
D0–D17
D0–D17
Q0–Q17
D0–D17
Q0–Q17
OE
OE
5V
OE
Q0–Q17
Figure 8. Word-Depth Expansion: 4096 × 18 Bits
SN74ACT7882
WRTCLK
WRTEN
WRTCLK
WRTEN1
RDCLK
RDEN1
WRTEN2
IR
RDEN2
OR
D0–D17
Q0–Q17
OE
D18–D35
IR
SN74ACT7882
RDCLK
RDEN
OE
Q18–Q35
OR
WRTCLK
WRTEN1
RDCLK
RDEN1
WRTEN2
IR
RDEN2
OR
OE
D0–D17
D0–D17
Q0–Q17
Figure 9. Word-Width Expansion: 2048 × 36 Bits
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Q0–Q17
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