TI TSL1401

× SOES029 − JUNE 1996
D 128 × 1 Sensor-Element Organization
D 400 Dots-Per-Inch (DPI) Sensor Pitch
D High Linearity and Uniformity
(TOP VIEW)
SI
CLK
AO
VDD
for 256 Gray-Scale (8-Bit) Applications
Output Referenced to Ground
Low Image Lag . . . 0.5% Typ
Operation to 2 MHz
Single 5-V Supply
D
D
D
D
1
8
2
7
3
6
4
5
NC
GND
GND
NC
NC − No internal connection
description
The TSL1401 linear sensor array consists of a 128 × 1 array of photodiodes, associated charge amplifier
circuitry, and a pixel data-hold function that provides simultaneous-integration start and stop times for all pixels.
The pixels measure 63.5 µm (H) by 55 µm (W) with 63.5-µm center-to-center spacing and 8.5-µm spacing
between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI) signal and
a clock.
functional block diagram
Pixel 1
Integrator
Reset
Pixel
2
Pixel
3
Pixel
128
VDD
Analog
Bus
4
Output
Amplifier
+
_
3
Sample/
Output
6,7
Switch Control Logic
Hold
CLK
SI
2
Q1
AO
RL
(External
Load)
Gain
Trim
Q2
Q3
Q128
128-Bit Shift Register
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1996, Texas Instruments Incorporated
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•
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•
1
× SOES029 − JUNE 1996
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
AO
3
Analog output
CLK
2
Clock. The clock controls charge transfer, pixel output, and reset.
GND
6, 7
Ground (substrate). All voltages are referenced to the substrate.
NC
5, 8
No internal connection
SI
1
Serial input. SI defines the start of the data-out sequence.
VDD
4
Supply voltage. Supply voltage for both analog and digital circuits.
detailed description
The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel.
During the integration period, a sampling capacitor connects to the output of the integrator through an analog
switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the
integration time.
The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle
is initiated by clocking in a logic 1 on SI. This causes all 128 sampling capacitors to be disconnected from their
respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift register,
the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output amplifier
that generates a voltage on analog output AO. The integrator reset period ends 18 clock cycles after the SI pulse
is clocked in. Then the next integration period begins.
AO is driven by a source follower that requires an external pulldown resistor. When the output is not in the output
phase, it is in a high-impedance state. The output is nominally 0 V for no light input and 2 V for a nominal full-scale
output.
The TSL1401 is intended for use in a wide variety of applications, including: image scanning, mark and code
reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and optical
linear and rotary encoding.
2
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× SOES029 − JUNE 1996
absolute maximum ratings†
Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Digital input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA to 20 mA
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to 85°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions (see Figure 1 and Figure 2)
Supply voltage, VDD
Input voltage, VI
MIN
NOM
MAX
4.5
5
5.5
V
VDD
VDD
V
0
VDD × 0.7
0
High-level input voltage, VIH
Low-level input voltage, VIL
Wavelength of light source, λ
Clock frequency, fclock
Sensor integration time, tint
Setup time, serial input, tsu(SI)
400
nm
5
2000
kHz
0.0645
100
ms
0
V
ns
20
Operating free-air temperature, TA
V
VDD × 0.3
700
0
Hold time, serial input, th(SI) (see Note 1)
UNIT
ns
70
°C
NOTE 1: SI must go low before the rising edge of the next clock pulse.
CLK
SI
Internal
Reset
18 Clock Cycles
Integration
Not Integrating
Integrating
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
128 Clock Cycles
AO
Hi-Z
Hi-Z
Figure 1. Timing Waveforms
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3
× SOES029 − JUNE 1996
electrical characteristics at fclock = 200 kHz, VDD = 5 V, TA = 25°C, λp = 565 nm, tint = 5 ms,
RL = 330 Ω, Ee = 14 µW/cm2 (unless otherwise noted) (see Note 2)
PARAMETER
TEST CONDITIONS
Analog output voltage (white, average over 128 pixels)
Analog output voltage (dark, average over 128 pixels)
PRNU
Pixel response nonuniformity
Ee = 0
See Note 3
Nonlinearity of analog output voltage
See Note 4
Output noise voltage
See Note 5
IL
Image lag
IDD
IIH
Supply current
IIL
Ci
Low-level input current
MAX
2
2.2
V
0.1
0.2
V
± 4%
± 7.5%
± 0.4%
136
175
mVrms
nJ/cm2
3
3.5
V
All pixels,
See Note 6
Ee = 0
0.08
0.120
All except pixel 1,
See Note 6
Ee = 0
0.017
0.035
See Note 7
V
0.5%
2.5
High-level input current
UNIT
FS
1
Analog output saturation voltage
Dark signal nonuniformity
TYP
1.8
0
Saturation exposure
DSNU
MIN
VI = VDD
VI = 0
Input capacitance
5
4
mA
1
µA
1
µA
pF
NOTES: 2. Clock duty cycle is assumed to be 50%.
3. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated.
4. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
5. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
6. DNSU is the difference between the maximum and minimum of dark-current voltage.
7. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
V
IL +
4
V
AO
–V
AO(dark)
* V AO(dark)
AO(white)
•
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•
× SOES029 − JUNE 1996
operating characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tw(H)
tw(L)
Clock pulse duration (high)
50
ns
Clock pulse duration (low)
50
ns
ts
Analog output settling time to ± 1%
tw
RL = 330 Ω,
1
2
128
CL = 50 pF
350
129
ns
5V
2.5 V
CLK
0V
tsu(SI)
SI
5V
50%
0V
th(SI)
ts
Pixel 1
Pixel 128
Figure 2. Operational Waveforms
TYPICAL CHARACTERISTICS
PHOTODIODE SPECTRAL RESPONSIVITY
1
TA = 25°C
0.8
Normalized Responsivity
AO
ts
0.6
0.4
0.2
0
300
400
500
700
600
800
900
1000 1100
λ − Wavelength − nm
Figure 3
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5
× SOES029 − JUNE 1996
APPLICATIONS INFORMATION
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated with an electrically
nonconductive clear plastic compound.
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
0.430 (10,92)
0.370 (9,40)
Pixel 4 is centered
horizontally on Pin 1
SI
CLK
AO
VDD
NC
GND
GND
NC
8
5
0.325 (8,26)
0.300 (7,62)
C
L (pixel)
C
L
0.017 (0,43)
0.260 (6,60)
0.240 (6,10)
0.075 (1,91)
0.040 (1,02)
0.030 (0,76) D NOM
1
0.065 (1,65)
0.200 (5,08) 0.045 (1,14)
0.155 (3,94)
15° TYP
4
0.020 (0,51) R NOM
4 Places
7° MAX TYP
0.075 (1,91)
0.040 (1,02)
Seating Plane
0.020 (0,51)
R MAX
4 Places
105°
90°
8 Places
0.012 (0,30)
0.008 (0,20)
0.050 (1,27)
0.020 (0,51)
0.060 (1,52)
0.015 (0,38)
0.300 (7,62)
T.P.†
0.065 (1,65)
0.045 (1,14)
† True position when unit is installed
NOTES: A. All linear dimensions are in inches and parenthetically in millimeters.
B. This drawing is subject ot change without notice.
Figure 4. Packaging Configuration
6
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•
0.150 (3,81)
0.125 (3,18)
0.022 (0,56)
0.014 (0,36)
0.100 (2,54) T.P.†
PACKAGE OPTION ADDENDUM
www.ti.com
2-Mar-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TSL1401
OBSOLETE
XCEPT
COB
Pins Package Eco Plan (2)
Qty
14
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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