XICOR X25021PI

X25021
X25021
2K
256 x 8 Bit
SPI Serial E2PROM with Block LockTM Protection
FEATURES
DESCRIPTION
•
•
•
The X25021 is a CMOS 2048-bit serial E2PROM, internally organized as 256 x 8. The X25021 features a Serial
Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
•
•
•
•
•
•
•
•
1MHz Clock Rate
SPI Modes (0,1 & 1,0)
256 X 8 Bits
—4 Byte Page Mode
Low Power CMOS
—10µA Standby Current
—3mA Active Current
2.7V To 5.5V Power Supply
Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM Array
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Latch
—Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
8-Lead PDlP Package
8-Lead SOIC Package
FUNCTIONAL DIAGRAM
STATUS
REGISTER
The X25021 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25021 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire input
to the X25021 disabling all write attempts, thus providing
a mechanism for limiting end user capability of altering
the memory.
The X25021 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
WRITE
PROTECT
LOGIC
X DECODE
LOGIC
256 BYTE
ARRAY
16
16 X 32
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
16
16 X 32
32
WP
32 X 32
WRITE
CONTROL
AND
TIMING
LOGIC
4
8
Y DECODE
DATA REGISTER
6615 FHD F01
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
©Xicor, Inc. 1995, 1996 Patents Pending
6615-1.5 6/10/96 T3/C1/D0 NS
1
Characteristics subject to change without notice
X25021
PIN DESCRIPTIONS
Hold (HOLD)
Serial Output (SO)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial
communication with the controller without resetting the
serial sequence. To pause, HOLD must be brought LOW
while SCK is HIGH. To resume communication, HOLD is
brought HIGH, again while SCK is HIGH. If the pause
feature is not used, HOLD should be held HIGH at all
times.
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the rising edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input
on this pin. Data is latched by the falling edge of the serial
clock.
PIN CONFIGURATION
Serial Clock (SCK)
DIP/SOIC
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the falling edge of the clock
input, while data on the SO pin change after the rising
edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25021 is deselected and the SO
output pin is at high impedance and unless an internal
write operation is underway, the X25021 will be in the
standby power mode. CS LOW enables the X25021,
placing it in the active power mode. It should be noted
that after power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
CS
1
8
VCC
SO
2
7
HOLD
WP
3
6
SCK
VSS
4
5
SI
X25021
6615 FHD F02
PIN NAMES
Symbol
CS
SO
SI
SCK
WP
VSS
VCC
HOLD
Write Protect (WP)
When WP is LOW, nonvolatile writes to the X25021 are
disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25021. If the
internal write cycle has already been initiated, WP going
LOW will have no affect on a write.
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Hold Input
6615 PGM T01
2
X25021
PRINCIPLES OF OPERATION
Status Register
The X25021 is a 256 x 8 E2PROM designed to interface
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is formatted as follows:
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The X25021 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the falling SCK. CS must be LOW during the entire
operation.
7
X
6
X
5
X
4
X
3
BP1
2
BP0
1
WEL
0
WIP
6615 PGM T02
BP0 and BP1 are set by the WRSR instruction. WEL
and WIP are read-only and automatically set by other
operations.
Table 1 contains a list of the instructions and their codes.
All instructions, addresses and data are transferred
MSB first.
The Write-In-Process (WIP) bit indicates whether the
X25021 is busy with a write operation. When set to a “1”,
a write is in progress, when set to a “0”, no write is in
progress. During a write, all other bits are set to “1”.
Data input is sampled on the first falling edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then resume operations. If the clock
line is shared with other peripheral devices on the SPI
bus, the user can assert the HOLD input to place the
X25021 into a “PAUSE” condition. After releasing HOLD,
the X25021 will resume operation from the point when
HOLD was first asserted.
The Write Enable Latch (WEL) bit indicates the status of
the “write enable” latch. When set to a “1”, the latch is set,
when set to a “0”, the latch is reset.
The Block Protect (BP0 and BP1) bits are nonvolatile
and allow the user to select one of four levels of protection. The X25021 is divided into four 1024-bit segments.
One, two, or all four of the segments may be protected.
That is, the user may read the segments but will be
unable to alter (write) data within the selected segments.
The partitioning is controlled as illustrated below.
Write Enable Latch
The X25021 contains a “write enable” latch. This latch
must be SET before a write operation will be completed
internally. The WREN instruction will set the latch and
the WRDI instruction will reset the latch. This latch is
automatically reset upon a power-up condition and after
the completion of a byte, page, or status register write
cycle.
Status Register Bits
BP1
BP0
0
0
1
1
0
1
0
1
Array Addresses
Protected
None
$C0–$FF
$80–$FF
$00–$FF
6615 PGM T03
Table 1. Instruction Set
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
Instruction Format*
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Status Register
Write Status Register
Read Data from Memory Array beginning at selected address
Write Data to Memory Array beginning at Selected Address
(1 to 32 Bytes)
6615 PGM T04
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
3
X25021
Clock and Data Timing
For the write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
data byte N is clocked in. If it is brought HIGH at any other
time the write operation will not be completed. Refer to
Figures 4 and 5 below for a detailed illustration of the
write sequences and time frames in which CS going
HIGH are valid.
Data input on the SI line is latched on the falling edge of
SCK. Data is output on the SO line by the rising edge of
SCK.
Read Sequence
When reading from the E2PROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25021, followed by the
8-bit address. After the READ opcode and address are
sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequentially
by continuing to provide clock pulses. The address is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached ($FF) the address counter rolls
over to address $00 allowing the read cycle to be
continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the read E2PROM
array operation sequence illustrated in Figure 1.
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5, 6
and 7 must be “0”. Figure 6 illustrates this sequence.
While the write is in progress following a status register
or E2PROM write sequence, the status register may be
read to check the WIP bit. During this time the WIP bit will
be HIGH.
Hold Operation
The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can be
resumed. The only restriction is the SCK input must be
HIGH when HOLD is first pulled LOW and SCK must
also be HIGH when HOLD is released.
To read the status register, the CS line is first pulled
LOW to select the device followed by the 8-bit RDSR
instruction. After the read status register opcode is
sent, the contents of the status register are shifted out
on the SO line. Figure 2 illustrates the read status
register sequence.
The HOLD input may be tied HIGH either directly to VCC
or tied to VCC through a resistor.
Write Sequence
Prior to any attempt to write data into the X25021, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the X25021.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the write
operation without taking CS HIGH after issuing the
WREN instruction, the write operation will be ignored.
To write data to the E2PROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. This is minimally a
twenty-four clock operation. CS must go LOW and
remain LOW for the duration of the operation. The host
may continue to write up to 4 bytes of data to the X25021.
The only restriction is the 4 bytes must reside on the
same page. If the address counter reaches the end of
the page and the clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may have been written.
4
X25021
Operational Notes
Data Protection
The X25021 powers-up in the following state:
The following circuitry has been included to prevent
inadvertent writes:
• The device is in the low power standby state.
• The “write enable” latch is reset upon power-up.
• A HIGH to LOW transition on CS is required to
enter an active state and receive an instruction.
• A WREN instruction must be issued to set the “write
enable” latch.
• SO pin is high impedance.
• CS must come HIGH at the proper clock count in
order to start a write cycle.
• The “write enable” latch is reset.
Figure 1. Read E2PROM Array Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
7
6
10 11 12 13 14 15 16 17 18 19 20 21 22
SCK
INSTRUCTION
BYTE ADDRESS
SI
5
4
3
2
1
0
DATA OUT
HIGH IMPEDANCE
7
SO
6
5
4
3
2
1
0
MSB
6615 FHD F14
Figure 2. Read Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
7
SO
MSB
5
6
5
4
3
2
1
0
6615 ILL F13
X25021
Figure 3. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
HIGH IMPEDANCE
SO
6615 ILL F05.1
Figure 4. Byte Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
INSTRUCTION
BYTE ADDRESS
7
SI
6
5
4
3
2
DATA BYTE
1
0
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
6615 FHD F06.1
6
X25021
Figure 5. Page Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
7
6
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
INSTRUCTION
DATA BYTE 1
BYTE ADDRESS
SI
5
4
3
2
1
7
0
6
5
4
3
2
1
0
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
DATA BYTE 2
SI
7
6
5
4
3
2
DATA BYTE 3
1
0
7
6
5
4
3
2
DATA BYTE 4
1
0
7
6
5
4
3
2
1
0
6615 FHD F07
Figure 6. Write Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
DATA BYTE
INSTRUCTION
7
SI
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
6615 ILL F08
7
X25021
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with Respect to VSS ......... –1V to +7V
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds) .............................. 300°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
–40°C
Supply Voltage
X25021
X25021-3
X25021-2.7
Max.
+70°C
+85°C
6615 PGM T05.1
Limits
5V ±10%
3V to 5.5V
2.7 to 5.5V
6615 PGM T06
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
ICC
VCC Supply Current (Active)
ISB
ILI
ILO
VIL(1)
VIH(1)
VOL
VOH
VCC Supply Current (Standby)
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Min.
Max.
3
Units
mA
10
10
10
–0.5
VCC x 0.3
VCC x 0.7 VCC + 0.5
0.4
VCC – 0.8
µA
µA
µA
V
V
V
V
Test Conditions
SCK = VCC x 0.1/VCC x 0.9 @ 1MHz,
SO = Open
CS = VCC, VIN = VSS or VCC – 0.3V
VIN = VSS to VCC
VOUT = VSS to VCC
IOL = 2mA
IOH = –1mA
6615 PGM T07.2
POWER-UP TIMING
Symbol
tPUR(2)
Parameter
Power-up to Read Operation
tPUW(2)
Power-up to Write Operation
Min.
Max.
1
Units
ms
5
ms
6615 PGM T08
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V.
Symbol
COUT(2)
CIN(2)
Test
Output Capacitance (SO)
Input Capacitance (SCK, SI, CS, WP, HOLD)
Max.
8
6
Units
pF
pF
Conditions
VOUT = 0V
VIN = 0V
6615 PGM T09
Notes:
(1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
8
X25021
EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC
A.C. TEST CONDITIONS
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10ns
Input and Output Timing Level
VCC x 0.5
5V
2.16KΩ
6615 PGM T10
OUTPUT
3.07KΩ
100pF
6615 FHD F12
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data Input Timing
Symbol
fSCK
tCYC
tLEAD
tLAG
tWH
tWL
tSU
tH
tRI
tFI
tHD
tCD
tCS
tWC(4)
Parameter
Clock Frequency
Cycle Time
CS Lead Time
CS Lag Time
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Data In Rise Time
Data In Fall Time
HOLD Setup Time
HOLD Hold Time
CS Deselect Time
Write Cycle Time
Min.
0
1000
500
500
400
400
100
100
Max.
1
2
2
200
200
500
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ms
6615 PGM T11.1
Data Output Timing
Symbol
fSCK
tDIS
tV
tHO
tRO(3)
tFO(3)
tLZ
tHZ
Parameter
Clock Frequency
Output Disable Time
Output Valid from Clock LOW
Output Hold Time
Output Rise Time
Output Fall Time
HOLD HIGH to Output in Low Z
HOLD LOW to Output in High Z
Min.
Max.
Units
0
1
500
400
MHz
ns
ns
ns
ns
ns
ns
ns
0
300
300
100
100
6615 PGM T12.1
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal
nonvolatile write cycle.
9
X25021
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tV
SO
SI
tHO
MSB OUT
tWL
tDIS
MSB–1 OUT
LSB OUT
ADDR
LSB IN
6615 FHD F09
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
SI
tH
tRI
MSB IN
tFI
LSB IN
HIGH IMPEDANCE
SO
6615 FHD F10.1
10
X25021
Hold Timing
CS
tHD
tCD
tCD
tHD
SCK
tHZ
tLZ
SO
SI
HOLD
6615 FHD F11
SYMBOL TABLE
WAVEFORM
11
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
X25021
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.045 (1.14)
0.150 (3.81)
0.125 (3.18)
0.020 (0.51)
0.016 (0.41)
0.110 (2.79)
0.090 (2.29)
0.015 (0.38)
MAX.
0.060 (1.52)
0.020 (0.51)
0.325 (8.25)
0.300 (7.62)
0°
15°
TYP. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F01
12
X25021
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
X 45°
0.020 (0.50)
0.050" TYPICAL
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F22.1
13
X25021
ORDERING INFORMATION
X25021
P
T
-V
VCC Limits
Blank = 5V ±10%
3 = 3V to 5.5V
2.7V = 2.7V to 5.5V
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
P = 8-Lead Plastic DIP
S = 8-Lead SOIC
Part Mark Convention
X25021
Blank = 8-Lead SOIC
P = 8-Lead Plastic DIP
X
X
Blank = 5V ±10%, 0°C to +70°C
I = 5V ±10%, –40°C to +85°C
D = 3V to 5.5V, 0°C to +70°C
E = 3V to 5.5V, –40°C to +85°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, –40°C to + 85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
14