ICMIC X25128P-2.7

ICmic
TM
This X25128 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
IC MICROSYSTEMS
16K x 8 Bit
X25128
128K
2
TM
SPI Serial E PROM with Block Lock
FEATURES
Protection
DESCRIPTION
2
The X25128 is a CMOS 131,072-bit serial E PROM,
internally organized as 16K x 8. The X25128 features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus.
•2MHz Clock Rate
•SPI Modes (0,0 & 1,1)
•16K X 8 Bits
—32 Byte Page Mode
•Low Power CMOS
The bus signals are a clock input (SCK) plus separate data
in (SI) and data out (SO) lines. Access to the
—<1µA Standby Current
—<5mA Active Current
•2.7V To 5.5V Power Supply
•Block Lock Protection
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same
bus.
2
—Protect 1/4, 1/2 or all of E PROM Array
•Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Enable Latch
—Write Protect Pin
•Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
•High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
•14-Lead SOIC Package
•16-Lead SOIC Package
•8-Lead PDIP Package
The X25128 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25128 will ignore transitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as a
hardwire input to the X25128 disabling all write
attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25128 utilizes Xicor’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
STATUS
REGISTER
WRITE
PROTECT
LOGIC
X DECODE
LOGIC
16K BYTE
ARRAY
128
16 X 256
SO
SI
COMMAND
DECODE
SCK
CS
AND
CONTROL
LOGIC
128
16 X 256
HOLD
256
32 X 256
WP
WRITE
CONTROL
AND
TIMING
LOGIC
32
8
Y DECODE
DATA REGISTER
©Xicor Inc. 1994, 1995, 1996 Patents Pending
3091-2.9 5/14/97 T2/C0/D2 SH
1
3091 FM F01
Characteristics subject to change without notice
X25128
PIN DESCRIPTIONS
low. If the pause feature is not used, HOLD should be
held high at all times.
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
PIN CONFIGURATION
Not to scale
14 Lead SOIC
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
CS
SO
1
2
14
13
NC
3
12
NC
NC
4
11
NC
NC
5
10
NC
WP
VSS
6
9
SCK
7
8
SI
.344”
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the
clock input, while data on the SO pin change after the
falling edge of the clock input.
X24128
VCC
HOLD
.244”
16 Lead SOIC
CS
SO
1
NC
3
14
NC
NC
4
13
NC
NC
5
12
NC
NC
6
11
NC
WP
VSS
7
10
SCK
8
9
Chip Select (CS)
When CS is high, the X25128 is deselected and the
SO output pin is at high impedance and unless an
internal write operation is underway, the X25128 will
be in the standby power mode. CS low enables the
X25128, placing it in the active power mode. It should
be noted that after power-up, a high to low transition
on CS is required prior to the start of any operation.
.394”
16
15
2
X25128
VCC
HOLD
SI
.244”
Write Protect (WP)
8 Lead PDIP
When WP is low and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25128 status register are
disabled, but the part otherwise functions normally.
When WP is held high, all functions, including nonvolatile writes operate normally. WP going low while CS is
still low will interrupt a write to the X25128 status
register. If the internal write cycle has already been
initiated, WP going low will have no effect on a write.
CS
SO
1
8
2
7
WP
VSS
3
.430”
X25128
4
VCC
HOLD
6
SCK
5
SI
.325”
3091 FM 02
PIN NAMES
The WP pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install
the X25128 in a system with WP pin grounded and still
be able to write to the status register. The WP pin functions will be enabled when the WPEN bit is set “0”.
Symbol
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought low while SCK is Low. To resume communication, HOLD is brought high, again while SCK is
Description
CS
Chip Select Input
SO
Serial Output
SI
Serial Input
SCK
Serial Clock Input
WP
Write Protect Input
VSS
Ground
VCC
Supply Voltage
HOLD
Hold Input
NC
No Connect
3091 FM T01
2
X25128
PRINCIPLES OF OPERATION
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is
formatted as follows:
2
The X25128 is a 8K x 8 E PROM designed to interface directly with the synchronous serial peripheral
interface (SPI) of many popular microcontroller families.
The X25128 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in
on the rising SCK. CS must be low and the HOLD and
WP inputs must be high during the entire operation.
The WP input is “Don’t Care” if WPEN is set “0”.
7
6
5
4
3
2
1
0
WPEN
X
X
X
BP1
BP0
WEL
WIP
3091 FM T02
WPEN, BP0 and BP1 are set by the WRSR instruction. WEL and WIP are read-only and automatically set
by other operations.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are
transferred MSB first.
The Write-In-Process (WIP) bit indicates whether the
X25128 is busy with a write operation. When set to a
“1”, a write is in progress, when set to a “0”, no write is
in progress. During a write, all other bits are set to “1”.
Data input is sampled on the first rising edge of SCK
after CS goes low. SCK is static, allowing the user to
stop the clock and then resume operations. If the clock
line is shared with other peripheral devices on the SPI
bus, the user can assert the HOLD input to place the
X25128 into a “PAUSE” condition. After releasing
HOLD, the X25128 will resume operation from the
point when HOLD was first asserted.
The Write Enable Latch (WEL) bit indicates the status
of the “write enable” latch. When set to a “1”, the latch
is set, when set to a “0”, the latch is reset.
The Block Protect (BP0 and BP1) bits are nonvolatile
and allows the user to select one of four levels of
protection. The X25128 is divided into four 32,768-bit
segments. One, two, or all four of the segments may
be protected. That is, the user may read the segments
but will be unable to alter (write) data within the
selected segments. The partitioning is controlled as
illustrated below.
Write Enable Latch
The X25128 contains a “write enable” latch. This latch
must be SET before a write operation will be
completed internally. The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-on condition
and after the completion of a byte, page, or status
register write cycle.
Status Register Bits
BP1
BP0
Array Addresses
Protected
0
0
None
0
1
$3000–$3FFF
1
0
$2000–$3FFF
1
1
$0000–$3FFF
3091 PGM T03
Table 1. Instruction Set
Instruction Name
Instruction Format*
Operation
WREN
0000 0110
Set the Write Enable Latch (Enable Write Operations)
WRDI
0000 0100
Reset the Write Enable Latch (Disable Write Operations)
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory Array beginning at selected address
WRITE
0000 0010
Write Data to Memory Array beginning at Selected Address
(1 to 32 Bytes)
3091 PGM T04
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
3
X25128
Write-Protect Enable
The Write-Protect-Enable (WPEN) is available for the
X25128 as a nonvolatile enable bit for the WP pin.
indefinitely. The read operation is terminated by taking
CS high. Refer to the read E2PROM array operation
sequence illustrated in Figure 1.
Protected Unprotected Status
WPEN WP WEL Blocks
Blocks
Register
To read the status register the CS line is first pulled
low to select the device followed by the 8-bit instruction. After the RDSR opcode is sent, the contents of
the status register are shifted out on the SO line. The
read status register sequence is illustrated in Figure 2.
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
Write Sequence
Prior to any attempt to write data into the X25128, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken low,
then the WREN instruction is clocked into the X25128.
After all eight bits of the instruction are transmitted, CS
must then be taken high. If the user continues the write
operation without taking CS high after issuing the
WREN instruction, the write operation will be ignored.
3091 PGM T05.1
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register
control the programmable hardware write protect
feature. Hardware write protection is enabled when
WP pin is low, and the WPEN bit is “1”. Hardware write
protection is disabled when either the WP pin is high
or the WPEN bit is “0”. When the chip is hardware
write protected, nonvolatile writes are disabled to the
Status Register, including the Block Protect bits and
the WPEN bit itself, as well as the block-protected
sections in the memory array. Only the sections of the
memory array that are not block-protected can be
written.
Note:
To write data to the E2PROM memory array, the user
issues the write instruction, followed by the address
and then the data to be written. This is minimally a
thirty-two clock operation. CS must go low and remain
low for the duration of the operation. The host may
continue to write up to 32 bytes of data to the X25128.
The only restriction is the 32 bytes must reside on the
same page. If the address counter reaches the end of
the page and the clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may have been written.
Since the WPEN bit is write protected, it
cannot be changed back to a “0”, as long as
the WP pin is held low.
For the write operation (byte or page write) to be
completed, CS can only be brought high after bit 0 of
data byte N is clocked in. If it is brought high at any
other time the write operation will not be completed.
Refer to Figures 4 and 5 below for a detailed illustration of the write sequences and time frames in which
CS going high are valid.
Clock and Data Timing
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
Read Sequence
When reading from the E2PROM array, CS is first
pulled low to select the device. The 8-bit read instruction is transmitted to the X25128, followed by the
16-bit address of which the last 14 are used. After the
read opcode and address are sent, the data stored in
the memory at the selected address is shifted out on
the SO line. The data stored in memory at the next
address can be read sequentially by continuing to
provide clock pulses. The address is automatically
incremented to the next higher address after each byte
of data is shifted out. When the highest address is
reached ($3FFF) the address counter rolls over to
address $0000 allowing the read cycle to be continued
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5
and 6 must be “0”. This sequence is shown in Figure 6.
While the write is in progress, following a status
register or E2PROM write sequence, the status
register may be read to check the WIP bit. During this
time the WIP bit will be high.
Hold Operation
The HOLD input should be high (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled low to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
4
X25128
be low when HOLD is first pulled low and SCK must
also be low when HOLD is released.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
The HOLD input may be tied high either directly to VCC
or tied to VCC through a resistor.
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write
enable” latch.
• CS must come high at the proper clock count in
order to start a write cycle.
Operational Notes
The X25128 powers-up in the following state:
• The device is in the low power standby state.
• A high to low transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset.
Figure 1. Read E2PROM Array Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
INSTRUCTION
16 BIT ADDRESS
15 14 13
SI
3
2
1
0
DATA OUT
HIGH IMPEDANCE
7
SO
6
5
MSB
CS
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
7
SO
MSB
5
6
5
4
3
2
3
2
1
0
3091 FM F03
Figure 2. Read Status Register Operation Sequence
0
4
1
0
3091 FM F04
X25128
Figure 3. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
HIGH IMPEDANCE
SO
3091 FM F05
Figure 4. Byte Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
20 21 22 23 24 25 26 27 28 29 30 31
10
SCK
INSTRUCTION
16 BIT ADDRESS
15 14 13
SI
3
2
DATA BYTE
1
0
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
3091 FM F06
6
X25128
Figure 5. Page Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
20 21 22 23 24 25 26 27 28 29 30 31
10
SCK
INSTRUCTION
16 BIT ADDRESS
15 14 13
SI
3
2
DATA BYTE 1
1
0
7
6
5
4
3
2
1
0
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
DATA BYTE 2
SI
7
6
5
4
3
DATA BYTE 3
2
1
0
7
6
5
4
3
DATA BYTE N
2
1
0
6
5
4
3
2
1
0
3091 FM F07
Figure 6. Write Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
INSTRUCTION
DATA BYTE
7
SI
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
3091 FM F08
7
X25128
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias ................... –65°C to +135°C
Storage Temperature........................ –65°C to +150°C
Voltage on any Pin with
Respect to VSS .................................... –1V to +7V
D.C. Output Current ..............................................5mA
Lead Temperature
(Soldering, 10 seconds) .............................. 300°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
0°C
+70°C
X25128
5V ±10%
Industrial
–40°C
+85°C
X25128-2.7
2.5V to 5.5V
Military
–55°C
+125°C
3091 FM T07.2
3091 FM T06.1
D.C. OPERATING CHARACTERISTICS
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
ICC
VCC Supply Current (Active)
5
mA
SCK = VCC x 0.1/VCC x 0.9 @ 2 MHz,
SO = Open, CS = VSS
ISB
VCC Supply Current (Standby)
1
µA
CS = VCC, VIN = VSS or VCC
ILI
Input Leakage Current
10
µA
VIN = VSS to VCC
ILO
Output Leakage Current
10
µA
VOUT = VSS to VCC
VlL(1)
VIH(1)
Input LOW Voltage
–1
VCC x 0.3
V
Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output LOW Voltage
0.4
V
VCC = 5V, IOL = 3mA
VOH1
Output HIGH Voltage
V
VCC = 5V, IOH = -1.6mA
VOL2
Output LOW Voltage
VOH2
Output HIGH Voltage
VCC – 0.8
0.4
VCC – 0.3
V
VCC = 3V, IOL = 1.5mA
V
VCC = 3V, IOH = -0.4mA
POWER-UP TIMING
Symbol
tPUR(3)
tPUW(3)
Parameter
Min.
Max.
Units
Power-up to Read Operation
1
ms
Power-up to Write Operation
5
ms
3091 FM T09
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
COUT(2)
CIN(2)
Test
Max.
Units
Conditions
Output Capacitance (SO)
8
pF
VOUT = 0V
Input Capacitance (SCK, SI, CS, WP, HOLD)
6
pF
VIN = 0V
3091 FM T10.1
Notes: (1)
(2)
(3)
VIL min. and VIH max. are for reference only and are not tested.
This parameter is periodically sampled and not 100% tested.
tPUR and tPUW are the delays required from the time V CC is stable until the specified operation can be initiated. These
parameters are periodically sampled and not 100% tested.
8
X25128
A.C. CONDITIONS OF TEST
EQUIVALENT A.C. LOAD CIRCUIT
5V
3V
1.44KΩ
OUTPUT
1.95KΩ
1.64KΩ
100pF
OUTPUT
4.63KΩ
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall
Times
10ns
VCC X 0.5
Input and Output
Timing Levels
100pF
3091 FM T11
3091 FM F09.1
A.C. OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.)
Data Input Timing
Symbol
Parameter
Min.
Max.
Units
0
2
MHz
fSCK
Clock Frequency
tCYC
Cycle Time
500
ns
tLEAD
CS Lead Time
250
ns
tLAG
CS Lag Time
250
ns
tWH
Clock HIGH Time
200
ns
tWL
Clock LOW Time
200
ns
tSU
Data Setup Time
50
ns
tH
Data Hold Time
50
ns
tRI(4)
tFI(4)
Data In Rise Time
2
µs
Data In Fall Time
2
µs
tHD
HOLD Setup Time
100
ns
tCD
HOLD Hold Time
100
ns
tCS
CS Deselect Time
2.0
µs
tWC(5)
Write Cycle Time
10
ms
3091 FM T12.2
Data Output Timing
Symbol
Parameter
Min.
Max.
Units
0
2
MHz
fSCK
Clock Frequency
tDIS
Output Disable Time
250
ns
tV
Output Valid from Clock LOW
200
ns
tHO
Output Hold Time
tRO(4)
tFO(4)
tLZ(4)
tHZ(4)
Output Rise Time
100
ns
Output Fall Time
100
ns
0
ns
HOLD HIGH to Output in Low Z
100
ns
HOLD LOW to Output in Low Z
100
ns
3091 FM T13.2
Notes: (4) This parameter is periodically sampled and not 100% tested.
(5) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal
nonvolatile write cycle.
9
X25128
Serial Output Timing
CS
t CYC
t LAG
tWH
SCK
tV
SO
SI
t HO
MSB OUT
t DIS
t WL
MSB–1 OUT
LSB OUT
ADDR
LSB IN
3091 FM F10.1
Serial Input Timing
t CS
CS
t LEAD
t LAG
SCK
tSU
SI
tH
tRI
MSB IN
t FI
LSB IN
HIGH IMPEDANCE
SO
3091 FM F11
10
X25128
Hold Timing
CS
tHD
tCD
t CD
t HD
SCK
tHZ
t LZ
SO
SI
HOLD
3091 FM F12.1
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
11
X25128
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.045 (1.14)
0.150 (3.81)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
0.015 (0.38)
MAX.
0.060 (1.52)
0.020 (0.51)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0°
15°
TYP .0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
7040 FM 18
12
X25128
PACKAGING INFORMATION
14-LEAD PLASTIC SMALL OUTLINE GULLWING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.51)
0.336 (8.55)
0.345 (8.75)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.10)
0.010 (0.25)
0.050 (1.27)
0.050" Typical
0.010 (0.25)
X 45°
0.020 (0.50)
0.050" T ypical
0° – 8°
0.250"
0.0075 (0.19)
0.010 (0.25)
0.016 (0.410)
0.037 (0.937)
FOO TPRINT
0.030" Typical
14 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
13
X25128
PACKAGING INFORMATION
16-LEAD PLASTIC SMALLOUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.51)
0.386 (9.80)
0.394 (10.01)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50) X 45°
0.050" Typical
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.050"
Typical
0.250"
0.016 (0.410)
0.037 (0.937)
FOOTPRINT
0.030" Typical
16 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14
X25128
ORDERING INFORMATION
X25128
X
X
G -X
Device
Vcc Range
Blank = 5V ±10%
2.7 = 2.7V to 5.5V
G = RoHS Compliant Lead Free package
Blank = Standard package. Non lead free
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
S14 = 14-Lead SOIC
S = 16-Lead SOIC
P = 8-Lead PDIP
Part Mark Convention
X25128
XG
X
G = RoHS compliant lead-free
S14 = 14-Lead SOIC
S = 16-Lead SOIC
P = 8-Lead PDIP
Blank = 5V ±10%, 0°C to +70°C
I = 5V ±10%, –40°C to +85°C
M = 5V ±10%, –55°C to +125°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, –40°C to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no
warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from
patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production
and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses
are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign
patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its safety or effectiveness.
15