ZILOG Z86C04

PRELIMINARY PRODUCT SPECIFICATION
1
Z86C04/C08
1
CMOS 8-BIT LOW-COST
1K/2K-ROM MICROCONTROLLERS
FEATURES
Part
Number
ROM
(KB)
Z86C04
Z86C08
1
2
RAM* Speed
(Bytes) (MHz)
125
125
12
12
–
–
–
Auto Permanent
Latch
WDT
Optional
Optional
Optional
Optional
Permanent Watch-Dog Timer (WDT)
RC Oscillator
32 kHz Operation
■
Two Programmable 8-Bit Counter/Timers,
Each with 6-Bit Programmable Prescaler
Note: * General-Purpose
■
18-Pin DIP and SOIC Packages
■
Power-On Reset (POR) Timer
■
3.0V to 5.5V Operating Range
■
■
Available Temperature Ranges
A = –40°C to +125°C
E = –40°C to +105°C
S = 0°C to +70°C
On-Chip Oscillator that Accepts RC, Crystal,
Ceramic Resonance, LC, or External Clock Drive
■
Clock-Free WDT Reset
■
Low-Power Consumption (50mw)
■
14 Input / Output Lines
■
Fast Instruction Pointer
(1.0 µs @ 12 MHz)
■
Six Vectored, Prioritized Interrupts from Six Different
Sources
■
Fourteen Digital Inputs at CMOS Levels;
Schmitt-Triggered
■
Software Enabled Watch-Dog Timer
■
Programmable Interrupt Polarity
■
Two Standby Modes: STOP and HALT
■
Low-Voltage Protection
■
Two On-Board Comparators
■
ROM Mask Options:
– Low Noise
– ROM Protect
– Auto Latch
– System Clock Driving WDT (Z86C04 only)
GENERAL DESCRIPTION
Zilog’s Z86C04/C08 are members of the Z8 ® MCU singlechip microcontroller family which offer easy software/hardware system expansion.
For applications demanding powerful I/O capabilities, the
Z86C04/C08’s dedicated input and output lines are
grouped into three ports, and are configurable under software control to provide timing, status signals, or parallel
I/O.
DS97DZ80502
Two on-chip counter/timers, with a large number of user
selectable modes, off-load the system of administering
real-time tasks such as counting/timing and I/O data communications. Additionally, two on-board comparators process analog signals with a common reference voltage (Figure 1).
PRELIMINARY
1
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
GENERAL DESCRIPTION (Continued)
Note: All Signals with a preceding front slash, "/", are
active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE
is active Low, only).
Input
Power connections follow conventional descriptions below:
Vcc
Connection
Circuit
Device
Power
Ground
VCC
GND
VDD
VSS
GND
Machine
Timing & Inst.
Control
Port 3
Counter/
Timers (2)
Interrupt
Control
Two Analog
Comparators
XTAL
ALU
FLAG
Prg. Memory
Register
Pointer
Register File
Port 2
Port 0
I/O
(Bit Programmable)
I/O
Program
Counter
Figure 1. Z86C04/C08
Functional Block Diagram
2
PRELIMINARY
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
PIN DESCRIPTIONS
Table 1: 18-Pin DIP and SOIC Pin Identification
P24
1
18
P23
P25
2
17
P22
P26
3
16
P21
P27
4
15
P20
VCC
5
14
GND
XTAL2
6
13
P02
XTAL1
7
12
P01
P31
8
11
P00
P32
9
10
P33
DIP
Pin #
Symbol
1-4
5
6
7
8
P24-P27
V CC
XTAL2
XTAL1
P31
P32
P33
P00-P02
GND
P20-P23
9
10
11-13
14
15-18
Function
Direction
Port 2, Pins 4, 5, 6, 7
Power Supply
Crystal Oscillator Clock
Crystal Oscillator Clock
Port 3, Pin 1, AN1
In/Output
Port 3, Pin 2, AN2
Port 3, Pin 3, REF
Port 0, Pins 0, 1, 2
Ground
Port 2, Pins 0, 1, 2, 3
Input
Input
In/Output
Output
Input
Input
In/Output
Figure 2. 18-Pin DIP Configuration
P24
1
18
P23
P25
2
17
P22
P26
3
16
P21
P27
4
15
P20
14
GND
Vcc
5
SOIC
XTAL2
6
13
P02
XTAL1
7
12
P01
P31
8
11
P00
P32
9
10
P33
Figure 3. 18-Pin SOIC Pin Configuration
DS97DZ80502
PRELIMINARY
3
1
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Units
Ambient Temperature under Bias
Storage Temperature
Voltage on any Pin with Respect to VSS [Note 1]
–40
–65
–0.7
+105
+150
+12
C
C
V
Voltage on VDD Pin with Respect to VSS
–0.3
+7
V
Voltage on Pin 7 with Respect to VSS [Note 2]
–0.7
Total Power Dissipation
Maximum Current out of VSS
V DD+1
462
84
V
mW
mA
Maximum Current into VDD
84
mA
+600
+600
12
12
70
70
µA
µA
mA
mA
mA
mA
Maximum Current into an Input Pin [Note 3]
Maximum Current into an Open-Drain Pin [Note 4]
Maximum Output Current Sinked by Any I/O Pin
Maximum Output Current Sourced by Any I/O Pin
Total Maximum Output Current Sinked by Port 2
Total Maximum Output Current Sourced by Port 2
–600
–600
Notes:
1. This applies to all pins except where otherwise noted. Maximum current into pin must be ±600µA.
2. There is no input protection diode from pin to VDD.
3. This excludes Pin 6 and Pin 7.
4. Device pin is not at an output Low state.
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an ex-
tended period may affect device reliability. Total power
dissipation should not exceed 462 mW for the package.
Power dissipation is calculated as follows:
Total Power dissipation = VDD x [I DD – (sum of IOH)] + sum of
[(V DD – VOH) x IOH ] + sum of (V 0L x I0L).
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin
(Figure 4).
From Output
Under Test
150 pF
Figure 4. Test Load Diagram
4
PRELIMINARY
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
CAPACITANCE
TA = 25°C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Parameter
Min
Max
Input capacitance
Output capacitance
I/O capacitance
0
0
0
15 pF
20 pF
25 pF
1
DC ELECTRICAL CHARACTERISTICS
TA = –40°C
to +125°C
Sym
Parameter
VCH
Clock Input High
Voltage
VCL
VIH
VIL
VOH
VOL1
VOL2
Clock Input Low
Voltage
Input High Voltage
Input Low Voltage
Output High
Voltage
Output Low Voltage
Output Low Voltage
VOFFSET
Comparator Input
Offset Voltage
VLV
VCC Low Voltage
Auto Reset
Input Leakage
(Input Bias
Current of
Comparator)
Output Leakage
IIL
IOL
DS97DZ80502
VCC [4]
Min
Max
Typical
@ 25°C
Units
3.0V
0.8 VCC
VCC+0.3
1.7
V
5.5V
0.8 VCC
VCC+0.3
2.8
V
3.0V
VSS–0.3
0.2 VCC
0.8
V
5.5V
VSS–0.3
0.2 VCC
1.7
V
3.0V
0.7 VCC
VCC+0.3
1.8
V
1
5.5V
0.7 VCC
VCC+0.3
2.8
V
1
3.0V
VSS–0.3
0.2 VCC
0.8
V
1
5.5V
VSS–0.3
0.2 VCC
1.5
V
1
3.0V
VCC–0.4
3.0
V
IOH = –2.0 mA
5
5.5V
VCC–0.4
4.8
V
IOH = –2.0 mA
5
3.0V
VCC–0.4
3.0
V
Low Noise @ IOH = –0.5 mA
5.5V
VCC–0.4
4.8
V
Low Noise @ IOH = –0.5 mA
Conditions
Notes
Driven by External
Clock Generator
Driven by External
Clock Generator
Driven by External
Clock Generator
Driven by External
Clock Generator
3.0V
0.8
0.2
V
IOL = +4.0 mA
5
5.5V
0.6
0.1
V
IOL = +4.0 mA
5
3.0V
0.6
0.2
V
Low Noise @ IOL = 1.0 mA
5.5V
0.6
0.1
V
Low Noise @ IOL = 1.0 mA
3.0V
1.2
0.8
V
IOL = +12 mA
5
5.5V
1.0
0.3
V
IOL = +12 mA
5
3.0V
5.5V
1.8
25
25
3.0
10
10
2.6
mV
mV
V
Int. CLK Freq @ 2 MHz Max.
3.0V
–1.0
1.0
µA
VIN = 0V, VCC
5.5
–1.0
1.0
µA
VIN = 0V, VCC
3.0V
–1.0
1.0
µA
VIN = 0V, VCC
5.5V
–1.0
1.0
µA
VIN = 0V, Vcc
PRELIMINARY
5
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
DC ELECTRICAL CHARACTERISTICS (Continued)
VVICR
ICC
I
I
CC1
CC
6
Comparator Input
Common Mode
Voltage Range
Supply Current
Standby Current
Supply Current
(Low Noise Mode)
0
VCC –1.5
V
3.0V
3.5
1.5
mA
5.5V
7.0
3.8
mA
3.0V
8.0
3.0
mA
5.5V
11.0
4.4
mA
3.0V
10
3.6
mA
5.5V
15
9.0
mA
3.0V
2.5
0.7
mA
5.5V
4.0
2.5
mA
HALT mode VIN = 0V,
VCC @ 2 MHz
5,7
3.0V
4.0
1.0
mA
HALT mode VIN = 0V,
VCC @ 8 MHz
5,7
5.5V
5.0
3.0
mA
HALT mode VIN = 0V,
VCC @ 8 MHz
5,7
3.0V
4.5
1.5
mA
HALT mode VIN = 0V,
VCC @ 12 MHz
5,7
5.5V
7.0
4.0
mA
HALT mode VIN = 0V,
VCC @ 12 MHz
5,7
3.0V
3.5
1.5
mA
5.5V
7.0
3.8
mA
3.0V
5.8
2.5
mA
5.5V
9.0
4.0
mA
3.0V
8.0
3.0
mA
5.5V
11.0
4.4
mA
All Output and I/O Pins Floating
@ 1 MHz
All Output and I/O Pins Floating
@ 1 MHz
All Output and I/O Pins Floating
@ 2 MHz
All Output and I/O Pins Floating
@ 2 MHz
All Output and I/O Pins Floating
@ 4 MHz
All Output and I/O Pins Floating
@ 4 MHz
PRELIMINARY
All Output and I/O Pins Floating
@ 2 MHz
All Output and I/O Pins Floating
@ 2 MHz
All Output and I/O Pins Floating
@ 8 MHz
All Output and I/O Pins Floating
@ 8 MHz
All Output and I/O Pins Floating
@ 12 MHz
All Output and I/O Pins Floating
@ 12 MHz
HALT mode VIN = 0V,
VCC @ 2 MHz
5,7
5,7
5,7
5,7
5,7
5,7
5,7
7
7
7
7
7
7
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
DC ELECTRICAL CHARACTERISTICS (Continued)
TA = –40°C
Sym Parameter
I
CC1
I
CC2
IALL
IALH
Standby Current
(Low Noise Mode)
VCC [4]
to +125°C Typical
Min Max @ 25°C Units
Conditions
Notes
3.0V
2.5
0.7
mA HALT mode VIN = 0V, VCC @ 1MHz
5.5V
4.0
2.5
mA HALT mode VIN = 0V, VCC @ 1MHz
3.0V
3.0
0.9
mA HALT mode VIN = 0V, VCC @ 2 MHz
7
5.5V
4.5
2.8
mA HALT mode VIN = 0V, VCC @ 2 MHz
7
3.0V
4.0
1.0
mA HALT mode VIN = 0V, VCC @ 4 MHz
7
5.5V
5.0
3.0
mA HALT mode VIN = 0V, VCC @ 4 MHz
7
3.0V
20
1.0
7
5.5V
20
1.0
Auto Latch Low Current 3.0V
8.0
3.0
µA STOP mode VIN = 0V, VCC ;WDT is not
Running
µA STOP mode VIN = 0V, VCC ;WDTis not
Running
µA 0V < VIN < VCC
5.5V
30
16
µA 0V < VIN < VCC
Auto Latch High Current 3.0V
–5.0
–1.5
µA 0V < VIN < VCC
5.5V
–20
–8.0
µA 0V < VIN < VCC
Standby Current
7
7
Notes:
1. Port 0, 2, and 3 only.
2. VSS = 0V = GND.
3. The device operates down to VLV. The minimum operational VCC is determined on the value of the voltage VLV at the ambient
temperature. The VLV increases as the temperature decreases.
4. VCC = 3.0V to 5.5V, typical values measured at VCC = 3.3V and VCC = 5.0V.
5. Standard Mode (not Low EMI mode).
6. Z86C08 only.
7. Inputs at power rail and outputs are unloaded.
7
PRELIMINARY
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
DC ELECTRICAL CHARACTERISTICS (Continued)
TA= 0°C to
+70°C
Symbol
VCH
VCL
VIH
VIL
VOH
VOL1
VOL2
Parameter
Clock Input High
Voltage
Clock Input Low
Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Low Voltage
VOFFSET
Comparator Input
Offset Voltage
VLV
VCC Low Voltage
Auto Reset
IIL
IOL
VVICR
8
Input Leakage
(Input Bias Current
of Comparator)
Output Leakage
Comparator Input
Common Mode
Voltage Range
VCC
Min
Max
TA= –40°C to
+105°C
Typical
Min
@ 25°C Units
Max
Conditions
Notes
3.0V 0.8 VCC VCC+0.3 0.8 VCC VCC+0.3
1.7
V
Driven by External
Clock Generator
Driven by External
Clock Generator
Driven by External
Clock Generator
Driven by External
Clock Generator
5.5V 0.8 VCC VCC+0.3 0.8 VCC VCC+0.3
2.8
V
3.0V VSS–0.3 0.2 VCC VSS–0.3 0.2 VCC
0.8
V
5.5V VSS–0.3 0.2 VCC VSS–0.3 0.2 VCC
1.7
V
3.0V 0.7 VCC VCC+0.3 0.7 VCC VCC+0.3
1.8
V
1
5.5V 0.7 VCC VCC+0.3 0.7 VCC VCC+0.3
2.8
V
1
3.0V VSS–0.3 0.2 VCC VSS–0.3 0.2 VCC
0.8
V
1
5.5V VSS–0.3 0.2 VCC VSS–0.3 0.2 VCC
1.5
V
1
3.0V VCC–0.4
VCC–0.4
3.0
V
IOH = –2.0 mA
5
5.5V VCC–0.4
VCC–0.4
4.8
V
IOH = –2.0 mA
5
3.0V VCC–0.4
VCC–0.4
3.0
V
Low Noise @
IOH = –0.5 mA
5.5V VCC–0.4
VCC–0.4
4.8
V
Low Noise @
IOH = –0.5 mA
3.0V
0.8
0.8
0.2
V
IOL= +4.0 mA
5
5.5V
0.4
0.4
0.1
V
IOL= +4.0 mA
5
3.0V
0.4
0.4
0.2
V
Low Noise @
IOL = 1.0 mA
5.5V
0.4
0.4
0.1
V
Low Noise @
IOL = 1.0 mA
3.0V
1.0
1.0
0.8
V
IOL = +12 mA
5
5.5V
0.8
0.8
0.3
V
IOL = +12 mA
5
3.0V
5.5V
25
25
2.8
25
25
10
10
2.6
2.0
3.0
2.6
3.0V
–1.0
1.0
–1.0
1.0
mV
mV
V Int. CLK Freq @
6 MHz Max.
V Int. CLK Freq @
4 MHz Max.
µA VIN = 0V, VCC
5.5V
–1.0
1.0
–1.0
1.0
µA VIN = 0V, VCC
2.2
3.0V
–1.0
1.0
–1.0
1.0
µA VIN = 0V, VCC
5.5V
–1.0
1.0
–1.0
1.0
µA VIN = 0V, VCC
0
VCC–1.0
0
VCC–1.5
PRELIMINARY
V
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
DC ELECTRICAL CHARACTERISTICS (Continued)
TA= 0°C to
+70°C
Symbol
Icc
I
CC1
9
Parameter
Supply Current
Standby Current
VCC
Min
Max
TA= –40°C to
+105°C
Typical
Min
@ 25°C Units
Max
Conditions
3.0V
3.5
3.5
1.5
5.5V
7.0
7.0
3.8
3.0V
8.0
8.0
3.0
5.5V
11.0
11.0
4.4
3.0V
10
10
3.6
5.5V
15
15
9.0
3.0V
2.5
2.5
0.7
5.5V
4.0
4.0
2.5
mA HALT mode VIN = 0V,
VCC @ 2 MHz
5,7
3.0V
4.0
4.0
1.0
mA HALT mode VIN = 0V,
VCC @ 8 MHz
5,7
5.5V
5.0
5.0
3.0
mA HALT mode VIN = 0V,
VCC @ 8 MHz
5,7
3.0V
4.5
4.5
1.5
mA HALT mode VIN = 0V,
VCC @ 12 MHz
5,7
5.5V
7.0
7.0
4.0
mA HALT mode VIN = 0V,
VCC @ 12 MHz
5,7
PRELIMINARY
mA All Output and I/O
Pins Floating @
2 MHz
mA All Output and I/O
Pins Floating @
2 MHz
mA All Output and I/O
Pins Floating @
8 MHz
mA All Output and I/O
Pins Floating @
8 MHz
mA All Output and I/O
Pins Floating @
12 MHz
mA All Output and I/O
Pins Floating @
12 MHz
mA HALT mode VIN = 0V,
VCC @ 2 MHz
Notes
5,7
5,7
5,7
5,7
5,7
5,7
5,7
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
DC ELECTRICAL CHARACTERISTICS (Continued)
TA= 0°C to
+70°C
Symbol
I
CC
10
Parameter
Supply Current
(Low Noise)
VCC
Min
Max
TA= –40°C to
+105°C
Typical
Min
@ 25°C Units
Max
3.0V
3.5
3.5
1.5
5.5V
7.0
7.0
3.8
3.0V
5.8
5.8
2.5
5.5V
9.0
9.0
4.0
3.0V
8.0
8.0
3.0
5.5V
11.0
11.0
4.4
PRELIMINARY
Conditions
mA All Output and I/O
Pins Floating @
1 MHz
mA All Output and I/O
Pins Floating @
1 MHz
mA All Output and I/O
Pins Floating @
2 MHz
mA All Output and I/O
Pins Floating @
2 MHz
mA All Output and I/O
Pins Floating @
4 MHz
mA All Output and I/O
Pins Floating @
4 MHz
Notes
7
7
7
7
7
7
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
TA= 0°C to
+70°C
Symbol
I
CC1
I
CC2
IALL
IALH
Parameter
Standby Current
(Low Noise Mode)
Standby Current
Auto Latch Low
Current
Auto Latch High
Current
VCC
Min
Max
TA= –40°C to
+105°C
Typical
Min
@ 25°C Units
Max
Conditions
Notes
3.0V
2.5
2.5
0.7
mA HALT mode VIN = 0V,
VCC @ 2 MHz
5,7
5.5V
4.0
4.0
2.5
mA HALT mode VIN = 0V,
VCC @ 2 MHz
5,7
3.0V
3.0
3.0
0.9
mA HALT mode VIN = 0V,
VCC @ 8 MHz
5,7
5.5V
4.5
4.5
2.8
mA HALT mode VIN = 0V,
VCC @ 8 MHz
5,7
3.0V
4.0
4.0
1.0
mA HALT mode VIN = 0V,
VCC @ 12 MHz
5,7
5.5V
5.0
5.0
3.0
mA HALT mode VIN = 0V,
VCC @ 12 MHz
5,7
3.0V
10
20
1.0
5.5V
10
20
1.0
3.0V
12
8.0
3.0
µA STOP mode VIN =
0V,Vcc WDT is not
Running
µA STOP mode VIN =
0V,Vcc WDT is not
Running
µA 0V < VIN < VCC
5.5V
32
30
16
µA 0V < VIN < VCC
3.0V
–8
–5.0
–1.5
µA 0V < VIN < VCC
5.5V
–16
–20
–8.0
µA 0V < VIN < VCC
7
7
Notes:
1. Port 0, 2, and 3 only.
2. VSS = 0V = GND.
3. The device operates down to VLV. The minimum operational VCC is determined on the value of the voltage VLV at the ambient
temperature. The VLV increases as the temperature decreases.
4. VCC = 3.0V to 5.5V, typical values measured at VCC = 3.3V and VCC = 5.0V.
5. Standard Mode (not Low EMI mode).
6. Z86C08 only.
7. Inputs at power rail and outputs are unloaded.
DS97DZ80502
PRELIMINARY
11
1
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
1
3
Clock
2
7
2
3
7
T
IN
4
5
6
IRQ
N
8
9
Figure 5. AC Electrical Timing Diagram
12
PRELIMINARY
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
AC ELECTRICAL CHARACTERISTICS
Timing Table (Standard Mode for SCLK/TCLK = XTAL/2)
1
TA = -40C to +125C
8 MHz
No
Symbol
Parameter
Min
Max
Min
Max
Units
Notes
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
125
125
DC
DC
25
25
62
62
83
83
DC
DC
15
15
41
41
ns
ns
ns
ns
ns
ns
ns
ns
100
100
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1,2
1,2
1
1,2
1
TpC
Input Clock Period
2
TrC,TfC
Clock Input Rise
and Fall Times
3
TwC
Input Clock Width
4
TwTinL
Timer Input Low Width
5
TwTinH
Timer Input High Width
6
TpTin
Timer Input Period
7
TrTin,
TtTin
Timer Input Rise
and Fall Time
8
TwIL
Int. Request Input
Low Time
9
TwIH
Int. Request Input
High Time
10 Twdt
11 Tpor
12 MHz
VCC
Watch-Dog Timer
Delay Time Before
Timeout
Power-On Reset Time
3.0V
5.5V
3.0V
5.5V
100
70
5TpC
5TpC
8TpC
8TpC
100
70
5TpC
5TpC
8TpC
8TpC
100
100
100
70
5TpC
5TpC
25
10
50
20
4
2
100
70
5TpC
5TpC
25
10
180
100
60
30
50
20
4
2
ms
ms
180
100
60
30
ms
ms
ms
ms
3
3
4
4
Notes:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
2. Interrupt request through Port 3 (P33-P31).
3. Z86C08.
4. Z86C04
DS97DZ80502
PRELIMINARY
13
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
TA= -40°C to +105°C
TA= 0°C to +70°C
No Symbol
1 TpC
Parameter
VCC
Input Clock Period 3.0V
5.5V
2 TrC,TfC Clock Input Rise
3.0V
and Fall Times
5.5V
3 TwC
Input Clock Width 3.0V
5.5V
4 TwTinL Timer Input Low
3.0V
Width
5.5V
5 TwTinH Timer Input High 3.0V
Width
5.5V
6 TpTin Timer Input Period 3.0V
5.5V
7 TrTin, Timer Input Rise 3.0V
TtTin
and Fall Time
5.5V
8 TwIL
Int. Request Input 3.0V
Low Time
5.5V
9 TwIH
Int. Request Input 3.0V
High Time
5.5V
10 Twdt
Watch-Dog Timer 3.0V
Delay Time
5.5V
Before Timeout
11 Tpor
Power-On Reset 3.0V
Time
5.5V
3.0V
5.5V
8 MHz
Min
Max
125
125
DC
DC
25
25
62
62
100
70
5TpC
5TpC
8TpC
8TpC
12 MHz
Min
Max
83
83
41
41
100
70
5TpC
5TpC
8TpC
8TpC
100
100
100
70
5TpC
5TpC
25
12
50
20
4
3
DC
DC
15
15
125
125
100
100
50
20
4
3
DC
DC
25
25
62
62
100
70
5TpC
5TpC
8TpC
8TpC
100
70
5TpC
5TpC
25
12
160
80
38
18
8 MHz
Min
Max
83
83
100
100
50
20
4
2
DC
DC
15
15
41
41
ns
ns
ns
ns
ns
ns
ns
ns
100
100
ns
ns
ns
ns
100
70
5TpC
5TpC
8TpC
8TpC
100
70
5TpC
5TpC
25
10
160
80
38
18
12 MHz
Min
Max Units Notes
100
70
5TpC
5TpC
25
10
160
80
38
18
50
20
4
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1,2
1,2
1
1,2
ms
ms
160
80
38
18
ms
ms
ms
ms
3
3
4
4
Notes:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
2. Interrupt request through Port 3 (P33-P31).
3. Z86C08.
4. Z86C04
14
PRELIMINARY
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
AC ELECTRICAL CHARACTERISTICS
Low Noise Mode (SCLK/TCLK = XTAL)
TA= –40°C to +125°C
No
Symbol
Parameter
1
TpC
Input Clock Period
2
TrC,TfC
Clock Input Rise
and Fall Times
3
TwC
Input Clock Width
4
TwTinL
Timer Input Low Width
5
TwTinH
Timer Input High Width
6
TpTin
Timer Input Period
7
TrTin,
TtTin
Timer Input Rise
and Fall Time
8
TwIL
Int. Request Input
Low Time
9
TwIH
Int. Request Input
High Time
10 Twdt
Watch-Dog Timer
Delay Time Before Timeout
VCC
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
1 MHz
Min
Max
4 MHz
Min
Max
1000
1000
250
250
DC
DC
25
25
500
500
100
70
2.5TpC
2.5TpC
4TpC
4TpC
Notes
DC
DC
25
25
ns
ns
ns
ns
ns
ns
ns
ns
100
100
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1,2
1,2
1
1,2
3
3
125
125
100
70
2.5TpC
2.5TpC
4TpC
4TpC
100
100
100
70
2.5TpC
2.5TpC
25
10
Units
100
70
2.5TpC
2.5TpC
25
10
ms
ms
Notes:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
2. Interrupt request through Port 3 (P33-P31).
3. Internal RC Oscillator driving WDT.
15
PRELIMINARY
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
TA= 0°C to 70°C
1 MHz
No
1
2
3
4
5
6
7
8
9
10
VCC
Symbol
Parameter
TpC
Input Clock Period
3.0V
5.5V
TrC,TfC Clock Input Rise
3.0V
and Fall Times
5.5V
TwC
Input Clock Width
3.0V
5.5V
TwTinL
Timer Input Low Width 3.0V
5.5V
TwTinH Timer Input High Width 3.0V
5.5V
TpTin
Timer Input Period
3.0V
5.5V
TrTin,
Timer Input Rise
3.0V
TtTin
and Fall Timer
5.5V
TwIL
Int. Request Input
3.0V
Low Time
5.5V
TwIH
Int. Request Input
3.0V
High Time
5.5V
Twdt
Watch-Dog Timer
3.0V
Delay Time Before
5.5V
Timeout
Min
1000
1000
Max
DC
DC
25
25
500
500
100
70
2.5TpC
2.5TpC
4TpC
4TpC
4 MHz
Min
250
250
125
125
100
70
2.5TpC
2.5TpC
4TpC
4TpC
100
100
100
70
2.5TpC
2.5TpC
25
12
TA= –40°C to +105°C
100
70
2.5TpC
2.5TpC
25
12
1 MHz
Max Min
DC 1000
DC 1000
25
25
500
500
100
70
2.5TpC
2.5TpC
4TpC
4TpC
100
100
100
70
2.5TpC
2.5TpC
25
10
Max
DC
DC
25
25
4 MHz
Min
250
250
125
125
100
70
2.5TpC
2.5TpC
4TpC
4TpC
100
100
100
70
2.5TpC
2.5TpC
25
10
Max Units Notes
DC
ns
1
DC
ns
1
25
ns
1
25
ns
1
ns
1
ns
1
ns
1
ns
1
1
1
1
1
100
ns
1
100
ns
1
ns
1,2
ns
1,2
1
1,2
ms
3
ms
3
Notes:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
2. Interrupt request through Port 3 (P33-P31).
3. Internal RC Oscillator driving WDT.
16
PRELIMINARY
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
LOW NOISE VERSION
Low EMI Emission
■
The Z8 can be programmed to operate in a Low EMI
emission mode by means of a mask ROM bit option. Use
of this feature results in:
■
®
■
All pre-driver slew rates reduced to 10 ns typical.
■
Internal SCLK/TCLK operation limited to a maximum of
4 MHz - 250 ns cycle time.
Output drivers have resistances of 200 ohms (typical).
Oscillator divide-by-two circuitry eliminated.
The Low EMI mode is mask-programmable to be selected
by the customer at the time the ROM code is submitted.a
APPLICATION PRECAUTIONS:
1. Emulator does not support the 32KHz operation.
2. For the Z86C04, the WDT only runs in Stop Mode if the
permanent WDT option is selected and if the on-board RC
oscillator is selected as the clock source for the WDT.
3. For the Z86C08, the WDT only runs in Stop Mode if the
permanent WDT option is selected.
4. The registers %FE (GPR) and %FF (SPL) are reset to
00Hex after Stop Mode recovery or any reset.
5. Emulator does not support the system clock driving the
WDT mask option.
DS97DZ80502
PRELIMINARY
17
1
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
PIN DESCRIPTION
XTAL1, XTAL2 Crystal In, Crystal Out (time-based input
and output, respectively). These pins connect a RC, parallel-resonant crystal, LC, or an external single-phase clock
to the on-chip clock oscillator and buffer.
node, reduces excessive supply current flow in the input
buffer. To change the Auto Latch state, the auto latches
must be over driven with current greater than IALH (high to
low) or IALL (low to high).
Auto Latch. The Auto Latch puts valid CMOS levels on all
CMOS inputs (except P33, P32, P31) that are not externally driven. After Power-On Reset, this level is 0 or 1 cannot
be determined. A valid CMOS level, rather than a floating
Port 0 (P02-P00). Port 0 is a 3-bit I/O, bidirectional,
Schmitt-triggered CMOS compatible I/O port. These three
I/O lines can be configured under software control to be all
inputs or all outputs (Figure 7).
Z86E04
and
Z86E08
Port 0 (I/O)
Open
PAD
Out
1.5
2.3 Hysteresis VCC @ 5.0V
In
Auto Latch Option
R
500 kΩ
Figure 6. Port 0 Configuration
18
PRELIMINARY
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Port 2 (P27-P20). Port 2 is an 8-bit I/O, bit programmable,
bi-directional, Schmitt-triggered CMOS compatible I/O
port. These eight I/O lines can be configured under soft-
Zilog
ware control to be an input or output, independently. Bits
programmed as outputs may be globally programmed as
either push-pull or open-drain (Figure 8).
Port 2 (I/O)
MCU
Open Drain
Open
PAD
Out
1.5
2.3 Hysteresis Vcc @ 5.0V
In
Auto Latch
R
500 kΩ
Figure 7. Port 2 Configuration
19
PRELIMINARY
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
PIN DESCRIPTION (Continued)
Port 3 (P33-P31). Port 3 is a 3-bit, Schmitt-triggered
CMOS compatible port with three fixed input (P33-P31)
lines. These three input lines can be configured under soft-
ware control as digital inputs or analog inputs. These three
input lines can also be used as the interrupt sources IRQ0IRQ3 and as the timer input signal (TIN) (Figure 9).
MCU
Port 3
R247 = P3M
D1
1 = Analog
0 = Digital
DIG.
PAD
P31
Data Latch
IRQ, Tin
P31 (AN1)
+
AN.
IRQ3
P32
Data Latch
IRQ0
PAD
P32 (AN2)
+
P33 (REF)
PAD
P33
Data Latch
IRQ1
Vcc
IRQ 0,1,2 = Falling Edge Detection
IRQ 3
= Rising Edge Detection
Figure 8. Port 3 Configuration
Comparator Inputs. Two analog comparators are added to
Port 3 inputs for interface flexibility. Typical applications for
these on-board comparators are: Zero crossing detection,
A/D conversion, voltage scaling, and threshold detection.
The dual comparator (common inverting terminal) features
a single power supply which discontinues power in STOP
mode. The common voltage range is 0-4V when the VCC is
5.0V.
20
Interrupts are generated on either edge of Comparator 2’s
output, or on the falling edge of Comparator 1’s output.
The comparator output may be used for interrupt generation, Port 3 data inputs, or TIN through P31. Alternately, the
comparators may be disabled, freeing the reference input
(P33) for use as IRQ1 and/or P33 input.
PRELIMINARY
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION
RESET. Upon power-up the Power-On Reset circuit waits
for TPOR ms, plus 18 clock cycles, and then starts program
execution at address%000C (Hex) (Figure 10). The device
control registers’ reset value is shown in Table 2.
INT OSC
XTAL OSC
Delay Line
TPOR ms
18 CLK
Reset Filter
POR
(Cold Start)
Chip
Reset
P27
(Stop Mode)
Figure 9. Internal Reset Configuration
Table 1. Z86C04/C08 & C05/C07 Control Registers
Reset Condition
Addr.
03H (3)*
02H (2)*
00H (0)*
FFH(255)
FFH (254)
FDH (253)
FCH (252)
FBH (251)
FAH (250)
Reg.
Port 3
Port 2
Port 0
SPL
GPR
RP
FLAGS
IMR
IRQ
D7
U
U
U
0
0
0
U
0
U
D6
U
U
U
0
0
0
U
U
U
D5
U
U
U
0
0
0
U
U
0
D4
U
U
U
0
0
0
U
U
0
D3
U
U
U
0
0
0
U
U
0
D2
U
U
U
0
0
0
U
U
0
D1
U
U
U
0
0
0
U
U
0
D0
U
U
U
0
0
0
U
U
0
F9H (249)
F8H (248)*
F7H (247)*
F6H (246)*
IPR
P01M
P3M
P2M
U
U
U
1
U
U
U
1
U
U
U
1
U
0
U
1
U
U
U
1
U
U
U
1
U
0
0
1
U
1
0
1
F5H (245)
F4H (244)
F3H (243)
F2H (242)
F1H (241)
PRE0
T0
PRE1
T1
TMR
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
0
U
0
0
U
0
U
0
Comments
IRQ3 is used
for positive
edge detection
Inputs after
reset
Note: *Registers are not reset after a STOP-Mode Recovery using P27 pin.
A subsequent reset will cause these control registers to be re-configured as shown in
Table 2 and the user must avoid bus contention on the port pins or it may affect device reliability.
DS97DZ80502
PRELIMINARY
21
1
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Program Memory. The Z86C04/C08 can address up to
1K/2K bytes of internal program memory (Figure 11). The
first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors
that correspond to the six available interrupts. Bytes 01023/2047 are on-chip mask-programmed ROM.
1023/2047
Location of
First Byte of
Instruction
Executed
After RESET
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
Location
SPL
Stack Pointer (Bits 7-0)
254
Reserved
253
Register Pointer
252
Program Control Flags
Flags
251
Interrupt Mask Register
IMR
0CH
250
Interrupt Request Register
IRQ
IPR
On-Chip
ROM
RP
11
IRQ5
0BH
249
Interrupt Priority Register
10
IRQ5
0AH
248
Ports 0-1 Mode
P01M
9
IRQ4
09H
247
Port 3 Mode
P3M
8
IRQ4
08H
246
Port 2 Mode
P2M
To Prescaler
PRE0
IRQ3
07H
245
7
244
Timer/Counter0
6
IRQ3
06H
243
T1 Prescaler
5
IRQ2
05H
242
Timer/Counter1
4
IRQ2
04H
241
Timer Mode
3
IRQ1
03H
2
IRQ1
02H
1
IRQ0
01H
IRQ0
00H
0
240
T0
PRE1
T1
TMR
Not Implemented
128
127
Figure 10. Program Memory Map
Register File. The Register File consists of three I/O port
registers, 125 general-purpose registers, and 14 control
and status registers (R0, R2-R3, R4-R127, and R241R255, respectively; see Figure 12). Note that R254 is
available for general purpose use. The Z8 instructions can
access registers directly or indirectly through an 8-bit address field. This allows short 4-bit register addressing using the Register Pointer. In the 4-bit mode, the register file
is divided into eight working register groups, each occupying 16 continuous locations. The Register Pointer (Figure
13) addresses the starting location of the active working-
22
Indentifiers
255
3FH/7FFH
12
register group. Upon power-up, the general purpose registers are undefined.
PRELIMINARY
General Purpose
Registers
4
3
Port 3
P3
2
Port 2
P2
1
Reserved
P1
0
Port 0
P0
Figure 11. Register File
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
r7 r6
r5 r4
r3 r2
r1 r0
R253
(Register Pointer)
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
FF
Register Group F
R15 to R0
F0
Counter/Timer. There are two 8-bit programmable
counter/timers (T0 and T1), each driven by its own 6-bit
programmable prescaler. The T1 prescaler can be driven
by internal or external clock sources, however the T0 can
be driven by the internal clock source only (Figure 14).
The 6-bit prescalers can divide the input frequency of the
clock source by any integer number from 1 to 64. Each
prescaler drives its counter, which decrements the value
(1 to 256) that has been loaded into the counter. When
both counter and prescaler reach the end of count, a timer
interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated.
The counter can be programmed to start, stop, restart to
continue, or restart from the initial value. The counters can
also be programmed to stop upon reaching zero (single
pass mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode).
7F
70
6F
60
5F
50
4F
40
3F
Specified Working
Register Group
30
2F
20
1F
10
0F
Register Group 1
R15 to R0
Register Group 0
R15 to R4*
I/O Ports
00
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register.
The counters, but not the prescalers are read at any time
without disturbing their value or count mode. The clock
source for T1 is user-definable and can be either the internal microprocessor clock divided by four, or an external
signal input through Port 3. The Timer Mode register configures the external timer input (P31) as an external clock,
a trigger input that is retriggerable or non-retriggerable, or
as a gate input for the internal clock.
R3 to R0
*Expanded Register Group (0) is selected in this figure
by handling bits D3 to D0 as "0" in Register R253(RP).
Figure 12. Register Pointer
Stack Pointer. The Z8 has an 8-bit Stack Pointer (R255)
used for the internal stack that resides within the 124 general-purpose registers.
General-Purpose Register (GPR). The general-purpose
register upon device power-up is undefined. The generalpurpose register upon a STOP-Mode Recovery and reset
stays in its last state. It may not keep its last state from a
VLV reset if the VCC drops below 2.6V. Note: Register R254
has been designated as a general-purpose register and is
set to 00H after any reset.
DS97DZ80502
PRELIMINARY
23
1
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
Internal Data Bus
Write
OSC
÷2
Write
Read
PRE0
Initial Value
Register
T0
Initial Value
Register
6-Bit
Down
Counter
8-Bit
Down
Counter
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE1
Initial Value
Register
T1
Initial Value
Register
T0
Current Value
Register
*
÷4
IRQ4
Internal
Clock
Clock
Logic
÷4
Internal Clock
Gated Clock
Triggered Clock
External Trigger
TIN P31
Write
* Note: Divide-by-two is not used in Low EMI Mode.
Write
IRQ5
T1
Current Value
Register
Read
Internal Data Bus
Figure 13. Counter/Timers Block Diagram
Interrupts. The Z8 has six interrupts from six different
sources. These interrupts are maskable and prioritized
(Figure 15). The six sources are divided as follows: the falling edge of P31 (AN1), P32 (AN2), P33 (REF), the rising
edge of P32 (AN2), and the two counter/timers. The Interrupt Mask Register globally or individually enables or disables the six interrupt requests (Table 3).
To accommodate polled interrupt systems, interrupt inputs
are masked and the interrupt request register is polled to
determine which of the interrupt requests needs service.
Note: User must select any Z86C08 mode in Zilog’s C12
ICEBOX™ emulator. The rising edge interrupt is not
supported on the Z86CCP00ZEM emulator.
When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. All Z8 interrupts are
vectored through locations in program memory. When an
Interrupt machine cycle is activated, an interrupt request is
granted. This disables all subsequent interrupts, saves the
Program Counter and Status Flags, and then branches to
the program memory vector location reserved for that interrupt. This memory location and the next byte contain the
16-bit starting address of the interrupt service routine for
that particular interrupt request.
24
PRELIMINARY
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Table 2. Interrupt Types, Sources, and Vectors
Name
Source
Vector Location
Comments
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
AN2(P32)
REF(P33)
AN1(P31)
AN2(P32)
T0
T1
0,1
2,3
4,5
6,7
8,9
10,11
External (F) Edge
External (F) Edge
External (F) Edge
External (R) Edge
Internal
Internal
Notes:
F = Falling edge triggered
R = Rising edge triggered.
IRQ0 - IRQ5
IRQ
IMR
6
Global
Interrupt
Enable
Interrupt
Request
IPR
PRIORITY
LOGIC
Vector Select
Figure 14. Interrupt Block Diagram
25
PRELIMINARY
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
Clock. The on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a RC, crystal, ceramic
resonator, LC, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal should be
AT cut, 12 MHz max, with a series resistance (RS) less
than or equal to 100 Ohms.
The crystal should be connected across XTAL1 and
XTAL2 using the vendor’s crystal recommended capacitors (which depends on the crystal manufacturer, ceramic
resonator and PCB layout) from each pin directly to device
Ground pin 14 (Figure 16).
Note that the crystal capacitor loads should be connected
to VSS pin 14 to reduce ground noise injection.
To use 32 KHz crystal, the 32 KHz operational mask option
must be selected, and an external resistor R must be connected across XTAL1 and XTAL2.To use RC oscillator,
the RC oscillator option must be selected.
HALT Mode. This instruction turns off the internal CPU
clock but not the crystal oscillation. The counter/timers and
external interrupts IRQ0, IRQ1, IRQ2, and IRQ3 remain
active. The device can be recovered by interrupts, either
externally or internally generated. An interrupt request
must be executed (enabled) to exit HALT mode. After the
interrupt service routine, the program continues from the
instruction after the HALT.
STOP Mode. This instruction turns off the internal clock
and external crystal oscillation and reduces the standby
current. The STOP mode can be released by two methods.
The first method is a RESET of the device by removing
VCC or dropping the VCC below VLV. The second method
is if P27 is at a low level when the device executes the
STOP instruction. A low condition on P27 releases the
STOP mode regardless if configured for input or output.
XTAL1
C1
*
R
32 KHz
LD
NOP
STOP
In order to enter STOP or HALT mode, it is necessary to
first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user must execute
a NOP (opcode = FFH) immediately before the appropriate
sleep instruction, that is, as follows:
FF
6F
*
*
FF
7F
NOP
HALT
*
*
*
; clear the pipeline
; enter HALT mode
Watch-Dog Timer (WDT). The Watch-Dog Timer is enabled by instruction WDT. When the WDT is enabled, it
cannot be stopped by the instruction. With the WDT instruction, the WDT should be refreshed once the WDT is
enabled within every Twdt period; otherwise, the Z8 resets
itself. The WDT instruction affects the Flags accordingly: Z
= 1, S = 0, V = 0.
WDT = 5F (Hex)
XTAL1
XTAL1
C
L
*
XTAL2
C2
; clear the pipeline
; enter STOP mode
or
XTAL2
C2
Ceramic
Resonator
or Crystal
NOP
STOP
XTAL1
C1
XTAL2
P2M, #1XXX XXXXB
Note: (X = dependent upon user’s application.)
XTAL1
C1
C2
32 KHz Crystal Clock
Program execution under both conditions begins at location 000C (Hex). However, when P27 is used to release
the STOP mode, the I/O port mode registers are not reconfigured to their default power-on conditions. This prevents any I/O, configured as output when the STOP instruction was executed, from glitching to an unknown
state. To use the P27 release approach with STOP mode,
use the following instruction:
LC Clock
XTAL2
External Clock
R
XTAL2
RC Clock
* = Use pin 14.
Figure 15. Oscillator Configuration
26
PRELIMINARY
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
Opcode WDT (5FH). The first time opcode 5FH is executed, the WDT is enabled, and subsequent execution clears
the WDT counter. This has to be done within the maximum
TWDT period; otherwise, the WDT times out and generates
a Reset. The generated Reset is the same as a Power-On
Reset of TPOR plus 18 XTAL clock cycles. The WDT does
not work (run) in STOP mode. The WDT is disabled during
and after a Reset, until the WDT is enabled again.
Opcode WDH (4FH). When this instruction is executed it
will enable the WDT during HALT. If not, the WDT will stop
when entering HALT. This instruction does not clear the
counters, it facilitates running the WDT function during
HALT mode. A WDH instruction executed without executing WDT (5FH) has no effect.
Permanent WDT Mask Option. Only when the
Permanent WDT Mask Option is selected, then the WDT
is hardwired to be enabled after reset. The WDT will
operate in Run mode, HALT mode, and STOP mode. The
Opcode 5FH is used to refresh or clear the WDT counter.
The WDH instruction (4FH) has no effect The WDT will not
run in Stop Mode if the system clock driving the WDT is
selected (Z86C04 only).
System Clock Driving WDT Mask Option (Z86C04 only)
When this option is selected, the Z8’s system clock drives
the WDT instead of the on-board RC oscillator driving the
WDT. The WDT time-out will be SCLK x 32,512.The WDT
will not run in Stop Mode.
Low Voltage Protection (VLV). Maximum (VLV) Conditions:
Case 1:
Case 2:
TA= –40°C , +85°C , Internal Clock
Frequency equal or less than 6 MHz
TA= –40°C , +105°C , Internal Clock
Frequency equal or less than 4 MHz
Note: The internal clock frequency is one-half the external
clock frequency in standard mode.
The device will function normally at or above 3.0V under all
conditions. Below 3.0V, the device functions normally until
the Low Voltage Protection trip point (VLV) is reached. The
device is guaranteed to function normally at supply
voltages above the low voltage trip point for the
temperatures and operating frequencies in Cases 1 and 2.
The actual low voltage trip point is a function of
temperature and process parameters (Figure 17).
2 MHz (Typical)
Temp
VLV
–40C°
3.0
0°C
2.75
+25°C
2.6
+70°C +105°C
2.3
2.1
ROM Protect. ROM Protect fully protects the Z86C04/C08
ROM code from being read internally. When ROM Protect
is selected. ROM look-up tables can be used in this
mode.
VCC
(Volts)
3.2
3.0
2.8
2.6
VLV (Typical)
2.4
2.2
2.0
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Figure 16. Typical Z86C04/C08 VLV vs. Temperature
DS97DZ80502
PRELIMINARY
27
1
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
Z8® CONTROL REGISTER DIAGRAMS
R241 TMR
R244 T0
D7 D6
D7 D6 D5 D4 D3 D2 D1 D0
D5 D4
D3
D2 D1
D0
T0 Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
T0 Current Value
(When READ)
0 No Function
1 Load T 0
0 Disable T 0 Count
1 Enable T 0 Count
0 No Function
1 Load T 1
0 Disable T 1 Count
1 Enable T 1 Count
T IN Modes
00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)
Figure 20. Counter/Timer 0 Register (F4H: Read/Write)
R245 PRE0
D7 D6 D5 D4 D3 D2 D1 D0
Count Mode
0 T0 Single Pass
1 T Modulo-n
0
Reserved (Must be 0.)
Reserved (Must be 0.)
Prescaler Modulo
(Range: 1-64 Decimal
01-00 Hex)
Figure 17. Timer Mode Register (F1H: Read/Write)
Figure 21. Prescaler 0 Register (F5H: Write Only)
R242 T1
D7 D6
D5
D4 D3
D2 D1
D0
R246 P2M
T1 Initial Value
(When Written)
(Range 1-256 Decimal
01-00 HEX)
T1 Current Value
(When READ)
Figure 18. Counter Time 1 Register (F2H: Read/Write)
D7
D6 D5
D4 D3
D2
D1 D0
P2 7 - P20 I/O Definition
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT
Figure 22. Port 2 Mode Register (F6H: Write Only)
R243 PRE1
D7 D6
D5
D4 D3
D2 D1
R247 P3M
D0
D7 D6 D5 D4 D3 D2 D1 D0
Count Mode
0 T 1 Single Pass
1 T 1 Modulo
0 Port 2 Open-Drain
1 Port 2 Push-Pull Active
Clock Source
1 T 1Internal
0 T 1External Timing Input
(T IN) Mode
Port 3 Inputs
0 Digital
1 Analog
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
Figure 19. Prescaler 1 Register (F3H: Write Only)
28
Reserved (Must be 0.)
Figure 23. Port 3 Mode Register (F7H: Write Only)
PRELIMINARY
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
R251 IMR
R248 P01M
D7 D6 D5 D4 D3 D2 D1
D7 D6 D5 D4 D3 D2 D1 D0
1
D0
P00 - P0 3 Mode
00 = Output
01 = Input
1 Enables IRQ5-IRQ0
(D = IRQ0)
0
Reserved (Must be 0.)
Must be 1.
1 Enables Interrupts
Reserved (Must be 0.)
Figure 24. Port 0 and 1 Mode Register
(F8H: Write Only)
Figure 27. Interrupt Mask Register (FBH: Read/Write)
R252 Flags
R249 IPR
D7 D6
D7 D6 D5 D4 D3 D2 D1 D0
D5
D4 D3
D2 D1
D0
User Flag F1
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
Reserved (Must be 0.)
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
Figure 28. Flag Register (FCH: Read/Write)
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
Figure 25. Interrupt Priority Register (F9H: Write Only)
Reserved (Must be 0.)
Register Pointer
R250 IRQ
D7 D6 D5 D4 D3 D2
Figure 29. Register Pointer (FDH: Read/Write)
D1 D0
IRQ0 = P32 Input ↓
IRQ1 = P33 Input ↓
IRQ2 = P31 Input ↓
IRQ3 = P32 Input ↑
IRQ4 = T0
IRQ5 = T1
R255 SPL
D7
DS97DZ80502
D1 D0
Stack Pointer Lower
Byte (SP 0 - SP 7 )
Reserved (Must be 0.)
Figure 26. Interrupt Request Register (FAH:
Read/Write)
D6 D5 D4 D3 D2
Figure 30. Stack Pointer (FFH: Read/Write)
PRELIMINARY
29
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
DEVICE CHARACTERISTICS
Standard Mode
Vcc (Volt)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
5.5V
2.0
1.5
3.0V
1.0
.5
-60
-40
-20
0
20
40
60
80
V OL
V IL
100
3.0V
5.5V
Temp
120
(C )
Figure 31. VIL, VOL vs. Temperature
30
PRELIMINARY
DS97DZ80502
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
Standard Mode
1
Vcc (Volt)
6.0
5.5
5.5V
5.0
4.5
4.0
3.5
3.0
5.5V
3.0V
2.5
2.0
3.0V
1.5
1.0
-60
-20
-40
0
40
20
60
80
100
120
Temp
C
VOH Vs Temp
V IH Vs Temp
Figure 32. VIH, VOH vs. Temperature
I OH
(mA)
0
2.0
3.0
4.0
5.0
6.0
VOH
(Volt)
-2.0
-3.0
-4.0
-5.0
-6.0
-7.0 125
25
-40 C
125
25
-40 C
-8.0
3.0V
5.5V
Figure 33. Typical IOH vs. VOH
DS97DZ80502
PRELIMINARY
31
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
Time
(ms)
40
30
20
+105 °C
+25 °C
10
-40 °C
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Voltage
Figure 34. Typical WDT Time Out Period vs. VCC Over Temperature
32
PRELIMINARY
DS97DZ80502
Zilog
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
PACKAGE INFORMATION
1
Figure 35. 18-Pin DIP Package Diagram
Figure 36. 18-Pin SOIC Package Diagram
DS97DZ80502
PRELIMINARY
33
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
ORDERING INFORMATION
Z86C08
(12 MHz)
Standard Temperature
Z86C04
(12 MHz)
Standard Temperature
18-Pin DIP
Z86C0412PSC
Extended Temperature
18-Pin DIP
Z86C0412PEC
Z86C0412PAC
18-Pin SOIC
Z86C0412SSC
18-Pin SOIC
Z86C0412SEC
Z86C0412SAC
18-Pin DIP
Z86C0812PSC
Extended Temperature
18-Pin DIP
Z86C0812PEC
Z86C0812PAC
18-Pin SOIC
Z86C0812SSC
18-Pin SOIC
Z86C0812SEC
Z86C0812SAC
For fast results, contact your local Zilog sale offices for assistance in ordering the part(s) desired.
CODES
Preferred Package
Longer Lead Time
E = –40°C to +105°C
P = DIP
S = SOIC
A = -40°C to +125°C
Preferred Temperature
Speeds
12 = 12 MHz
S = 0°C to +70°C
Environmental
C = Plastic Standard
Example:
Z 86C04 12 P S C
is a Z86C04, 12 MHz, DIP, 0°C to +70°C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
34
PRELIMINARY
DS97DZ80502